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135 changed files with 41867 additions and 25107 deletions
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6
.gitignore vendored
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@ -2,8 +2,6 @@
*.rpt
*.bak
.#*
#*.*#
.*~
/db
/incremental_db
@ -21,15 +19,11 @@ drivers/
HAL/
Part_test/
.metadata/
.settings/
RemoteSystemsTempFiles/
aldec/
cadence/
synopsys/
db/
incremental_db/
*.xml
/testbenches/*.bak
/common_uart/*.bak

242
HDL/IP/sine256.mif
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@ -1,242 +0,0 @@
WIDTH = 8;
DEPTH = 256;
ADDRESS_RADIX = DEC;
DATA_RADIX = HEX;
CONTENT BEGIN
0 : 02;
1 : 05;
2 : 08;
3 : 0B;
4 : 0E;
5 : 11;
6 : 14;
7 : 17;
8 : 1A;
9 : 1D;
10 : 20;
11 : 23;
12 : 26;
13 : 29;
14 : 2C;
15 : 2F;
16 : 32;
17 : 35;
18 : 38;
19 : 3A;
20 : 3D;
21 : 40;
22 : 43;
23 : 45;
24 : 48;
25 : 4A;
26 : 4D;
27 : 4F;
28 : 52;
29 : 54;
30 : 56;
31 : 59;
32 : 5B;
33 : 5D;
34 : 5F;
35 : 61;
36 : 63;
37 : 65;
38 : 67;
39 : 69;
40 : 6A;
41 : 6C;
42 : 6E;
43 : 6F;
44 : 71;
45 : 72;
46 : 73;
47 : 75;
48 : 76;
49 : 77;
50 : 78;
51 : 79;
52 : 7A;
53 : 7B;
54 : 7C;
55 : 7C;
56 : 7D;
57 : 7D;
[58..69] : 7E;
70 : 7D;
71 : 7D;
72 : 7C;
73 : 7C;
74 : 7B;
75 : 7A;
76 : 79;
77 : 78;
78 : 77;
79 : 76;
80 : 75;
81 : 73;
82 : 72;
83 : 71;
84 : 6F;
85 : 6E;
86 : 6C;
87 : 6A;
88 : 69;
89 : 67;
90 : 65;
91 : 63;
92 : 61;
93 : 5F;
94 : 5D;
95 : 5B;
96 : 59;
97 : 56;
98 : 54;
99 : 52;
100 : 4F;
101 : 4D;
102 : 4A;
103 : 48;
104 : 45;
105 : 43;
106 : 40;
107 : 3D;
108 : 3A;
109 : 38;
110 : 35;
111 : 32;
112 : 2F;
113 : 2C;
114 : 29;
115 : 26;
116 : 23;
117 : 20;
118 : 1D;
119 : 1A;
120 : 17;
121 : 14;
122 : 11;
123 : 0E;
124 : 0B;
125 : 08;
126 : 05;
127 : 02;
128 : FE;
129 : FB;
130 : F8;
131 : F5;
132 : F2;
133 : EF;
134 : EC;
135 : E9;
136 : E6;
137 : E3;
138 : E0;
139 : DD;
140 : DA;
141 : D7;
142 : D4;
143 : D1;
144 : CE;
145 : CB;
146 : C8;
147 : C6;
148 : C3;
149 : C0;
150 : BD;
151 : BB;
152 : B8;
153 : B6;
154 : B3;
155 : B1;
156 : AE;
157 : AC;
158 : AA;
159 : A7;
160 : A5;
161 : A3;
162 : A1;
163 : 9F;
164 : 9D;
165 : 9B;
166 : 99;
167 : 97;
168 : 96;
169 : 94;
170 : 92;
171 : 91;
172 : 8F;
173 : 8E;
174 : 8D;
175 : 8B;
176 : 8A;
177 : 89;
178 : 88;
179 : 87;
180 : 86;
181 : 85;
182 : 84;
183 : 84;
184 : 83;
185 : 83;
[186..197] : 82;
198 : 83;
199 : 83;
200 : 84;
201 : 84;
202 : 85;
203 : 86;
204 : 87;
205 : 88;
206 : 89;
207 : 8A;
208 : 8B;
209 : 8D;
210 : 8E;
211 : 8F;
212 : 91;
213 : 92;
214 : 94;
215 : 96;
216 : 97;
217 : 99;
218 : 9B;
219 : 9D;
220 : 9F;
221 : A1;
222 : A3;
223 : A5;
224 : A7;
225 : AA;
226 : AC;
227 : AE;
228 : B1;
229 : B3;
230 : B6;
231 : B8;
232 : BB;
233 : BD;
234 : C0;
235 : C3;
236 : C6;
237 : C8;
238 : CB;
239 : CE;
240 : D1;
241 : D4;
242 : D7;
243 : DA;
244 : DD;
245 : E0;
246 : E3;
247 : E6;
248 : E9;
249 : EC;
250 : EF;
251 : F2;
252 : F5;
253 : F8;
254 : FB;
255 : FE;
END;

5
HDL/IP/sinelut.qip
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@ -1,5 +0,0 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sinelut.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sinelut_bb.v"]

159
HDL/IP/sinelut.v
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@ -1,159 +0,0 @@
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sinelut.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sinelut (
address,
clock,
q);
input [7:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "sine256.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "sine256.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "sine256.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

110
HDL/IP/sinelut_bb.v
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@ -1,110 +0,0 @@
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sinelut.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module sinelut (
address,
clock,
q);
input [7:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "sine256.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "sine256.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

5
HDL/IP/sinelut_inst.v
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@ -1,5 +0,0 @@
sinelut sinelut_inst (
.address ( address_sig ),
.clock ( clock_sig ),
.q ( q_sig )
);

23
HDL/phacc.sv
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@ -1,23 +0,0 @@
module phacc
#(
parameter unsigned WIDTH = 14
) (
input logic [7:0] phinc,
input clk,
input reset,
output [7:0] phase
);
logic [WIDTH - 1 : 0] sum;
always_ff @(posedge clk, negedge reset) begin
if (~reset) begin
sum <= 0;
end else begin
sum <= sum + phinc;
end
end
assign phase = sum[WIDTH - 1 : WIDTH - 8];
endmodule

23
HDL/sdmod.sv
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@ -1,23 +0,0 @@
module sdmod (
input signed [7:0] val,
input clk,
input reset,
output daco
);
logic out;
logic signed [7:0] eps;
logic signed [8:0] un;
always_ff @(posedge clk, negedge reset) begin
if (~reset) begin
un <= 9'd0;
end else begin
un <= val - eps;
end
end
assign out = (un >= $signed(9'd0)) ? 1'd1 : 1'd0;
assign eps = (un >= $signed(9'd0)) ? $signed(9'd126) - un : $signed(-9'd126) - un;
assign daco = out;
endmodule

37
HDL/sigdel.sv
View File

@ -1,37 +0,0 @@
//top-level module
module sigdel
#(
PHACC_WIDTH = 27
) (
//clock and reset
input logic clk, clr_n,
//control slave
input logic [31:0] wr_data,
input logic wr_n,
output logic fout
);
logic [7:0] phinc_val, phase, sine;
//control slave logic
always_ff @ (posedge clk or negedge clr_n) begin
if (!clr_n) begin
phinc_val[7:0] <= 8'd0;
end else begin
if (!wr_n) begin
phinc_val[7:0] <= wr_data[31:0];
end
end
end
phacc phacc_inst (.phinc(1'b1), .clk(clk), .reset(clr_n), .phase(phase));
defparam phacc_inst.WIDTH = PHACC_WIDTH;
sinelut sinelut_inst (
.address (phase), .clock (clk), .q(sine)
);
sdmod sdmod_inst (
.val(sine), .clk(clk), .reset(clr_n), .daco(fout)
);
endmodule

128
Testbench/dec/#dec_tb.sv# Normal file
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@ -0,0 +1,128 @@
`timescale 1 ns/1 ns
module dec_tb();
// Wires and variables to connect to UUT (unit under test)
logic clk, clrn, train;
logic r, y, g;
logic [1:0] div;
logic ctl_wr, ctl_rd;
logic ctl_addr;
logic [31:0] ctl_wrdata;
logic [31:0] ctl_rddata;
logic ram_wr;
logic [3:0] ram_addr;
logic [31:0] ram_wrdata;
logic [31:0] divisor[3:0] = {
{8'd10, 8'd70, 8'd50, 8'd20},
{8'd10, 8'd30, 8'd40, 8'd30},
{8'd10, 8'd30, 8'd10, 8'd100},
{8'd10, 8'd60, 8'd80, 8'd50}
};
// Instantiate UUT
dec my_sem(
.clk(clk), .clrn(clrn),
.ctl_wr(ctl_wr), .ctl_rd(ctl_rd),
.ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
.ram_wr(ram_wr),
.ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
.train(train), .red(r), .yellow(y), .green(g)
);
// Clock definition
initial begin
clk = 0;
forever #10 clk = ~clk;
end
// Divisor and train definition
initial begin
//initial reset
clrn = 0;
div = 0;
train = 0;
//take reset off
@(negedge clk) clrn = 1;
//configure semaphore
for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM
write_reg_transaction(1,div); //write initial divisor
write_reg_transaction(0,1); //enable semaphore
//run trains
repeat (4)
begin
repeat (10) @(posedge clk);
train=1;
repeat (4) @(posedge clk);
train=0;
wait ({r,y,g}==3'b001);
repeat (10) @(posedge clk);
write_reg_transaction(1,div);
div=div+1;
end
//wait a little
repeat (10) @(posedge clk);
$stop;
end
//Single register write transaction task
task write_reg_transaction;
//input signals
input [1:0] offs;
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ctl_wr = 1;
ctl_addr = offs;
ctl_wrdata = val;
@(posedge clk);
//deassert signals
ctl_wr = 0;
ctl_addr = 'bx;
ctl_wrdata = 'bx;
end
endtask
//Single register read transaction task
task read_reg_transaction;
//input signals
input [1:0] offs;
output [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ctl_rd = 1;
ctl_addr = offs;
@(posedge clk);
val = ctl_rddata;
//deassert signals
ctl_rd = 0;
ctl_addr = 'bx;
end
endtask
//RAM write transaction task
task write_ram_transaction;
//input signals
input [1:0] offs;
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ram_wr = 1;
ram_addr = offs;
ram_wrdata = val;
@(posedge clk);
//deassert signals
ram_wr = 0;
ram_addr = 'bx;
ram_wrdata = 'bx;
end
endtask
endmodule

9
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673520674097 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 12 13:51:13 2023 " "Processing started: Thu Jan 12 13:51:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674097 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674098 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\[\"; expecting an operand sigdel.sv(14) " "Verilog HDL syntax error at sigdel.sv(14) near text: \"\[\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 14 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "sigdel sigdel.sv(1) " "Ignored design unit \"sigdel\" at sigdel.sv(1) due to previous errors" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680483 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "923 " "Peak virtual memory: 923 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 12 13:51:20 2023 " "Processing ended: Thu Jan 12 13:51:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680505 ""}

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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="sigdel">
</PROJECT>
</LOG_ROOT>

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Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Version_Index = 486699264
Creation_Time = Mon Jan 16 21:47:58 2023

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|sigdel
phinc[0] => Add0.IN14
phinc[1] => Add0.IN13
phinc[2] => Add0.IN12
phinc[3] => Add0.IN11
phinc[4] => Add0.IN10
phinc[5] => Add0.IN9
phinc[6] => Add0.IN8
phinc[7] => Add0.IN7
clk => acc[0].CLK
clk => acc[1].CLK
clk => acc[2].CLK
clk => acc[3].CLK
clk => acc[4].CLK
clk => acc[5].CLK
clk => acc[6].CLK
clk => acc[7].CLK
clk => acc[8].CLK
clk => acc[9].CLK
clk => acc[10].CLK
clk => acc[11].CLK
clk => acc[12].CLK
clk => acc[13].CLK
clr_n => acc[0].ACLR
clr_n => acc[1].ACLR
clr_n => acc[2].ACLR
clr_n => acc[3].ACLR
clr_n => acc[4].ACLR
clr_n => acc[5].ACLR
clr_n => acc[6].ACLR
clr_n => acc[7].ACLR
clr_n => acc[8].ACLR
clr_n => acc[9].ACLR
clr_n => acc[10].ACLR
clr_n => acc[11].ACLR
clr_n => acc[12].ACLR
clr_n => acc[13].ACLR
phase[0] <= acc[6].DB_MAX_OUTPUT_PORT_TYPE
phase[1] <= acc[7].DB_MAX_OUTPUT_PORT_TYPE
phase[2] <= acc[8].DB_MAX_OUTPUT_PORT_TYPE
phase[3] <= acc[9].DB_MAX_OUTPUT_PORT_TYPE
phase[4] <= acc[10].DB_MAX_OUTPUT_PORT_TYPE
phase[5] <= acc[11].DB_MAX_OUTPUT_PORT_TYPE
phase[6] <= acc[12].DB_MAX_OUTPUT_PORT_TYPE
phase[7] <= acc[13].DB_MAX_OUTPUT_PORT_TYPE

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<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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v1

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673883395012 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 16 18:36:34 2023 " "Processing started: Mon Jan 16 18:36:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel " "Found entity 1: sigdel" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sigdel_tb.sv 1 1 " "Found 1 design units, including 1 entities, in source file sigdel_tb.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel_tb " "Found entity 1: sigdel_tb" { } { { "sigdel_tb.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Testbench/sigdel/sigdel_tb.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "sigdel " "Elaborating entity \"sigdel\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1673883401097 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1673883401388 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1673883401553 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1673883401553 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1673883401619 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1673883401619 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1047 " "Peak virtual memory: 1047 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 16 18:36:41 2023 " "Processing ended: Mon Jan 16 18:36:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401622 ""}

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v1

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FIT

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{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "phase[0]",
"strict" : false
},
{
"name" : "phase[1]",
"strict" : false
},
{
"name" : "phase[2]",
"strict" : false
},
{
"name" : "phase[3]",
"strict" : false
},
{
"name" : "phase[4]",
"strict" : false
},
{
"name" : "phase[5]",
"strict" : false
},
{
"name" : "phase[6]",
"strict" : false
},
{
"name" : "phase[7]",
"strict" : false
},
{
"name" : "clk",
"strict" : false
},
{
"name" : "clr_n",
"strict" : false
},
{
"name" : "phinc[6]",
"strict" : false
},
{
"name" : "phinc[7]",
"strict" : false
},
{
"name" : "phinc[5]",
"strict" : false
},
{
"name" : "phinc[4]",
"strict" : false
},
{
"name" : "phinc[3]",
"strict" : false
},
{
"name" : "phinc[2]",
"strict" : false
},
{
"name" : "phinc[1]",
"strict" : false
},
{
"name" : "phinc[0]",
"strict" : false
}
]
}
]
}

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`timescale 1 ns/1 ns
module inc_lut_tb();
// Parameters
localparam CLK_PRD = 20;
localparam PHACC_WIDTH = 14;
logic clk, clr_n, wr_n;
logic [7:0] phinc_val, phase, sine;
// Instantiate UUT and connect used ports
phacc phacc(.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
defparam phacc.WIDTH = PHACC_WIDTH;
sinelut sinelut_inst (
.address (phase), .clock (clk), .q(sine)
);
// Clock definition
initial begin
clk = 0;
forever #(CLK_PRD/2) clk = ~clk;
end
// Reset and initial values definition
initial begin
clr_n = 0;
#(CLK_PRD*5) clr_n = 1;
end
// Bus write transaction simulation
initial begin
// Wait until system is out of reset
@(posedge clr_n);
phinc_val=(2**(PHACC_WIDTH - 8));
if ((phinc_val <= 255) && (phinc_val != 0)) begin
#(CLK_PRD * 256 * 5) $stop;
end else begin
$display("Error: value of phase increment is out of range! Stopped simulation.");
#1 $stop;
end
end
endmodule

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This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

3
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Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Version_Index = 486699264
Creation_Time = Thu Jan 12 13:26:18 2023

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7aee213afbf8301ed5eefc8c827f49a3

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`timescale 1 ns/1 ns
module lut_mod_tb();
// Parameters
localparam CLK_PRD = 20;
localparam PHACC_WIDTH = 14;
logic clk, clr_n, wr_n, daco;
logic [7:0] phinc_val, phase, sine;
// Instantiate UUT and connect used ports
phacc phacc (
.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase)
);
defparam phacc.WIDTH = PHACC_WIDTH;
sinelut sinelut_inst (
.address(phase), .clock(clk), .q(sine)
);
sdmod sdmod_inst (
.val(sine), .clk(clk), .reset(clr_n), .daco(daco)
// .val(8'd0), .clk(clk), .reset(clr_n), .daco(daco)
// .val(8'd255), .clk(clk), .reset(clr_n), .daco(daco)
);
// Clock definition
initial begin
clk = 0;
forever #(CLK_PRD/2) clk = ~clk;
end
// Reset and initial values definition
initial begin
clr_n = 0;
#(CLK_PRD*5) clr_n = 1;
end
// Bus write transaction simulation
initial begin
// Wait until system is out of reset
@(posedge clr_n);
phinc_val=(2**(PHACC_WIDTH - 8));
if ((phinc_val <= 255) && (phinc_val != 0)) begin
#(CLK_PRD * 256 * 10) $stop;
end else begin
$display("Error: value of phase increment is out of range! Stopped simulation.");
#1 $stop;
end
end
endmodule

30
Testbench/sigdel/sigdel.qpf
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@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 10:16:23 January 27, 2023
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "10:16:23 January 27, 2023"
# Revisions
PROJECT_REVISION = "sigdel"

79
Testbench/sigdel/sigdel.qsf
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@ -1,79 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 10:16:23 January 27, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# sigdel_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE15F23C8
set_global_assignment -name TOP_LEVEL_ENTITY sigdel
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:16:23 JANUARY 27, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH sigdel_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME inc_lut_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id inc_lut_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME inc_lut_tb -section_id inc_lut_tb
set_global_assignment -name EDA_TEST_BENCH_NAME lut_mod_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id lut_mod_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME lut_mod_tb -section_id lut_mod_tb
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/phacc.sv
set_global_assignment -name QIP_FILE ../../HDL/IP/sinelut.qip
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sigdel.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sdmod.sv
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_FILE inc_lut_tb.sv -section_id inc_lut_tb
set_global_assignment -name EDA_TEST_BENCH_FILE lut_mod_tb.sv -section_id lut_mod_tb
set_global_assignment -name EDA_TEST_BENCH_NAME sigdel_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sigdel_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sigdel_tb -section_id sigdel_tb
set_global_assignment -name EDA_TEST_BENCH_FILE sigdel_tb.sv -section_id sigdel_tb
set_location_assignment PIN_T2 -to clk
set_location_assignment PIN_E4 -to clr_n
set_location_assignment PIN_E3 -to fout
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
Testbench/sigdel/sigdel.qws
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Binary file not shown.

37
Testbench/sigdel/sigdel.sv
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@ -1,37 +0,0 @@
//top-level module
module sigdel
#(
PHACC_WIDTH = 14
) (
//clock and reset
input logic clk, clr_n,
//control slave
input logic [31:0] wr_data,
input logic wr_n,
output logic fout
);
logic [7:0] phinc_val;
//control slave logic
always_ff @ (posedge clk or negedge clr_n) begin
if (!clr_n) begin
phinc_val[7:0] <= 8'd0;
end else begin
if (!wr_n) begin
phinc_val[7:0] <= wr_data[31:0];
end
end
end
phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
defparam phacc_inst.WIDTH = PHACC_WIDTH;
sinelut sinelut_inst (
.address (phase), .clock (clk), .q(sine)
);
sdmod sdmod_inst (
.val(sine), .clk(clk), .reset(clr_n), .daco(fout)
);
endmodule

81
Testbench/sigdel/sigdel_tb.sv
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@ -1,81 +0,0 @@
`timescale 1 ns/1 ns
module sigdel_tb();
// Parameters
localparam CLK_PRD = 20;
localparam SAMPLES_PRD = 256;
localparam OVERSAMPLING = 4;
localparam PHACC_WIDTH = 14;
// Wires and variables to connect to UUT (unit under test)
logic clk, clr_n, wr_n;
logic [31:0] wr_data;
logic [31:0] phinc_val;
logic fout;
// Instantiate UUT and connect used ports
sigdel dut(.clk(clk), .clr_n(clr_n), .wr_n(wr_n), .wr_data(wr_data), .fout(fout));
defparam dut.PHACC_WIDTH = PHACC_WIDTH;
// Clock definition
initial begin
clk = 0;
forever #(CLK_PRD/2) clk = ~clk;
end
// Reset and initial values definition
initial begin
clr_n = 0;
wr_n = 1;
wr_data = 'bx;
#(CLK_PRD*5) clr_n = 1;
end
// Bus write transaction simulation
initial begin
// Wait until system is out of reset
@(posedge clr_n);
// Check if phase increment for required accumulator width
// and oversamlpling ratio will fit in 8 bits
phinc_val=(2**(PHACC_WIDTH-8))/OVERSAMPLING;
if ((phinc_val <= 255) && (phinc_val != 0))
begin
// Write phase increment several clock cycles after reset
#(CLK_PRD*3) write_transaction(phinc_val);
// Wait for one sine period (for 14-bit phase accumulator case)
#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
#(CLK_PRD*3) write_transaction(phinc_val*5);
#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
$stop;
end
else
begin
//Output simulation error
$display("Error: value of phase increment is out of range! Stopped simulation.");
//Stop simulation (small delay needed for $display to work)
#1 $stop;
end
end
//Single write transaction task
task write_transaction;
//input signals
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
wr_n = 0;
wr_data = val;
@(posedge clk);
//deassert signals
wr_n = 1;
wr_data = 'bx;
end
endtask
endmodule

242
Testbench/sigdel/sine256.mif
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@ -1,242 +0,0 @@
WIDTH = 8;
DEPTH = 256;
ADDRESS_RADIX = DEC;
DATA_RADIX = HEX;
CONTENT BEGIN
0 : 02;
1 : 05;
2 : 08;
3 : 0B;
4 : 0E;
5 : 11;
6 : 14;
7 : 17;
8 : 1A;
9 : 1D;
10 : 20;
11 : 23;
12 : 26;
13 : 29;
14 : 2C;
15 : 2F;
16 : 32;
17 : 35;
18 : 38;
19 : 3A;
20 : 3D;
21 : 40;
22 : 43;
23 : 45;
24 : 48;
25 : 4A;
26 : 4D;
27 : 4F;
28 : 52;
29 : 54;
30 : 56;
31 : 59;
32 : 5B;
33 : 5D;
34 : 5F;
35 : 61;
36 : 63;
37 : 65;
38 : 67;
39 : 69;
40 : 6A;
41 : 6C;
42 : 6E;
43 : 6F;
44 : 71;
45 : 72;
46 : 73;
47 : 75;
48 : 76;
49 : 77;
50 : 78;
51 : 79;
52 : 7A;
53 : 7B;
54 : 7C;
55 : 7C;
56 : 7D;
57 : 7D;
[58..69] : 7E;
70 : 7D;
71 : 7D;
72 : 7C;
73 : 7C;
74 : 7B;
75 : 7A;
76 : 79;
77 : 78;
78 : 77;
79 : 76;
80 : 75;
81 : 73;
82 : 72;
83 : 71;
84 : 6F;
85 : 6E;
86 : 6C;
87 : 6A;
88 : 69;
89 : 67;
90 : 65;
91 : 63;
92 : 61;
93 : 5F;
94 : 5D;
95 : 5B;
96 : 59;
97 : 56;
98 : 54;
99 : 52;
100 : 4F;
101 : 4D;
102 : 4A;
103 : 48;
104 : 45;
105 : 43;
106 : 40;
107 : 3D;
108 : 3A;
109 : 38;
110 : 35;
111 : 32;
112 : 2F;
113 : 2C;
114 : 29;
115 : 26;
116 : 23;
117 : 20;
118 : 1D;
119 : 1A;
120 : 17;
121 : 14;
122 : 11;
123 : 0E;
124 : 0B;
125 : 08;
126 : 05;
127 : 02;
128 : FE;
129 : FB;
130 : F8;
131 : F5;
132 : F2;
133 : EF;
134 : EC;
135 : E9;
136 : E6;
137 : E3;
138 : E0;
139 : DD;
140 : DA;
141 : D7;
142 : D4;
143 : D1;
144 : CE;
145 : CB;
146 : C8;
147 : C6;
148 : C3;
149 : C0;
150 : BD;
151 : BB;
152 : B8;
153 : B6;
154 : B3;
155 : B1;
156 : AE;
157 : AC;
158 : AA;
159 : A7;
160 : A5;
161 : A3;
162 : A1;
163 : 9F;
164 : 9D;
165 : 9B;
166 : 99;
167 : 97;
168 : 96;
169 : 94;
170 : 92;
171 : 91;
172 : 8F;
173 : 8E;
174 : 8D;
175 : 8B;
176 : 8A;
177 : 89;
178 : 88;
179 : 87;
180 : 86;
181 : 85;
182 : 84;
183 : 84;
184 : 83;
185 : 83;
[186..197] : 82;
198 : 83;
199 : 83;
200 : 84;
201 : 84;
202 : 85;
203 : 86;
204 : 87;
205 : 88;
206 : 89;
207 : 8A;
208 : 8B;
209 : 8D;
210 : 8E;
211 : 8F;
212 : 91;
213 : 92;
214 : 94;
215 : 96;
216 : 97;
217 : 99;
218 : 9B;
219 : 9D;
220 : 9F;
221 : A1;
222 : A3;
223 : A5;
224 : A7;
225 : AA;
226 : AC;
227 : AE;
228 : B1;
229 : B3;
230 : B6;
231 : B8;
232 : BB;
233 : BD;
234 : C0;
235 : C3;
236 : C6;
237 : C8;
238 : CB;
239 : CE;
240 : D1;
241 : D4;
242 : D7;
243 : DA;
244 : DD;
245 : E0;
246 : E3;
247 : E6;
248 : E9;
249 : EC;
250 : EF;
251 : F2;
252 : F5;
253 : F8;
254 : FB;
255 : FE;
END;

151
Top/#niosII_tb.csv# Normal file
View File

@ -0,0 +1,151 @@
# system info niosII_tb on 2022.10.24.18:26:01
system_info:
name,value
DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1666621532
#
#
# Files generated for niosII_tb on 2022.10.24.18:26:01
files:
filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_002,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_004,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_008,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_demux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
niosII_tb.niosII_inst,niosII
niosII_tb.niosII_inst.cpu,niosII_cpu
niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
niosII_tb.niosII_inst.mem,niosII_mem
niosII_tb.niosII_inst.sem,dec
niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.router,niosII_mm_interconnect_0_router
niosII_tb.niosII_inst.mm_interconnect_0.router_001,niosII_mm_interconnect_0_router_001
niosII_tb.niosII_inst.mm_interconnect_0.router_002,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_003,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_005,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_006,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_007,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_004,niosII_mm_interconnect_0_router_004
niosII_tb.niosII_inst.mm_interconnect_0.router_008,niosII_mm_interconnect_0_router_008
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux,niosII_mm_interconnect_0_cmd_demux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux_001,niosII_mm_interconnect_0_cmd_demux_001
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_002,niosII_mm_interconnect_0_cmd_demux_001
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_001,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_003,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_004,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_005,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_006,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_002,niosII_mm_interconnect_0_cmd_mux_002
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_001,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_003,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_004,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_005,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_006,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux,niosII_mm_interconnect_0_rsp_mux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux_001,niosII_mm_interconnect_0_rsp_mux_001
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
niosII_tb.niosII_inst.rst_controller,altera_reset_controller
niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source

87
Top/niosII.qsys
View File

@ -29,7 +29,7 @@
{
datum baseAddress
{
value = "34816";
value = "133120";
type = "String";
}
}
@ -45,7 +45,7 @@
{
datum baseAddress
{
value = "36896";
value = "135272";
type = "String";
}
}
@ -105,15 +105,7 @@
type = "String";
}
}
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element sigdel_0
element sem
{
datum _sortIndex
{
@ -121,11 +113,19 @@
type = "int";
}
}
element sigdel_0.avalon_slave
element sem.ctl_slave
{
datum baseAddress
{
value = "36904";
value = "135264";
type = "String";
}
}
element sem.ram_slave
{
datum baseAddress
{
value = "135168";
type = "String";
}
}
@ -141,16 +141,16 @@
{
datum baseAddress
{
value = "36864";
value = "135232";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE15F23C8" />
<parameter name="device" value="EP4CE115F29C7" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="8" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@ -167,12 +167,8 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk.clk_in" type="clock" dir="end" />
<interface
name="conduit_end"
internal="sigdel_0.conduit_end"
type="conduit"
dir="end" />
<interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end" />
<interface name="sem_export" internal="sem.sem" type="conduit" dir="end" />
<module name="clk" kind="clock_source" version="18.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
@ -182,8 +178,8 @@
<module name="cpu" kind="altera_nios2_gen2" version="18.1" enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_DEVICE" value="EP4CE15F23C8" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
<parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
<parameter name="breakSlave" value="None" />
@ -196,10 +192,10 @@
<parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
<parameter name="dataAddrWidth" value="16" />
<parameter name="dataAddrWidth" value="18" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@ -237,8 +233,8 @@
<parameter name="icache_size" value="4096" />
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Tiny" />
<parameter name="instAddrWidth" value="16" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
<parameter name="instAddrWidth" value="18" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
@ -396,7 +392,7 @@
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="32768" />
<parameter name="memorySize" value="131072" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
@ -408,8 +404,8 @@
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
<module name="sigdel_0" kind="sigdel" version="1.0" enabled="1">
<parameter name="PHACC_WIDTH" value="26" />
<module name="sem" kind="sem" version="1.1" enabled="1">
<parameter name="m" value="32" />
</module>
<module
name="sys_clk_timer"
@ -433,16 +429,16 @@
start="cpu.data_master"
end="jtag_uart.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x9020" />
<parameter name="baseAddress" value="0x00021068" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="18.1"
start="cpu.data_master"
end="sigdel_0.avalon_slave">
end="sem.ctl_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x9028" />
<parameter name="baseAddress" value="0x00021060" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -451,7 +447,16 @@
start="cpu.data_master"
end="cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8800" />
<parameter name="baseAddress" value="0x00020800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="18.1"
start="cpu.data_master"
end="sem.ram_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -460,7 +465,7 @@
start="cpu.data_master"
end="sys_clk_timer.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x9000" />
<parameter name="baseAddress" value="0x00021040" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2">
@ -474,7 +479,7 @@
start="cpu.instruction_master"
end="cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x8800" />
<parameter name="baseAddress" value="0x00020800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -490,7 +495,7 @@
<connection kind="clock" version="18.1" start="clk.clk" end="jtag_uart.clk" />
<connection kind="clock" version="18.1" start="clk.clk" end="sys_clk_timer.clk" />
<connection kind="clock" version="18.1" start="clk.clk" end="mem.clk1" />
<connection kind="clock" version="18.1" start="clk.clk" end="sigdel_0.clock" />
<connection kind="clock" version="18.1" start="clk.clk" end="sem.clock" />
<connection
kind="interrupt"
version="18.1"
@ -513,11 +518,7 @@
start="clk.clk_reset"
end="sys_clk_timer.reset" />
<connection kind="reset" version="18.1" start="clk.clk_reset" end="mem.reset1" />
<connection
kind="reset"
version="18.1"
start="clk.clk_reset"
end="sigdel_0.reset_sink" />
<connection kind="reset" version="18.1" start="clk.clk_reset" end="sem.reset_n" />
<connection
kind="reset"
version="18.1"
@ -542,7 +543,7 @@
kind="reset"
version="18.1"
start="cpu.debug_reset_request"
end="sigdel_0.reset_sink" />
end="sem.reset_n" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />

848
Top/niosII.sopcinfo
View File

File diff suppressed because one or more lines are too long

164
Top/niosII/niosII.bsf
View File

@ -1,70 +1,94 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 496 184)
(text "niosII" (rect 234 -1 254 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 20 180)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 192 72)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 192 152)(line_width 1))
)
(port
(pt 0 112)
(output)
(text "conduit_end_writeresponsevalid_n" (rect 0 0 135 12)(font "Arial" (font_size 8)))
(text "conduit_end_writeresponsevalid_n" (rect 4 101 196 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 192 112)(line_width 1))
)
(drawing
(text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 197 67 412 144)(font "Arial" (color 0 0 0)))
(text "conduit_end" (rect 123 83 312 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "writeresponsevalid_n" (rect 197 107 514 224)(font "Arial" (color 0 0 0)))
(text "reset" (rect 163 123 356 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 197 147 436 304)(font "Arial" (color 0 0 0)))
(text " niosII " (rect 470 168 988 346)(font "Arial" ))
(line (pt 192 32)(pt 304 32)(line_width 1))
(line (pt 304 32)(pt 304 168)(line_width 1))
(line (pt 192 168)(pt 304 168)(line_width 1))
(line (pt 192 32)(pt 192 168)(line_width 1))
(line (pt 193 52)(pt 193 76)(line_width 1))
(line (pt 194 52)(pt 194 76)(line_width 1))
(line (pt 193 92)(pt 193 116)(line_width 1))
(line (pt 194 92)(pt 194 116)(line_width 1))
(line (pt 193 132)(pt 193 156)(line_width 1))
(line (pt 194 132)(pt 194 156)(line_width 1))
(line (pt 0 0)(pt 496 0)(line_width 1))
(line (pt 496 0)(pt 496 184)(line_width 1))
(line (pt 0 184)(pt 496 184)(line_width 1))
(line (pt 0 0)(pt 0 184)(line_width 1))
)
)
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 288 232)
(text "niosII" (rect 130 -1 150 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 216 20 228)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 112 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 112 112)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "sem_export_train" (rect 0 0 70 12)(font "Arial" (font_size 8)))
(text "sem_export_train" (rect 4 141 100 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 112 152)(line_width 1))
)
(port
(pt 0 168)
(output)
(text "sem_export_red" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "sem_export_red" (rect 4 157 88 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 112 168)(line_width 1))
)
(port
(pt 0 184)
(output)
(text "sem_export_yellow" (rect 0 0 77 12)(font "Arial" (font_size 8)))
(text "sem_export_yellow" (rect 4 173 106 184)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 112 184)(line_width 1))
)
(port
(pt 0 200)
(output)
(text "sem_export_green" (rect 0 0 76 12)(font "Arial" (font_size 8)))
(text "sem_export_green" (rect 4 189 100 200)(font "Arial" (font_size 8)))
(line (pt 0 200)(pt 112 200)(line_width 1))
)
(drawing
(text "clk" (rect 97 43 212 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 117 67 252 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 83 83 196 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 117 107 276 224)(font "Arial" (color 0 0 0)))
(text "sem_export" (rect 44 123 148 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "train" (rect 117 147 264 304)(font "Arial" (color 0 0 0)))
(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
(text " niosII " (rect 262 216 572 442)(font "Arial" ))
(line (pt 112 32)(pt 176 32)(line_width 1))
(line (pt 176 32)(pt 176 216)(line_width 1))
(line (pt 112 216)(pt 176 216)(line_width 1))
(line (pt 112 32)(pt 112 216)(line_width 1))
(line (pt 113 52)(pt 113 76)(line_width 1))
(line (pt 114 52)(pt 114 76)(line_width 1))
(line (pt 113 92)(pt 113 116)(line_width 1))
(line (pt 114 92)(pt 114 116)(line_width 1))
(line (pt 113 132)(pt 113 204)(line_width 1))
(line (pt 114 132)(pt 114 204)(line_width 1))
(line (pt 0 0)(pt 288 0)(line_width 1))
(line (pt 288 0)(pt 288 232)(line_width 1))
(line (pt 0 232)(pt 288 232)(line_width 1))
(line (pt 0 0)(pt 0 232)(line_width 1))
)
)

15
Top/niosII/niosII.cmp
View File

@ -1,8 +1,11 @@
component niosII is
component niosII is
port (
clk_clk : in std_logic := 'X'; -- clk
conduit_end_writeresponsevalid_n : out std_logic; -- writeresponsevalid_n
reset_reset_n : in std_logic := 'X' -- reset_n
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sem_export_train : in std_logic := 'X'; -- train
sem_export_red : out std_logic; -- red
sem_export_yellow : out std_logic; -- yellow
sem_export_green : out std_logic -- green
);
end component niosII;
end component niosII;

99
Top/niosII/niosII.html
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2023.02.07.17:03:00</td>
<td class="l">2023.01.17.19:00:54</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -100,8 +100,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a href="#module_mem"><b>mem</b>
</a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160;
<a href="#module_sigdel_0"><b>sigdel_0</b>
</a> sigdel 1.0
<a href="#module_sem"><b>sem</b>
</a> sem 1.1
<br/>&#160;&#160;
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span>
@ -131,8 +131,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="slaveb">debug_mem_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00008800</td>
<td class="addr"><span style="color:#989898">0x</span>00008800</td>
<td class="addr"><span style="color:#989898">0x</span>00020800</td>
<td class="addr"><span style="color:#989898">0x</span>00020800</td>
</tr>
<tr>
<td class="slavemodule">&#160;
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="slaveb">avalon_jtag_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00009020</td>
<td class="addr"><span style="color:#989898">0x</span>00021068</td>
<td class="empty"></td>
</tr>
<tr>
@ -167,15 +167,20 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_sigdel_0"><b>sigdel_0</b>
<a href="#module_sem"><b>sem</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slaveb">avalon_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00009028</td>
<td class="slavem">ctl_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021060</td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavem">ram_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
<td class="empty"></td>
</tr>
<tr>
@ -188,7 +193,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="slaveb">s1&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00009000</td>
<td class="addr"><span style="color:#989898">0x</span>00021040</td>
<td class="empty"></td>
</tr>
</table>
@ -251,7 +256,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a href="#module_clk">clk</a>
</td>
<td class="from">clk&#160;&#160;</td>
<td class="main" rowspan="29">cpu</td>
<td class="main" rowspan="31">cpu</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
@ -302,14 +307,24 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
<td class="neighbor" rowspan="4">
<a href="#module_sigdel_0">sigdel_0</a>
<td class="neighbor" rowspan="6">
<a href="#module_sem">sem</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;avalon_slave</td>
<td class="to">&#160;&#160;ctl_slave</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;ram_slave</td>
</tr>
<tr>
<td></td>
@ -319,7 +334,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;reset_sink</td>
<td class="to">&#160;&#160;reset_n</td>
</tr>
<tr style="height:6px">
<td></td>
@ -976,7 +991,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">breakAbsoluteAddr</td>
<td class="parametervalue">34848</td>
<td class="parametervalue">133152</td>
</tr>
<tr>
<td class="parametername">mmu_TLBMissExcAbsAddr</td>
@ -1032,7 +1047,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">instAddrWidth</td>
<td class="parametervalue">16</td>
<td class="parametervalue">18</td>
</tr>
<tr>
<td class="parametername">faAddrWidth</td>
@ -1040,7 +1055,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">dataAddrWidth</td>
<td class="parametervalue">16</td>
<td class="parametervalue">18</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0AddrWidth</td>
@ -1084,7 +1099,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">instSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td>
</tr>
<tr>
<td class="parametername">faSlaveMapParam</td>
@ -1092,7 +1107,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /&gt;&lt;/address-map&gt;</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -1168,11 +1183,11 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">AUTO_DEVICE</td>
<td class="parametervalue">EP4CE15F23C8</td>
<td class="parametervalue">EP4CE115F29C7</td>
</tr>
<tr>
<td class="parametername">AUTO_DEVICE_SPEEDGRADE</td>
<td class="parametervalue">8</td>
<td class="parametervalue">7</td>
</tr>
<tr>
<td class="parametername">AUTO_CLK_CLOCK_DOMAIN</td>
@ -1205,7 +1220,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">BREAK_ADDR</td>
<td class="parametervalue">0x00008820</td>
<td class="parametervalue">0x00020820</td>
</tr>
<tr>
<td class="parametername">CPU_ARCH_NIOS2_R1</td>
@ -1229,7 +1244,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">DATA_ADDR_WIDTH</td>
<td class="parametervalue">16</td>
<td class="parametervalue">18</td>
</tr>
<tr>
<td class="parametername">DCACHE_LINE_SIZE</td>
@ -1301,7 +1316,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">INST_ADDR_WIDTH</td>
<td class="parametervalue">16</td>
<td class="parametervalue">18</td>
</tr>
<tr>
<td class="parametername">OCI_VERSION</td>
@ -1576,7 +1591,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">memorySize</td>
<td class="parametervalue">32768</td>
<td class="parametervalue">131072</td>
</tr>
<tr>
<td class="parametername">readDuringWriteMode</td>
@ -1644,11 +1659,11 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">derived_set_addr_width</td>
<td class="parametervalue">13</td>
<td class="parametervalue">15</td>
</tr>
<tr>
<td class="parametername">derived_set_addr_width2</td>
<td class="parametervalue">13</td>
<td class="parametervalue">15</td>
</tr>
<tr>
<td class="parametername">derived_set_data_width</td>
@ -1737,7 +1752,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">SIZE_VALUE</td>
<td class="parametervalue">32768</td>
<td class="parametervalue">131072</td>
</tr>
<tr>
<td class="parametername">WRITABLE</td>
@ -1748,28 +1763,34 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
</table>
</div>
<a name="module_sigdel_0"> </a>
<a name="module_sem"> </a>
<div>
<hr/>
<h2>sigdel_0</h2>sigdel v1.0
<h2>sem</h2>sem v1.1
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="4">
<td class="neighbor" rowspan="6">
<a href="#module_cpu">cpu</a>
</td>
<td class="from">data_master&#160;&#160;</td>
<td class="main" rowspan="9">sigdel_0</td>
<td class="main" rowspan="11">sem</td>
</tr>
<tr>
<td class="to">&#160;&#160;avalon_slave</td>
<td class="to">&#160;&#160;ctl_slave</td>
</tr>
<tr>
<td class="from">data_master&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;ram_slave</td>
</tr>
<tr>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset_sink</td>
<td class="to">&#160;&#160;reset_n</td>
</tr>
<tr style="height:6px">
<td></td>
@ -1787,7 +1808,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<td class="from">clk_reset&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset_sink</td>
<td class="to">&#160;&#160;reset_n</td>
</tr>
</table>
</div>
@ -1799,8 +1820,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">PHACC_WIDTH</td>
<td class="parametervalue">26</td>
<td class="parametername">m</td>
<td class="parametervalue">32</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
@ -2018,7 +2039,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.03 seconds</td>
<td class="r">rendering took 0.02 seconds</td>
</tr>
</table>
</body>

962
Top/niosII/niosII.xml
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12
Top/niosII/niosII_bb.v
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@ -1,10 +1,16 @@
module niosII (
clk_clk,
conduit_end_writeresponsevalid_n,
reset_reset_n);
reset_reset_n,
sem_export_train,
sem_export_red,
sem_export_yellow,
sem_export_green);
input clk_clk;
output conduit_end_writeresponsevalid_n;
input reset_reset_n;
input sem_export_train;
output sem_export_red;
output sem_export_yellow;
output sem_export_green;
endmodule

13
Top/niosII/niosII_inst.v
View File

@ -1,6 +1,9 @@
niosII u0 (
.clk_clk (<connected-to-clk_clk>), // clk.clk
.conduit_end_writeresponsevalid_n (<connected-to-conduit_end_writeresponsevalid_n>), // conduit_end.writeresponsevalid_n
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
);
.clk_clk (<connected-to-clk_clk>), // clk.clk
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
.sem_export_train (<connected-to-sem_export_train>), // sem_export.train
.sem_export_red (<connected-to-sem_export_red>), // .red
.sem_export_yellow (<connected-to-sem_export_yellow>), // .yellow
.sem_export_green (<connected-to-sem_export_green>) // .green
);

28
Top/niosII/niosII_inst.vhd
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@ -1,15 +1,21 @@
component niosII is
component niosII is
port (
clk_clk : in std_logic := 'X'; -- clk
conduit_end_writeresponsevalid_n : out std_logic; -- writeresponsevalid_n
reset_reset_n : in std_logic := 'X' -- reset_n
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sem_export_train : in std_logic := 'X'; -- train
sem_export_red : out std_logic; -- red
sem_export_yellow : out std_logic; -- yellow
sem_export_green : out std_logic -- green
);
end component niosII;
u0 : component niosII
end component niosII;
u0 : component niosII
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
conduit_end_writeresponsevalid_n => CONNECTED_TO_conduit_end_writeresponsevalid_n, -- conduit_end.writeresponsevalid_n
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sem_export_train => CONNECTED_TO_sem_export_train, -- sem_export.train
sem_export_red => CONNECTED_TO_sem_export_red, -- .red
sem_export_yellow => CONNECTED_TO_sem_export_yellow, -- .yellow
sem_export_green => CONNECTED_TO_sem_export_green -- .green
);

1040
Top/niosII/synthesis/niosII.debuginfo
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435
Top/niosII/synthesis/niosII.qip
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64
Top/niosII/synthesis/niosII.v
View File

@ -4,22 +4,25 @@
`timescale 1 ps / 1 ps
module niosII (
input wire clk_clk, // clk.clk
output wire conduit_end_writeresponsevalid_n, // conduit_end.writeresponsevalid_n
input wire reset_reset_n // reset.reset_n
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
input wire sem_export_train, // sem_export.train
output wire sem_export_red, // .red
output wire sem_export_yellow, // .yellow
output wire sem_export_green // .green
);
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [15:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire [17:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [15:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire [17:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
@ -28,8 +31,11 @@ module niosII (
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire mm_interconnect_0_sigdel_0_avalon_slave_write; // mm_interconnect_0:sigdel_0_avalon_slave_write -> sigdel_0:wr_n
wire [31:0] mm_interconnect_0_sigdel_0_avalon_slave_writedata; // mm_interconnect_0:sigdel_0_avalon_slave_writedata -> sigdel_0:wr_data
wire [31:0] mm_interconnect_0_sem_ctl_slave_readdata; // sem:ctl_rddata -> mm_interconnect_0:sem_ctl_slave_readdata
wire [0:0] mm_interconnect_0_sem_ctl_slave_address; // mm_interconnect_0:sem_ctl_slave_address -> sem:ctl_addr
wire mm_interconnect_0_sem_ctl_slave_read; // mm_interconnect_0:sem_ctl_slave_read -> sem:ctl_rd
wire mm_interconnect_0_sem_ctl_slave_write; // mm_interconnect_0:sem_ctl_slave_write -> sem:ctl_wr
wire [31:0] mm_interconnect_0_sem_ctl_slave_writedata; // mm_interconnect_0:sem_ctl_slave_writedata -> sem:ctl_wrdata
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_readdata; // cpu:debug_mem_slave_readdata -> mm_interconnect_0:cpu_debug_mem_slave_readdata
wire mm_interconnect_0_cpu_debug_mem_slave_waitrequest; // cpu:debug_mem_slave_waitrequest -> mm_interconnect_0:cpu_debug_mem_slave_waitrequest
wire mm_interconnect_0_cpu_debug_mem_slave_debugaccess; // mm_interconnect_0:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess
@ -38,6 +44,9 @@ module niosII (
wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
wire [3:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr
wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr
wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata
wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
wire [15:0] mm_interconnect_0_sys_clk_timer_s1_readdata; // sys_clk_timer:readdata -> mm_interconnect_0:sys_clk_timer_s1_readdata
wire [2:0] mm_interconnect_0_sys_clk_timer_s1_address; // mm_interconnect_0:sys_clk_timer_s1_address -> sys_clk_timer:address
@ -45,14 +54,14 @@ module niosII (
wire [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata; // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata
wire mm_interconnect_0_mem_s2_chipselect; // mm_interconnect_0:mem_s2_chipselect -> mem:chipselect2
wire [31:0] mm_interconnect_0_mem_s2_readdata; // mem:readdata2 -> mm_interconnect_0:mem_s2_readdata
wire [12:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2
wire [14:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2
wire [3:0] mm_interconnect_0_mem_s2_byteenable; // mm_interconnect_0:mem_s2_byteenable -> mem:byteenable2
wire mm_interconnect_0_mem_s2_write; // mm_interconnect_0:mem_s2_write -> mem:write2
wire [31:0] mm_interconnect_0_mem_s2_writedata; // mm_interconnect_0:mem_s2_writedata -> mem:writedata2
wire mm_interconnect_0_mem_s2_clken; // mm_interconnect_0:mem_s2_clken -> mem:clken2
wire mm_interconnect_0_mem_s1_chipselect; // mm_interconnect_0:mem_s1_chipselect -> mem:chipselect
wire [31:0] mm_interconnect_0_mem_s1_readdata; // mem:readdata -> mm_interconnect_0:mem_s1_readdata
wire [12:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address
wire [14:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address
wire [3:0] mm_interconnect_0_mem_s1_byteenable; // mm_interconnect_0:mem_s1_byteenable -> mem:byteenable
wire mm_interconnect_0_mem_s1_write; // mm_interconnect_0:mem_s1_write -> mem:write
wire [31:0] mm_interconnect_0_mem_s1_writedata; // mm_interconnect_0:mem_s1_writedata -> mem:writedata
@ -60,7 +69,7 @@ module niosII (
wire irq_mapper_receiver0_irq; // sys_clk_timer:irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq
wire [31:0] cpu_irq_irq; // irq_mapper:sender_irq -> cpu:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sigdel_0:clr_n, sys_clk_timer:reset_n]
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu:reset_req, mem:reset_req, rst_translator:reset_req_in]
wire cpu_debug_reset_request_reset; // cpu:debug_reset_request -> rst_controller:reset_in1
@ -127,14 +136,23 @@ module niosII (
.freeze (1'b0) // (terminated)
);
sigdel #(
.PHACC_WIDTH (26)
) sigdel_0 (
.clk (clk_clk), // clock.clk
.clr_n (~rst_controller_reset_out_reset), // reset_sink.reset_n
.fout (conduit_end_writeresponsevalid_n), // conduit_end.writeresponsevalid_n
.wr_n (~mm_interconnect_0_sigdel_0_avalon_slave_write), // avalon_slave.write_n
.wr_data (mm_interconnect_0_sigdel_0_avalon_slave_writedata) // .writedata
dec #(
.m (32)
) sem (
.clk (clk_clk), // clock.clk
.ctl_wr (mm_interconnect_0_sem_ctl_slave_write), // ctl_slave.write
.ctl_rd (mm_interconnect_0_sem_ctl_slave_read), // .read
.ctl_addr (mm_interconnect_0_sem_ctl_slave_address), // .address
.ctl_wrdata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
.ctl_rddata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
.clrn (~rst_controller_reset_out_reset), // reset_n.reset_n
.ram_wr (mm_interconnect_0_sem_ram_slave_write), // ram_slave.write
.ram_addr (mm_interconnect_0_sem_ram_slave_address), // .address
.ram_wrdata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
.train (sem_export_train), // sem.train
.red (sem_export_red), // .red
.yellow (sem_export_yellow), // .yellow
.green (sem_export_green) // .green
);
niosII_sys_clk_timer sys_clk_timer (
@ -192,8 +210,14 @@ module niosII (
.mem_s2_byteenable (mm_interconnect_0_mem_s2_byteenable), // .byteenable
.mem_s2_chipselect (mm_interconnect_0_mem_s2_chipselect), // .chipselect
.mem_s2_clken (mm_interconnect_0_mem_s2_clken), // .clken
.sigdel_0_avalon_slave_write (mm_interconnect_0_sigdel_0_avalon_slave_write), // sigdel_0_avalon_slave.write
.sigdel_0_avalon_slave_writedata (mm_interconnect_0_sigdel_0_avalon_slave_writedata), // .writedata
.sem_ctl_slave_address (mm_interconnect_0_sem_ctl_slave_address), // sem_ctl_slave.address
.sem_ctl_slave_write (mm_interconnect_0_sem_ctl_slave_write), // .write
.sem_ctl_slave_read (mm_interconnect_0_sem_ctl_slave_read), // .read
.sem_ctl_slave_readdata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
.sem_ctl_slave_writedata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
.sem_ram_slave_address (mm_interconnect_0_sem_ram_slave_address), // sem_ram_slave.address
.sem_ram_slave_write (mm_interconnect_0_sem_ram_slave_write), // .write
.sem_ram_slave_writedata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
.sys_clk_timer_s1_address (mm_interconnect_0_sys_clk_timer_s1_address), // sys_clk_timer_s1.address
.sys_clk_timer_s1_write (mm_interconnect_0_sys_clk_timer_s1_write), // .write
.sys_clk_timer_s1_readdata (mm_interconnect_0_sys_clk_timer_s1_readdata), // .readdata

1830
Top/niosII/synthesis/submodules/altera_avalon_sc_fifo.v
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File diff suppressed because it is too large Load Diff

518
Top/niosII/synthesis/submodules/altera_merlin_arbitrator.sv
View File

@ -11,262 +11,262 @@
// agreement for further details.
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
// $Revision: #3 $
// $Date: 2010/07/07 $
// $Author: jyeap $
/* -----------------------------------------------------------------------
Round-robin/fixed arbitration implementation.
Q: how do you find the least-significant set-bit in an n-bit binary number, X?
A: M = X & (~X + 1)
Example: X = 101000100
101000100 &
010111011 + 1 =
101000100 &
010111100 =
-----------
000000100
The method can be generalized to find the first set-bit
at a bit index no lower than bit-index N, simply by adding
2**N rather than 1.
Q: how does this relate to round-robin arbitration?
A:
Let X be the concatenation of all request signals.
Let the number to be added to X (hereafter called the
top_priority) initialize to 1, and be assigned from the
concatenation of the previous saved-grant, left-rotated
by one position, each time arbitration occurs. The
concatenation of grants is then M.
Problem: consider this case:
top_priority = 010000
request = 001001
~request + top_priority = 000110
next_grant = 000000 <- no one is granted!
There was no "set bit at a bit index no lower than bit-index 4", so
the result was 0.
We need to propagate the carry out from (~request + top_priority) to the LSB, so
that the sum becomes 000111, and next_grant is 000001. This operation could be
called a "circular add".
A bit of experimentation on the circular add reveals a significant amount of
delay in exiting and re-entering the carry chain - this will vary with device
family. Quartus also reports a combinational loop warning. Finally,
Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
Modelsim _doesn't_ report a combinational loop!)
An alternate solution: concatenate the request vector with itself, and OR
corresponding bits from the top and bottom halves to determine next_grant.
Example:
top_priority = 010000
{request, request} = 001001 001001
{~request, ~request} + top_priority = 110111 000110
result of & operation = 000001 000000
next_grant = 000001
Notice that if request = 0, the sum operation will overflow, but we can ignore
this; the next_grant result is 0 (no one granted), as you might expect.
In the implementation, the last-granted value must be maintained as
a non-zero value - best probably simply not to update it when no requests
occur.
----------------------------------------------------------------------- */
`timescale 1 ns / 1 ns
module altera_merlin_arbitrator
#(
parameter NUM_REQUESTERS = 8,
// --------------------------------------
// Implemented schemes
// "round-robin"
// "fixed-priority"
// "no-arb"
// --------------------------------------
parameter SCHEME = "round-robin",
parameter PIPELINE = 0
)
(
input clk,
input reset,
// --------------------------------------
// Requests
// --------------------------------------
input [NUM_REQUESTERS-1:0] request,
// --------------------------------------
// Grants
// --------------------------------------
output [NUM_REQUESTERS-1:0] grant,
// --------------------------------------
// Control Signals
// --------------------------------------
input increment_top_priority,
input save_top_priority
);
// --------------------------------------
// Signals
// --------------------------------------
wire [NUM_REQUESTERS-1:0] top_priority;
reg [NUM_REQUESTERS-1:0] top_priority_reg;
reg [NUM_REQUESTERS-1:0] last_grant;
wire [2*NUM_REQUESTERS-1:0] result;
// --------------------------------------
// Scheme Selection
// --------------------------------------
generate
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
assign top_priority = top_priority_reg;
end
else begin
// Fixed arbitration (or single-requester corner case)
assign top_priority = 1'b1;
end
endgenerate
// --------------------------------------
// Decision Logic
// --------------------------------------
altera_merlin_arb_adder
#(
.WIDTH (2 * NUM_REQUESTERS)
)
adder
(
.a ({ ~request, ~request }),
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
.sum (result)
);
generate if (SCHEME == "no-arb") begin
// --------------------------------------
// No arbitration: just wire request directly to grant
// --------------------------------------
assign grant = request;
end else begin
// Do the math in double-vector domain
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
assign grant_double_vector = {request, request} & result;
// --------------------------------------
// Extract grant from the top and bottom halves
// of the double vector.
// --------------------------------------
assign grant =
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
end
endgenerate
// --------------------------------------
// Left-rotate the last grant vector to create top_priority.
// --------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
top_priority_reg <= 1'b1;
end
else begin
if (PIPELINE) begin
if (increment_top_priority) begin
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1]} : top_priority_reg;
end
end else begin
if (increment_top_priority) begin
if (|request)
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1] };
else
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
end
else if (save_top_priority) begin
top_priority_reg <= grant;
end
end
end
end
endmodule
// ----------------------------------------------
// Adder for the standard arbitrator
// ----------------------------------------------
module altera_merlin_arb_adder
#(
parameter WIDTH = 8
)
(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] sum
);
wire [WIDTH:0] sum_lint;
// ----------------------------------------------
// Benchmarks indicate that for small widths, the full
// adder has higher fmax because synthesis can merge
// it with the mux, allowing partial decisions to be
// made early.
//
// The magic number is 4 requesters, which means an
// 8 bit adder.
// ----------------------------------------------
genvar i;
generate if (WIDTH <= 8) begin : full_adder
wire cout[WIDTH-1:0];
assign sum[0] = (a[0] ^ b[0]);
assign cout[0] = (a[0] & b[0]);
for (i = 1; i < WIDTH; i = i+1) begin : arb
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
end
end else begin : carry_chain
assign sum_lint = a + b;
assign sum = sum_lint[WIDTH-1:0];
end
endgenerate
endmodule
// (C) 2001-2010 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/merlin/altera_merlin_std_arbitrator/altera_merlin_std_arbitrator_core.sv#3 $
// $Revision: #3 $
// $Date: 2010/07/07 $
// $Author: jyeap $
/* -----------------------------------------------------------------------
Round-robin/fixed arbitration implementation.
Q: how do you find the least-significant set-bit in an n-bit binary number, X?
A: M = X & (~X + 1)
Example: X = 101000100
101000100 &
010111011 + 1 =
101000100 &
010111100 =
-----------
000000100
The method can be generalized to find the first set-bit
at a bit index no lower than bit-index N, simply by adding
2**N rather than 1.
Q: how does this relate to round-robin arbitration?
A:
Let X be the concatenation of all request signals.
Let the number to be added to X (hereafter called the
top_priority) initialize to 1, and be assigned from the
concatenation of the previous saved-grant, left-rotated
by one position, each time arbitration occurs. The
concatenation of grants is then M.
Problem: consider this case:
top_priority = 010000
request = 001001
~request + top_priority = 000110
next_grant = 000000 <- no one is granted!
There was no "set bit at a bit index no lower than bit-index 4", so
the result was 0.
We need to propagate the carry out from (~request + top_priority) to the LSB, so
that the sum becomes 000111, and next_grant is 000001. This operation could be
called a "circular add".
A bit of experimentation on the circular add reveals a significant amount of
delay in exiting and re-entering the carry chain - this will vary with device
family. Quartus also reports a combinational loop warning. Finally,
Modelsim 6.3g has trouble with the expression, evaluating it to 'X'. But
Modelsim _doesn't_ report a combinational loop!)
An alternate solution: concatenate the request vector with itself, and OR
corresponding bits from the top and bottom halves to determine next_grant.
Example:
top_priority = 010000
{request, request} = 001001 001001
{~request, ~request} + top_priority = 110111 000110
result of & operation = 000001 000000
next_grant = 000001
Notice that if request = 0, the sum operation will overflow, but we can ignore
this; the next_grant result is 0 (no one granted), as you might expect.
In the implementation, the last-granted value must be maintained as
a non-zero value - best probably simply not to update it when no requests
occur.
----------------------------------------------------------------------- */
`timescale 1 ns / 1 ns
module altera_merlin_arbitrator
#(
parameter NUM_REQUESTERS = 8,
// --------------------------------------
// Implemented schemes
// "round-robin"
// "fixed-priority"
// "no-arb"
// --------------------------------------
parameter SCHEME = "round-robin",
parameter PIPELINE = 0
)
(
input clk,
input reset,
// --------------------------------------
// Requests
// --------------------------------------
input [NUM_REQUESTERS-1:0] request,
// --------------------------------------
// Grants
// --------------------------------------
output [NUM_REQUESTERS-1:0] grant,
// --------------------------------------
// Control Signals
// --------------------------------------
input increment_top_priority,
input save_top_priority
);
// --------------------------------------
// Signals
// --------------------------------------
wire [NUM_REQUESTERS-1:0] top_priority;
reg [NUM_REQUESTERS-1:0] top_priority_reg;
reg [NUM_REQUESTERS-1:0] last_grant;
wire [2*NUM_REQUESTERS-1:0] result;
// --------------------------------------
// Scheme Selection
// --------------------------------------
generate
if (SCHEME == "round-robin" && NUM_REQUESTERS > 1) begin
assign top_priority = top_priority_reg;
end
else begin
// Fixed arbitration (or single-requester corner case)
assign top_priority = 1'b1;
end
endgenerate
// --------------------------------------
// Decision Logic
// --------------------------------------
altera_merlin_arb_adder
#(
.WIDTH (2 * NUM_REQUESTERS)
)
adder
(
.a ({ ~request, ~request }),
.b ({{NUM_REQUESTERS{1'b0}}, top_priority}),
.sum (result)
);
generate if (SCHEME == "no-arb") begin
// --------------------------------------
// No arbitration: just wire request directly to grant
// --------------------------------------
assign grant = request;
end else begin
// Do the math in double-vector domain
wire [2*NUM_REQUESTERS-1:0] grant_double_vector;
assign grant_double_vector = {request, request} & result;
// --------------------------------------
// Extract grant from the top and bottom halves
// of the double vector.
// --------------------------------------
assign grant =
grant_double_vector[NUM_REQUESTERS - 1 : 0] |
grant_double_vector[2 * NUM_REQUESTERS - 1 : NUM_REQUESTERS];
end
endgenerate
// --------------------------------------
// Left-rotate the last grant vector to create top_priority.
// --------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
top_priority_reg <= 1'b1;
end
else begin
if (PIPELINE) begin
if (increment_top_priority) begin
top_priority_reg <= (|request) ? {grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1]} : top_priority_reg;
end
end else begin
if (increment_top_priority) begin
if (|request)
top_priority_reg <= { grant[NUM_REQUESTERS-2:0],
grant[NUM_REQUESTERS-1] };
else
top_priority_reg <= { top_priority_reg[NUM_REQUESTERS-2:0], top_priority_reg[NUM_REQUESTERS-1] };
end
else if (save_top_priority) begin
top_priority_reg <= grant;
end
end
end
end
endmodule
// ----------------------------------------------
// Adder for the standard arbitrator
// ----------------------------------------------
module altera_merlin_arb_adder
#(
parameter WIDTH = 8
)
(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH-1:0] sum
);
wire [WIDTH:0] sum_lint;
// ----------------------------------------------
// Benchmarks indicate that for small widths, the full
// adder has higher fmax because synthesis can merge
// it with the mux, allowing partial decisions to be
// made early.
//
// The magic number is 4 requesters, which means an
// 8 bit adder.
// ----------------------------------------------
genvar i;
generate if (WIDTH <= 8) begin : full_adder
wire cout[WIDTH-1:0];
assign sum[0] = (a[0] ^ b[0]);
assign cout[0] = (a[0] & b[0]);
for (i = 1; i < WIDTH; i = i+1) begin : arb
assign sum[i] = (a[i] ^ b[i]) ^ cout[i-1];
assign cout[i] = (a[i] & b[i]) | (cout[i-1] & (a[i] ^ b[i]));
end
end else begin : carry_chain
assign sum_lint = a + b;
assign sum = sum_lint[WIDTH-1:0];
end
endgenerate
endmodule

566
Top/niosII/synthesis/submodules/altera_merlin_burst_uncompressor.sv
View File

@ -11,286 +11,286 @@
// agreement for further details.
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// ------------------------------------------
// Merlin Burst Uncompressor
//
// Compressed read bursts -> uncompressed
// ------------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_burst_uncompressor
#(
parameter ADDR_W = 16,
parameter BURSTWRAP_W = 3,
parameter BYTE_CNT_W = 4,
parameter PKT_SYMBOLS = 4,
parameter BURST_SIZE_W = 3
)
(
input clk,
input reset,
// sink ST signals
input sink_startofpacket,
input sink_endofpacket,
input sink_valid,
output sink_ready,
// sink ST "data"
input [ADDR_W - 1: 0] sink_addr,
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
input sink_is_compressed,
input [BURST_SIZE_W-1 : 0] sink_burstsize,
// source ST signals
output source_startofpacket,
output source_endofpacket,
output source_valid,
input source_ready,
// source ST "data"
output [ADDR_W - 1: 0] source_addr,
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
// Note: in the slave agent, the output should always be uncompressed. In
// other applications, it may be required to leave-compressed or not. How to
// control? Seems like a simple mux - pass-through if no uncompression is
// required.
output source_is_compressed,
output [BURST_SIZE_W-1 : 0] source_burstsize
);
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[63:0] bytes_in_transfer;
input [BURST_SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
endcase
endfunction
// num_symbols is PKT_SYMBOLS, appropriately sized.
wire [31:0] int_num_symbols = PKT_SYMBOLS;
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
// def: Burst Compression. In a merlin network, a compressed burst is one
// which is transmitted in a single beat. Example: read burst. In
// constrast, an uncompressed burst (example: write burst) is transmitted in
// one beat per writedata item.
//
// For compressed bursts which require response packets, burst
// uncompression is required. Concrete example: a read burst of size 8
// occupies one response-fifo position. When that fifo position reaches the
// front of the FIFO, the slave starts providing the required 8 readdatavalid
// pulses. The 8 return response beats must be provided in a single packet,
// with incrementing address and decrementing byte_cnt fields. Upon receipt
// of the final readdata item of the burst, the response FIFO item is
// retired.
// Burst uncompression logic provides:
// a) 2-state FSM (idle, busy)
// reset to idle state
// transition to busy state for 2nd and subsequent rdv pulses
// - a single-cycle burst (aka non-burst read) causes no transition to
// busy state.
// b) response startofpacket/endofpacket logic. The response FIFO item
// will have sop asserted, and may have eop asserted. (In the case of
// multiple read bursts transmit in the command fabric in a single packet,
// the eop assertion will come in a later FIFO item.) To support packet
// conservation, and emit a well-formed packet on the response fabric,
// i) response fabric startofpacket is asserted only for the first resp.
// beat;
// ii) response fabric endofpacket is asserted only for the last resp.
// beat.
// c) response address field. The response address field contains an
// incrementing sequence, such that each readdata item is associated with
// its slave-map location. N.b. a) computing the address correctly requires
// knowledge of burstwrap behavior b) there may be no clients of the address
// field, which makes this field a good target for optimization. See
// burst_uncompress_address_counter below.
// d) response byte_cnt field. The response byte_cnt field contains a
// decrementing sequence, such that each beat of the response contains the
// count of bytes to follow. In the case of sub-bursts in a single packet,
// the byte_cnt field may decrement down to num_symbols, then back up to
// some value, multiple times in the packet.
reg burst_uncompress_busy;
reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
wire first_packet_beat;
wire last_packet_beat;
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
// First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
// the output.
assign source_byte_cnt =
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
assign source_valid = sink_valid;
// Last packet beat is set throughout receipt of an uncompressed read burst
// from the response FIFO - this forces all the burst uncompression machinery
// idle.
assign last_packet_beat = ~sink_is_compressed |
(
burst_uncompress_busy ?
(sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
sink_valid & (sink_byte_cnt == num_symbols)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_busy <= '0;
burst_uncompress_byte_counter <= '0;
end
else begin
if (source_valid & source_ready & sink_valid) begin
// No matter what the current state, last_packet_beat leads to
// idle.
if (last_packet_beat) begin
burst_uncompress_busy <= '0;
burst_uncompress_byte_counter <= '0;
end
else begin
if (burst_uncompress_busy) begin
burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ?
(burst_uncompress_byte_counter_lint - num_symbols) :
(sink_byte_cnt - num_symbols);
end
else begin // not busy, at least one more beat to go
burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
// To do: should busy go true for numsymbols-size compressed
// bursts?
burst_uncompress_busy <= 1'b1;
end
end
end
end
end
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
wire [63:0] decoded_burstsize_wire;
wire [ADDR_W-1:0] decoded_burstsize;
localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
// The input burstwrap value can be used as a mask against address values,
// but with one caveat: the address width may be (probably is) wider than
// the burstwrap width. The spec says: extend the msb of the burstwrap
// value out over the entire address width (but only if the address width
// actually is wider than the burstwrap width; otherwise it's a 0-width or
// negative range and concatenation multiplier).
generate
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
// Sign-extend, just wires:
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
end
else begin
assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
end
endgenerate
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_address_base <= '0;
end
else if (first_packet_beat & source_ready) begin
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
end
end
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed
wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
(
(first_packet_beat ?
sink_addr :
burst_uncompress_address_offset) + decoded_burstsize
) &
addr_width_burstwrap[ADDR_W-1:0];
wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_address_offset <= '0;
end
else begin
if (source_ready & source_valid) begin
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
// if (first_packet_beat) begin
// burst_uncompress_address_offset <=
// (sink_addr + num_symbols) & addr_width_burstwrap;
// end
// else begin
// burst_uncompress_address_offset <=
// (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
// end
end
end
end
// On the first packet beat, send the input address out unchanged,
// while values are computed/registered for 2nd and subsequent beats.
assign source_addr = first_packet_beat ? sink_addr :
burst_uncompress_address_base | burst_uncompress_address_offset;
assign source_burstwrap = sink_burstwrap;
assign source_burstsize = sink_burstsize;
//-------------------------------------------------------------------
// A single (compressed) read burst will have sop/eop in the same beat.
// A sequence of read sub-bursts emitted by a burst adapter in response to a
// single read burst will have sop on the first sub-burst, eop on the last.
// Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
// packet conservation.
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
assign source_endofpacket = sink_endofpacket & last_packet_beat;
assign sink_ready = source_valid & source_ready & last_packet_beat;
// This is correct for the slave agent usage, but won't always be true in the
// width adapter. To do: add an "please uncompress" input, and use it to
// pass-through or modify, and set source_is_compressed accordingly.
assign source_is_compressed = 1'b0;
endmodule
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_agent/altera_merlin_burst_uncompressor.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// ------------------------------------------
// Merlin Burst Uncompressor
//
// Compressed read bursts -> uncompressed
// ------------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_burst_uncompressor
#(
parameter ADDR_W = 16,
parameter BURSTWRAP_W = 3,
parameter BYTE_CNT_W = 4,
parameter PKT_SYMBOLS = 4,
parameter BURST_SIZE_W = 3
)
(
input clk,
input reset,
// sink ST signals
input sink_startofpacket,
input sink_endofpacket,
input sink_valid,
output sink_ready,
// sink ST "data"
input [ADDR_W - 1: 0] sink_addr,
input [BURSTWRAP_W - 1 : 0] sink_burstwrap,
input [BYTE_CNT_W - 1 : 0] sink_byte_cnt,
input sink_is_compressed,
input [BURST_SIZE_W-1 : 0] sink_burstsize,
// source ST signals
output source_startofpacket,
output source_endofpacket,
output source_valid,
input source_ready,
// source ST "data"
output [ADDR_W - 1: 0] source_addr,
output [BURSTWRAP_W - 1 : 0] source_burstwrap,
output [BYTE_CNT_W - 1 : 0] source_byte_cnt,
// Note: in the slave agent, the output should always be uncompressed. In
// other applications, it may be required to leave-compressed or not. How to
// control? Seems like a simple mux - pass-through if no uncompression is
// required.
output source_is_compressed,
output [BURST_SIZE_W-1 : 0] source_burstsize
);
//----------------------------------------------------
// AXSIZE decoding
//
// Turns the axsize value into the actual number of bytes
// being transferred.
// ---------------------------------------------------
function reg[63:0] bytes_in_transfer;
input [BURST_SIZE_W-1:0] axsize;
case (axsize)
4'b0000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
4'b0001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000010;
4'b0010: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000100;
4'b0011: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000001000;
4'b0100: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000010000;
4'b0101: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000100000;
4'b0110: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000001000000;
4'b0111: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000010000000;
4'b1000: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000100000000;
4'b1001: bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000001000000000;
default:bytes_in_transfer = 64'b0000000000000000000000000000000000000000000000000000000000000001;
endcase
endfunction
// num_symbols is PKT_SYMBOLS, appropriately sized.
wire [31:0] int_num_symbols = PKT_SYMBOLS;
wire [BYTE_CNT_W-1:0] num_symbols = int_num_symbols[BYTE_CNT_W-1:0];
// def: Burst Compression. In a merlin network, a compressed burst is one
// which is transmitted in a single beat. Example: read burst. In
// constrast, an uncompressed burst (example: write burst) is transmitted in
// one beat per writedata item.
//
// For compressed bursts which require response packets, burst
// uncompression is required. Concrete example: a read burst of size 8
// occupies one response-fifo position. When that fifo position reaches the
// front of the FIFO, the slave starts providing the required 8 readdatavalid
// pulses. The 8 return response beats must be provided in a single packet,
// with incrementing address and decrementing byte_cnt fields. Upon receipt
// of the final readdata item of the burst, the response FIFO item is
// retired.
// Burst uncompression logic provides:
// a) 2-state FSM (idle, busy)
// reset to idle state
// transition to busy state for 2nd and subsequent rdv pulses
// - a single-cycle burst (aka non-burst read) causes no transition to
// busy state.
// b) response startofpacket/endofpacket logic. The response FIFO item
// will have sop asserted, and may have eop asserted. (In the case of
// multiple read bursts transmit in the command fabric in a single packet,
// the eop assertion will come in a later FIFO item.) To support packet
// conservation, and emit a well-formed packet on the response fabric,
// i) response fabric startofpacket is asserted only for the first resp.
// beat;
// ii) response fabric endofpacket is asserted only for the last resp.
// beat.
// c) response address field. The response address field contains an
// incrementing sequence, such that each readdata item is associated with
// its slave-map location. N.b. a) computing the address correctly requires
// knowledge of burstwrap behavior b) there may be no clients of the address
// field, which makes this field a good target for optimization. See
// burst_uncompress_address_counter below.
// d) response byte_cnt field. The response byte_cnt field contains a
// decrementing sequence, such that each beat of the response contains the
// count of bytes to follow. In the case of sub-bursts in a single packet,
// the byte_cnt field may decrement down to num_symbols, then back up to
// some value, multiple times in the packet.
reg burst_uncompress_busy;
reg [BYTE_CNT_W:0] burst_uncompress_byte_counter;
wire [BYTE_CNT_W-1:0] burst_uncompress_byte_counter_lint;
wire first_packet_beat;
wire last_packet_beat;
assign first_packet_beat = sink_valid & ~burst_uncompress_busy;
assign burst_uncompress_byte_counter_lint = burst_uncompress_byte_counter[BYTE_CNT_W-1:0];
// First cycle: burst_uncompress_byte_counter isn't ready yet, mux the input to
// the output.
assign source_byte_cnt =
first_packet_beat ? sink_byte_cnt : burst_uncompress_byte_counter_lint;
assign source_valid = sink_valid;
// Last packet beat is set throughout receipt of an uncompressed read burst
// from the response FIFO - this forces all the burst uncompression machinery
// idle.
assign last_packet_beat = ~sink_is_compressed |
(
burst_uncompress_busy ?
(sink_valid & (burst_uncompress_byte_counter_lint == num_symbols)) :
sink_valid & (sink_byte_cnt == num_symbols)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_busy <= '0;
burst_uncompress_byte_counter <= '0;
end
else begin
if (source_valid & source_ready & sink_valid) begin
// No matter what the current state, last_packet_beat leads to
// idle.
if (last_packet_beat) begin
burst_uncompress_busy <= '0;
burst_uncompress_byte_counter <= '0;
end
else begin
if (burst_uncompress_busy) begin
burst_uncompress_byte_counter <= (burst_uncompress_byte_counter > 0) ?
(burst_uncompress_byte_counter_lint - num_symbols) :
(sink_byte_cnt - num_symbols);
end
else begin // not busy, at least one more beat to go
burst_uncompress_byte_counter <= sink_byte_cnt - num_symbols;
// To do: should busy go true for numsymbols-size compressed
// bursts?
burst_uncompress_busy <= 1'b1;
end
end
end
end
end
reg [ADDR_W - 1 : 0 ] burst_uncompress_address_base;
reg [ADDR_W - 1 : 0] burst_uncompress_address_offset;
wire [63:0] decoded_burstsize_wire;
wire [ADDR_W-1:0] decoded_burstsize;
localparam ADD_BURSTWRAP_W = (ADDR_W > BURSTWRAP_W) ? ADDR_W : BURSTWRAP_W;
wire [ADD_BURSTWRAP_W-1:0] addr_width_burstwrap;
// The input burstwrap value can be used as a mask against address values,
// but with one caveat: the address width may be (probably is) wider than
// the burstwrap width. The spec says: extend the msb of the burstwrap
// value out over the entire address width (but only if the address width
// actually is wider than the burstwrap width; otherwise it's a 0-width or
// negative range and concatenation multiplier).
generate
if (ADDR_W > BURSTWRAP_W) begin : addr_sign_extend
// Sign-extend, just wires:
assign addr_width_burstwrap[ADDR_W - 1 : BURSTWRAP_W] =
{(ADDR_W - BURSTWRAP_W) {sink_burstwrap[BURSTWRAP_W - 1]}};
assign addr_width_burstwrap[BURSTWRAP_W-1:0] = sink_burstwrap [BURSTWRAP_W-1:0];
end
else begin
assign addr_width_burstwrap[BURSTWRAP_W-1 : 0] = sink_burstwrap;
end
endgenerate
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_address_base <= '0;
end
else if (first_packet_beat & source_ready) begin
burst_uncompress_address_base <= sink_addr & ~addr_width_burstwrap[ADDR_W-1:0];
end
end
assign decoded_burstsize_wire = bytes_in_transfer(sink_burstsize); //expand it to 64 bits
assign decoded_burstsize = decoded_burstsize_wire[ADDR_W-1:0]; //then take the width that is needed
wire [ADDR_W : 0] p1_burst_uncompress_address_offset =
(
(first_packet_beat ?
sink_addr :
burst_uncompress_address_offset) + decoded_burstsize
) &
addr_width_burstwrap[ADDR_W-1:0];
wire [ADDR_W-1:0] p1_burst_uncompress_address_offset_lint = p1_burst_uncompress_address_offset [ADDR_W-1:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
burst_uncompress_address_offset <= '0;
end
else begin
if (source_ready & source_valid) begin
burst_uncompress_address_offset <= p1_burst_uncompress_address_offset_lint;
// if (first_packet_beat) begin
// burst_uncompress_address_offset <=
// (sink_addr + num_symbols) & addr_width_burstwrap;
// end
// else begin
// burst_uncompress_address_offset <=
// (burst_uncompress_address_offset + num_symbols) & addr_width_burstwrap;
// end
end
end
end
// On the first packet beat, send the input address out unchanged,
// while values are computed/registered for 2nd and subsequent beats.
assign source_addr = first_packet_beat ? sink_addr :
burst_uncompress_address_base | burst_uncompress_address_offset;
assign source_burstwrap = sink_burstwrap;
assign source_burstsize = sink_burstsize;
//-------------------------------------------------------------------
// A single (compressed) read burst will have sop/eop in the same beat.
// A sequence of read sub-bursts emitted by a burst adapter in response to a
// single read burst will have sop on the first sub-burst, eop on the last.
// Assert eop only upon (sink_endofpacket & last_packet_beat) to preserve
// packet conservation.
assign source_startofpacket = sink_startofpacket & ~burst_uncompress_busy;
assign source_endofpacket = sink_endofpacket & last_packet_beat;
assign sink_ready = source_valid & source_ready & last_packet_beat;
// This is correct for the slave agent usage, but won't always be true in the
// width adapter. To do: add an "please uncompress" input, and use it to
// pass-through or modify, and set source_is_compressed accordingly.
assign source_is_compressed = 1'b0;
endmodule

580
Top/niosII/synthesis/submodules/altera_merlin_master_agent.sv
View File

@ -11,293 +11,293 @@
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// --------------------------------------
// Merlin Master Agent
//
// Converts Avalon-MM transactions into
// Merlin network packets.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_master_agent
#(
// -------------------
// Packet Format Parameters
// -------------------
parameter
PKT_QOS_H = 109,
PKT_QOS_L = 106,
PKT_DATA_SIDEBAND_H = 105,
PKT_DATA_SIDEBAND_L = 98,
PKT_ADDR_SIDEBAND_H = 97,
PKT_ADDR_SIDEBAND_L = 93,
PKT_CACHE_H = 92,
PKT_CACHE_L = 89,
PKT_THREAD_ID_H = 88,
PKT_THREAD_ID_L = 87,
PKT_BEGIN_BURST = 81,
PKT_PROTECTION_H = 80,
PKT_PROTECTION_L = 80,
PKT_BURSTWRAP_H = 79,
PKT_BURSTWRAP_L = 77,
PKT_BYTE_CNT_H = 76,
PKT_BYTE_CNT_L = 74,
PKT_ADDR_H = 73,
PKT_ADDR_L = 42,
PKT_BURST_SIZE_H = 86,
PKT_BURST_SIZE_L = 84,
PKT_BURST_TYPE_H = 94,
PKT_BURST_TYPE_L = 93,
PKT_TRANS_EXCLUSIVE = 83,
PKT_TRANS_LOCK = 82,
PKT_TRANS_COMPRESSED_READ = 41,
PKT_TRANS_POSTED = 40,
PKT_TRANS_WRITE = 39,
PKT_TRANS_READ = 38,
PKT_DATA_H = 37,
PKT_DATA_L = 6,
PKT_BYTEEN_H = 5,
PKT_BYTEEN_L = 2,
PKT_SRC_ID_H = 1,
PKT_SRC_ID_L = 1,
PKT_DEST_ID_H = 0,
PKT_DEST_ID_L = 0,
PKT_RESPONSE_STATUS_L = 110,
PKT_RESPONSE_STATUS_H = 111,
PKT_ORI_BURST_SIZE_L = 112,
PKT_ORI_BURST_SIZE_H = 114,
ST_DATA_W = 115,
ST_CHANNEL_W = 1,
// -------------------
// Agent Parameters
// -------------------
AV_BURSTCOUNT_W = 3,
ID = 1,
SUPPRESS_0_BYTEEN_RSP = 1,
BURSTWRAP_VALUE = 4,
CACHE_VALUE = 0,
SECURE_ACCESS_BIT = 1,
USE_READRESPONSE = 0,
USE_WRITERESPONSE = 0,
// -------------------
// Derived Parameters
// -------------------
PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
PKT_PROTECTION_W = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
) (
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Avalon-MM Anti-Master
// -------------------
input [PKT_ADDR_W-1 : 0] av_address,
input av_write,
input av_read,
input [PKT_DATA_W-1 : 0] av_writedata,
output reg [PKT_DATA_W-1 : 0] av_readdata,
output reg av_waitrequest,
output reg av_readdatavalid,
input [PKT_BYTEEN_W-1 : 0] av_byteenable,
input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
input av_debugaccess,
input av_lock,
output reg [1 : 0] av_response,
output reg av_writeresponsevalid,
// -------------------
// Command Source
// -------------------
output reg cp_valid,
output reg [ST_DATA_W-1 : 0] cp_data,
output wire cp_startofpacket,
output wire cp_endofpacket,
input cp_ready,
// -------------------
// Response Sink
// -------------------
input rp_valid,
input [ST_DATA_W-1 : 0] rp_data,
input [ST_CHANNEL_W-1 : 0] rp_channel,
input rp_startofpacket,
input rp_endofpacket,
output reg rp_ready
);
// ------------------------------------------------------------
// Utility Functions
// ------------------------------------------------------------
function integer clogb2;
input [31 : 0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
clogb2 = clogb2 - 1;
end
endfunction // clogb2
localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1);
localparam NUMSYMBOLS = PKT_BYTEEN_W;
localparam BURSTING = (MAX_BURST > NUMSYMBOLS);
localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
localparam BURST_SIZE = clogb2(NUMSYMBOLS);
typedef enum bit [1 : 0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
OTHER_WRAP = 2'b11
} MerlinBurstType;
// --------------------------------------
// Potential optimization: compare in words to save bits?
// --------------------------------------
wire is_burst;
assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
wire [31 : 0] id_int = ID;
wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
// --------------------------------------
// Address alignment
//
// The packet format requires that addresses be aligned to
// the transaction size.
// --------------------------------------
wire [PKT_ADDR_W-1 : 0] av_address_aligned;
generate
if (NUMSYMBOLS > 1) begin
assign av_address_aligned =
{av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
end
else begin
assign av_address_aligned = av_address;
end
endgenerate
// --------------------------------------
// Command & Response Construction
// --------------------------------------
always_comb begin
cp_data = '0;
cp_data[PKT_PROTECTION_L] = av_debugaccess;
cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // secure cache bit
cp_data[PKT_PROTECTION_L+2] = 1'b0; // instruction/data cache bit
cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = av_burstcount;
cp_data[PKT_ADDR_H : PKT_ADDR_L] = av_address_aligned;
cp_data[PKT_TRANS_EXCLUSIVE] = 1'b0;
cp_data[PKT_TRANS_LOCK] = av_lock;
cp_data[PKT_TRANS_COMPRESSED_READ] = av_read & is_burst;
cp_data[PKT_TRANS_READ] = av_read;
cp_data[PKT_TRANS_WRITE] = av_write;
cp_data[PKT_TRANS_POSTED] = av_write & !USE_WRITERESPONSE;
cp_data[PKT_DATA_H : PKT_DATA_L] = av_writedata;
cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] = av_byteenable;
cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] = burstsize_sig;
cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = bursttype_value;
cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L] = id_int[PKT_SRC_ID_W-1 : 0];
cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L] = '0;
cp_data[PKT_CACHE_H : PKT_CACHE_L] = CACHE_VALUE[3 : 0];
cp_data[PKT_QOS_H : PKT_QOS_L] = '0;
cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L] = '0;
cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L] = '0;
av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L];
if (USE_WRITERESPONSE || USE_READRESPONSE)
av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
else
av_response = '0;
end
// --------------------------------------
// Command Control
// --------------------------------------
reg hold_waitrequest;
always @ (posedge clk, posedge reset) begin
if (reset)
hold_waitrequest <= 1'b1;
else
hold_waitrequest <= 1'b0;
end
always_comb begin
cp_valid = 0;
if ((av_write || av_read) && ~hold_waitrequest)
cp_valid = 1;
end
generate if (BURSTING) begin
reg sop_enable;
always @(posedge clk, posedge reset) begin
if (reset) begin
sop_enable <= 1'b1;
end
else begin
if (cp_valid && cp_ready) begin
sop_enable <= 1'b0;
if (cp_endofpacket)
sop_enable <= 1'b1;
end
end
end
assign cp_startofpacket = sop_enable;
assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS);
end
else begin
assign cp_startofpacket = 1'b1;
assign cp_endofpacket = 1'b1;
end
endgenerate
// --------------------------------------
// Backpressure & Readdatavalid
// --------------------------------------
always_comb begin
rp_ready = 1;
av_readdatavalid = 0;
av_writeresponsevalid = 0;
av_waitrequest = hold_waitrequest | !cp_ready;
if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
av_writeresponsevalid = rp_valid;
else
av_readdatavalid = rp_valid;
if (SUPPRESS_0_BYTEEN_RSP) begin
if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
av_readdatavalid = 0;
end
end
endmodule
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_master_agent/altera_merlin_master_agent.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// --------------------------------------
// Merlin Master Agent
//
// Converts Avalon-MM transactions into
// Merlin network packets.
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_merlin_master_agent
#(
// -------------------
// Packet Format Parameters
// -------------------
parameter
PKT_QOS_H = 109,
PKT_QOS_L = 106,
PKT_DATA_SIDEBAND_H = 105,
PKT_DATA_SIDEBAND_L = 98,
PKT_ADDR_SIDEBAND_H = 97,
PKT_ADDR_SIDEBAND_L = 93,
PKT_CACHE_H = 92,
PKT_CACHE_L = 89,
PKT_THREAD_ID_H = 88,
PKT_THREAD_ID_L = 87,
PKT_BEGIN_BURST = 81,
PKT_PROTECTION_H = 80,
PKT_PROTECTION_L = 80,
PKT_BURSTWRAP_H = 79,
PKT_BURSTWRAP_L = 77,
PKT_BYTE_CNT_H = 76,
PKT_BYTE_CNT_L = 74,
PKT_ADDR_H = 73,
PKT_ADDR_L = 42,
PKT_BURST_SIZE_H = 86,
PKT_BURST_SIZE_L = 84,
PKT_BURST_TYPE_H = 94,
PKT_BURST_TYPE_L = 93,
PKT_TRANS_EXCLUSIVE = 83,
PKT_TRANS_LOCK = 82,
PKT_TRANS_COMPRESSED_READ = 41,
PKT_TRANS_POSTED = 40,
PKT_TRANS_WRITE = 39,
PKT_TRANS_READ = 38,
PKT_DATA_H = 37,
PKT_DATA_L = 6,
PKT_BYTEEN_H = 5,
PKT_BYTEEN_L = 2,
PKT_SRC_ID_H = 1,
PKT_SRC_ID_L = 1,
PKT_DEST_ID_H = 0,
PKT_DEST_ID_L = 0,
PKT_RESPONSE_STATUS_L = 110,
PKT_RESPONSE_STATUS_H = 111,
PKT_ORI_BURST_SIZE_L = 112,
PKT_ORI_BURST_SIZE_H = 114,
ST_DATA_W = 115,
ST_CHANNEL_W = 1,
// -------------------
// Agent Parameters
// -------------------
AV_BURSTCOUNT_W = 3,
ID = 1,
SUPPRESS_0_BYTEEN_RSP = 1,
BURSTWRAP_VALUE = 4,
CACHE_VALUE = 0,
SECURE_ACCESS_BIT = 1,
USE_READRESPONSE = 0,
USE_WRITERESPONSE = 0,
// -------------------
// Derived Parameters
// -------------------
PKT_BURSTWRAP_W = PKT_BURSTWRAP_H - PKT_BURSTWRAP_L + 1,
PKT_BYTE_CNT_W = PKT_BYTE_CNT_H - PKT_BYTE_CNT_L + 1,
PKT_PROTECTION_W = PKT_PROTECTION_H - PKT_PROTECTION_L + 1,
PKT_ADDR_W = PKT_ADDR_H - PKT_ADDR_L + 1,
PKT_DATA_W = PKT_DATA_H - PKT_DATA_L + 1,
PKT_BYTEEN_W = PKT_BYTEEN_H - PKT_BYTEEN_L + 1,
PKT_SRC_ID_W = PKT_SRC_ID_H - PKT_SRC_ID_L + 1,
PKT_DEST_ID_W = PKT_DEST_ID_H - PKT_DEST_ID_L + 1,
PKT_BURST_SIZE_W = PKT_BURST_SIZE_H - PKT_BURST_SIZE_L + 1
) (
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Avalon-MM Anti-Master
// -------------------
input [PKT_ADDR_W-1 : 0] av_address,
input av_write,
input av_read,
input [PKT_DATA_W-1 : 0] av_writedata,
output reg [PKT_DATA_W-1 : 0] av_readdata,
output reg av_waitrequest,
output reg av_readdatavalid,
input [PKT_BYTEEN_W-1 : 0] av_byteenable,
input [AV_BURSTCOUNT_W-1 : 0] av_burstcount,
input av_debugaccess,
input av_lock,
output reg [1 : 0] av_response,
output reg av_writeresponsevalid,
// -------------------
// Command Source
// -------------------
output reg cp_valid,
output reg [ST_DATA_W-1 : 0] cp_data,
output wire cp_startofpacket,
output wire cp_endofpacket,
input cp_ready,
// -------------------
// Response Sink
// -------------------
input rp_valid,
input [ST_DATA_W-1 : 0] rp_data,
input [ST_CHANNEL_W-1 : 0] rp_channel,
input rp_startofpacket,
input rp_endofpacket,
output reg rp_ready
);
// ------------------------------------------------------------
// Utility Functions
// ------------------------------------------------------------
function integer clogb2;
input [31 : 0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
clogb2 = clogb2 - 1;
end
endfunction // clogb2
localparam MAX_BURST = 1 << (AV_BURSTCOUNT_W - 1);
localparam NUMSYMBOLS = PKT_BYTEEN_W;
localparam BURSTING = (MAX_BURST > NUMSYMBOLS);
localparam BITS_TO_ZERO = clogb2(NUMSYMBOLS);
localparam BURST_SIZE = clogb2(NUMSYMBOLS);
typedef enum bit [1 : 0]
{
FIXED = 2'b00,
INCR = 2'b01,
WRAP = 2'b10,
OTHER_WRAP = 2'b11
} MerlinBurstType;
// --------------------------------------
// Potential optimization: compare in words to save bits?
// --------------------------------------
wire is_burst;
assign is_burst = (BURSTING) & (av_burstcount > NUMSYMBOLS);
wire [31 : 0] burstwrap_value_int = BURSTWRAP_VALUE;
wire [31 : 0] id_int = ID;
wire [PKT_BURST_SIZE_W-1 : 0] burstsize_sig = BURST_SIZE[PKT_BURST_SIZE_W-1 : 0];
wire [1 : 0] bursttype_value = burstwrap_value_int[PKT_BURSTWRAP_W-1] ? INCR : WRAP;
// --------------------------------------
// Address alignment
//
// The packet format requires that addresses be aligned to
// the transaction size.
// --------------------------------------
wire [PKT_ADDR_W-1 : 0] av_address_aligned;
generate
if (NUMSYMBOLS > 1) begin
assign av_address_aligned =
{av_address[PKT_ADDR_W-1 : BITS_TO_ZERO], {BITS_TO_ZERO {1'b0}}};
end
else begin
assign av_address_aligned = av_address;
end
endgenerate
// --------------------------------------
// Command & Response Construction
// --------------------------------------
always_comb begin
cp_data = '0;
cp_data[PKT_PROTECTION_L] = av_debugaccess;
cp_data[PKT_PROTECTION_L+1] = SECURE_ACCESS_BIT[0]; // secure cache bit
cp_data[PKT_PROTECTION_L+2] = 1'b0; // instruction/data cache bit
cp_data[PKT_BURSTWRAP_H : PKT_BURSTWRAP_L] = burstwrap_value_int[PKT_BURSTWRAP_W-1 : 0];
cp_data[PKT_BYTE_CNT_H : PKT_BYTE_CNT_L] = av_burstcount;
cp_data[PKT_ADDR_H : PKT_ADDR_L] = av_address_aligned;
cp_data[PKT_TRANS_EXCLUSIVE] = 1'b0;
cp_data[PKT_TRANS_LOCK] = av_lock;
cp_data[PKT_TRANS_COMPRESSED_READ] = av_read & is_burst;
cp_data[PKT_TRANS_READ] = av_read;
cp_data[PKT_TRANS_WRITE] = av_write;
cp_data[PKT_TRANS_POSTED] = av_write & !USE_WRITERESPONSE;
cp_data[PKT_DATA_H : PKT_DATA_L] = av_writedata;
cp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] = av_byteenable;
cp_data[PKT_BURST_SIZE_H : PKT_BURST_SIZE_L] = burstsize_sig;
cp_data[PKT_ORI_BURST_SIZE_H : PKT_ORI_BURST_SIZE_L] = burstsize_sig;
cp_data[PKT_BURST_TYPE_H : PKT_BURST_TYPE_L] = bursttype_value;
cp_data[PKT_SRC_ID_H : PKT_SRC_ID_L] = id_int[PKT_SRC_ID_W-1 : 0];
cp_data[PKT_THREAD_ID_H : PKT_THREAD_ID_L] = '0;
cp_data[PKT_CACHE_H : PKT_CACHE_L] = CACHE_VALUE[3 : 0];
cp_data[PKT_QOS_H : PKT_QOS_L] = '0;
cp_data[PKT_ADDR_SIDEBAND_H : PKT_ADDR_SIDEBAND_L] = '0;
cp_data[PKT_DATA_SIDEBAND_H : PKT_DATA_SIDEBAND_L] = '0;
av_readdata = rp_data[PKT_DATA_H : PKT_DATA_L];
if (USE_WRITERESPONSE || USE_READRESPONSE)
av_response = rp_data[PKT_RESPONSE_STATUS_H : PKT_RESPONSE_STATUS_L];
else
av_response = '0;
end
// --------------------------------------
// Command Control
// --------------------------------------
reg hold_waitrequest;
always @ (posedge clk, posedge reset) begin
if (reset)
hold_waitrequest <= 1'b1;
else
hold_waitrequest <= 1'b0;
end
always_comb begin
cp_valid = 0;
if ((av_write || av_read) && ~hold_waitrequest)
cp_valid = 1;
end
generate if (BURSTING) begin
reg sop_enable;
always @(posedge clk, posedge reset) begin
if (reset) begin
sop_enable <= 1'b1;
end
else begin
if (cp_valid && cp_ready) begin
sop_enable <= 1'b0;
if (cp_endofpacket)
sop_enable <= 1'b1;
end
end
end
assign cp_startofpacket = sop_enable;
assign cp_endofpacket = (av_read) | (av_burstcount == NUMSYMBOLS);
end
else begin
assign cp_startofpacket = 1'b1;
assign cp_endofpacket = 1'b1;
end
endgenerate
// --------------------------------------
// Backpressure & Readdatavalid
// --------------------------------------
always_comb begin
rp_ready = 1;
av_readdatavalid = 0;
av_writeresponsevalid = 0;
av_waitrequest = hold_waitrequest | !cp_ready;
if (USE_WRITERESPONSE && (rp_data[PKT_TRANS_WRITE] == 1))
av_writeresponsevalid = rp_valid;
else
av_readdatavalid = rp_valid;
if (SUPPRESS_0_BYTEEN_RSP) begin
if (rp_data[PKT_BYTEEN_H : PKT_BYTEEN_L] == 0)
av_readdatavalid = 0;
end
end
endmodule

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@ -11,472 +11,472 @@
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------
// Merlin Slave Translator
//
// Translates Universal Avalon MM Slave
// to any Avalon MM Slave
// -------------------------------------
//
//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
//The key feature here is that no same cycle turnaround data is processed through the fabric.
//import avalon_utilities_pkg::*;
`timescale 1 ns / 1 ns
module altera_merlin_slave_translator #(
parameter
//Widths
AV_ADDRESS_W = 32,
AV_DATA_W = 32,
AV_BURSTCOUNT_W = 4,
AV_BYTEENABLE_W = 4,
UAV_BYTEENABLE_W = 4,
//Read Latency
AV_READLATENCY = 1,
//Timing
AV_READ_WAIT_CYCLES = 0,
AV_WRITE_WAIT_CYCLES = 0,
AV_SETUP_WAIT_CYCLES = 0,
AV_DATA_HOLD_CYCLES = 0,
//Optional Port Declarations
USE_READDATAVALID = 1,
USE_WAITREQUEST = 1,
USE_READRESPONSE = 0,
USE_WRITERESPONSE = 0,
//Variable Addressing
AV_SYMBOLS_PER_WORD = 4,
AV_ADDRESS_SYMBOLS = 0,
AV_BURSTCOUNT_SYMBOLS = 0,
BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
UAV_ADDRESS_W = 38,
UAV_BURSTCOUNT_W = 10,
UAV_DATA_W = 32,
AV_CONSTANT_BURST_BEHAVIOR = 0,
UAV_CONSTANT_BURST_BEHAVIOR = 0,
CHIPSELECT_THROUGH_READLATENCY = 0,
// Tightly-Coupled Options
USE_UAV_CLKEN = 0,
AV_REQUIRE_UNALIGNED_ADDRESSES = 0
) (
// -------------------
// Clock & Reset
// -------------------
input wire clk,
input wire reset,
// -------------------
// Universal Avalon Slave
// -------------------
input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
input wire [UAV_DATA_W - 1 : 0] uav_writedata,
input wire uav_write,
input wire uav_read,
input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
input wire uav_lock,
input wire uav_debugaccess,
input wire uav_clken,
output logic uav_readdatavalid,
output logic uav_waitrequest,
output logic [UAV_DATA_W - 1 : 0] uav_readdata,
output logic [1:0] uav_response,
// input wire uav_writeresponserequest,
output logic uav_writeresponsevalid,
// -------------------
// Customizable Avalon Master
// -------------------
output logic [AV_ADDRESS_W - 1 : 0] av_address,
output logic [AV_DATA_W - 1 : 0] av_writedata,
output logic av_write,
output logic av_read,
output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
output logic av_begintransfer,
output wire av_chipselect,
output logic av_beginbursttransfer,
output logic av_lock,
output wire av_clken,
output wire av_debugaccess,
output wire av_outputenable,
input logic [AV_DATA_W - 1 : 0] av_readdata,
input logic av_readdatavalid,
input logic av_waitrequest,
input logic [1:0] av_response,
// output logic av_writeresponserequest,
input wire av_writeresponsevalid
);
function integer clog2_plusone;
input [31:0] Depth;
integer i;
begin
i = Depth;
for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
i = i >> 1;
end
endfunction
function integer max;
//returns the larger of two passed arguments
input [31:0] one;
input [31:0] two;
if(one > two)
max=one;
else
max=two;
endfunction // int
localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
AV_ADDRESS_W :
UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
AV_BURSTCOUNT_W :
UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
// Calculate the symbols per word as the power of 2 extended symbols per word
wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
// +--------------------------------
// |Backwards Compatibility Signals
// +--------------------------------
assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
assign av_debugaccess = uav_debugaccess;
// +-------------------
// |Passthru Signals
// +-------------------
reg [1 : 0] av_response_delayed;
always @(posedge clk, posedge reset) begin
if (reset) begin
av_response_delayed <= 2'b0;
end else begin
av_response_delayed <= av_response;
end
end
always_comb
begin
if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
uav_response = '0;
end else begin
if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
uav_response = av_response;
end else begin
uav_response = av_response_delayed;
end
end
end
// assign av_writeresponserequest = uav_writeresponserequest;
assign uav_writeresponsevalid = av_writeresponsevalid;
//-------------------------
//Writedata and Byteenable
//-------------------------
always@* begin
av_byteenable = '0;
av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
always@* begin
av_writedata = '0;
av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
end
// +-------------------
// |Calculated Signals
// +-------------------
logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
if(byteenable[i] == 1) begin
return i;
end
end
return '0;
endfunction
reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
reg [AV_ADDRESS_W - 1 : 0] address_reg;
always@(posedge clk, posedge reset) begin
if(reset) begin
burstcount_reg <= '0;
address_reg <= '0;
end else begin
burstcount_reg <= burstcount_reg;
address_reg <= address_reg;
if(av_beginbursttransfer) begin
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
end
end
end
logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
always@* begin
if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
temp_wire = decode_byteenable(uav_byteenable);
real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
end else begin
real_uav_address = uav_address;
end
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_address = address_reg;
end
always@* begin
av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_burstcount = burstcount_reg;
end
always@* begin
av_lock = uav_lock;
end
// -------------------
// Writebyteenable Assignment
// -------------------
always@* begin
av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
// -------------------
// Waitrequest Assignment
// -------------------
reg av_waitrequest_generated;
reg av_waitrequest_generated_read;
reg av_waitrequest_generated_write;
reg waitrequest_reset_override;
reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
always@(posedge reset, posedge clk) begin
if(reset) begin
wait_latency_counter <= '0;
waitrequest_reset_override <= 1'h1;
end else begin
waitrequest_reset_override <= 1'h0;
wait_latency_counter <= '0;
if( ~uav_waitrequest | waitrequest_reset_override )
wait_latency_counter <= '0;
else if( uav_read | uav_write )
wait_latency_counter <= wait_latency_counter + 1'h1;
end
end
always @* begin
av_read = uav_read;
av_write = uav_write;
av_waitrequest_generated = 1'h1;
av_waitrequest_generated_read = 1'h1;
av_waitrequest_generated_write = 1'h1;
if(LOG2_OF_LATENCY_SUM == 1)
av_waitrequest_generated = 0;
if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
if(uav_write)
av_waitrequest_generated = av_waitrequest_generated_write;
else
av_waitrequest_generated = av_waitrequest_generated_read;
end
if(USE_WAITREQUEST) begin
uav_waitrequest = av_waitrequest;
end else begin
uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
end
end
// --------------
// Readdata Assignment
// --------------
reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
always@(posedge clk, posedge reset) begin
if(reset)
av_readdata_pre <= 'b0;
else
av_readdata_pre <= av_readdata;
end
always@* begin
uav_readdata = {UAV_DATA_W{1'b0}};
if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
uav_readdata[AV_DATA_W-1:0] = av_readdata;
end else begin
uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
end
end
// -------------------
// Readdatavalid Assigment
// -------------------
reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
reg top_read_latency_shift_reg;
always@* begin
uav_readdatavalid=top_read_latency_shift_reg;
if(USE_READDATAVALID) begin
uav_readdatavalid = av_readdatavalid;
end
end
always@* begin
top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
top_read_latency_shift_reg=read_latency_shift_reg;
end
if (AV_READLATENCY > 1) begin
top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
end
end
always@(posedge reset, posedge clk) begin
if (reset) begin
read_latency_shift_reg <= '0;
end else if (av_clken) begin
read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
end
end
end
// ------------
// Chipselect and OutputEnable
// ------------
reg av_chipselect_pre;
wire cs_extension;
reg av_outputenable_pre;
assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
always@(posedge reset, posedge clk) begin
if(reset)
av_outputenable_pre <= 1'b0;
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
av_outputenable_pre <= 0;
else
av_outputenable_pre <= cs_extension | uav_read;
end
always@(posedge reset, posedge clk) begin
if(reset) begin
av_chipselect_pre <= 1'b0;
end else begin
av_chipselect_pre <= 1'b0;
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
if(uav_read) begin
av_chipselect_pre <= 1'b1;
end else if(cs_extension == 1) begin
av_chipselect_pre <= 1'b1;
end
end
end
end
// -------------------
// Begintransfer Assigment
// -------------------
reg end_begintransfer;
always@* begin
av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
end
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_begintransfer <= 1'b0;
end else begin
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
end_begintransfer <= 1'b1;
else if(uav_waitrequest)
end_begintransfer <= end_begintransfer;
else
end_begintransfer <= 1'b0;
end
end
// -------------------
// Beginbursttransfer Assigment
// -------------------
reg end_beginbursttransfer;
reg in_transfer;
always@* begin
av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
end
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_beginbursttransfer <= 1'b0;
in_transfer <= 1'b0;
end else begin
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
if(uav_write && uav_burstcount == symbols_per_word)
in_transfer <=1'b0;
else if(uav_write)
in_transfer <=1'b1;
end
end
endmodule
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator.sv#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------
// Merlin Slave Translator
//
// Translates Universal Avalon MM Slave
// to any Avalon MM Slave
// -------------------------------------
//
//Notable Note: 0 AV_READLATENCY is not allowed and will be converted to a 1 cycle readlatency in all cases but one
//If you declare a slave with fixed read timing requirements, the readlatency of such a slave will be allowed to be zero
//The key feature here is that no same cycle turnaround data is processed through the fabric.
//import avalon_utilities_pkg::*;
`timescale 1 ns / 1 ns
module altera_merlin_slave_translator #(
parameter
//Widths
AV_ADDRESS_W = 32,
AV_DATA_W = 32,
AV_BURSTCOUNT_W = 4,
AV_BYTEENABLE_W = 4,
UAV_BYTEENABLE_W = 4,
//Read Latency
AV_READLATENCY = 1,
//Timing
AV_READ_WAIT_CYCLES = 0,
AV_WRITE_WAIT_CYCLES = 0,
AV_SETUP_WAIT_CYCLES = 0,
AV_DATA_HOLD_CYCLES = 0,
//Optional Port Declarations
USE_READDATAVALID = 1,
USE_WAITREQUEST = 1,
USE_READRESPONSE = 0,
USE_WRITERESPONSE = 0,
//Variable Addressing
AV_SYMBOLS_PER_WORD = 4,
AV_ADDRESS_SYMBOLS = 0,
AV_BURSTCOUNT_SYMBOLS = 0,
BITS_PER_WORD = clog2_plusone(AV_SYMBOLS_PER_WORD - 1),
UAV_ADDRESS_W = 38,
UAV_BURSTCOUNT_W = 10,
UAV_DATA_W = 32,
AV_CONSTANT_BURST_BEHAVIOR = 0,
UAV_CONSTANT_BURST_BEHAVIOR = 0,
CHIPSELECT_THROUGH_READLATENCY = 0,
// Tightly-Coupled Options
USE_UAV_CLKEN = 0,
AV_REQUIRE_UNALIGNED_ADDRESSES = 0
) (
// -------------------
// Clock & Reset
// -------------------
input wire clk,
input wire reset,
// -------------------
// Universal Avalon Slave
// -------------------
input wire [UAV_ADDRESS_W - 1 : 0] uav_address,
input wire [UAV_DATA_W - 1 : 0] uav_writedata,
input wire uav_write,
input wire uav_read,
input wire [UAV_BURSTCOUNT_W - 1 : 0] uav_burstcount,
input wire [UAV_BYTEENABLE_W - 1 : 0] uav_byteenable,
input wire uav_lock,
input wire uav_debugaccess,
input wire uav_clken,
output logic uav_readdatavalid,
output logic uav_waitrequest,
output logic [UAV_DATA_W - 1 : 0] uav_readdata,
output logic [1:0] uav_response,
// input wire uav_writeresponserequest,
output logic uav_writeresponsevalid,
// -------------------
// Customizable Avalon Master
// -------------------
output logic [AV_ADDRESS_W - 1 : 0] av_address,
output logic [AV_DATA_W - 1 : 0] av_writedata,
output logic av_write,
output logic av_read,
output logic [AV_BURSTCOUNT_W - 1 : 0] av_burstcount,
output logic [AV_BYTEENABLE_W - 1 : 0] av_byteenable,
output logic [AV_BYTEENABLE_W - 1 : 0] av_writebyteenable,
output logic av_begintransfer,
output wire av_chipselect,
output logic av_beginbursttransfer,
output logic av_lock,
output wire av_clken,
output wire av_debugaccess,
output wire av_outputenable,
input logic [AV_DATA_W - 1 : 0] av_readdata,
input logic av_readdatavalid,
input logic av_waitrequest,
input logic [1:0] av_response,
// output logic av_writeresponserequest,
input wire av_writeresponsevalid
);
function integer clog2_plusone;
input [31:0] Depth;
integer i;
begin
i = Depth;
for(clog2_plusone = 0; i > 0; clog2_plusone = clog2_plusone + 1)
i = i >> 1;
end
endfunction
function integer max;
//returns the larger of two passed arguments
input [31:0] one;
input [31:0] two;
if(one > two)
max=one;
else
max=two;
endfunction // int
localparam AV_READ_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_READ_WAIT_CYCLES);
localparam AV_WRITE_WAIT_INDEXED = (AV_SETUP_WAIT_CYCLES + AV_WRITE_WAIT_CYCLES);
localparam AV_DATA_HOLD_INDEXED = (AV_WRITE_WAIT_INDEXED + AV_DATA_HOLD_CYCLES);
localparam LOG2_OF_LATENCY_SUM = max(clog2_plusone(AV_READ_WAIT_INDEXED + 1),clog2_plusone(AV_DATA_HOLD_INDEXED + 1));
localparam BURSTCOUNT_SHIFT_SELECTOR = AV_BURSTCOUNT_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_SHIFT_SELECTOR = AV_ADDRESS_SYMBOLS ? 0 : BITS_PER_WORD;
localparam ADDRESS_HIGH = ( UAV_ADDRESS_W > AV_ADDRESS_W + ADDRESS_SHIFT_SELECTOR ) ?
AV_ADDRESS_W :
UAV_ADDRESS_W - ADDRESS_SHIFT_SELECTOR;
localparam BURSTCOUNT_HIGH = ( UAV_BURSTCOUNT_W > AV_BURSTCOUNT_W + BURSTCOUNT_SHIFT_SELECTOR ) ?
AV_BURSTCOUNT_W :
UAV_BURSTCOUNT_W - BURSTCOUNT_SHIFT_SELECTOR;
localparam BYTEENABLE_ADDRESS_BITS = ( clog2_plusone(UAV_BYTEENABLE_W) - 1 ) >= 1 ? clog2_plusone(UAV_BYTEENABLE_W) - 1 : 1;
// Calculate the symbols per word as the power of 2 extended symbols per word
wire [31 : 0] symbols_per_word_int = 2**(clog2_plusone(AV_SYMBOLS_PER_WORD[UAV_BURSTCOUNT_W : 0] - 1));
wire [UAV_BURSTCOUNT_W-1 : 0] symbols_per_word = symbols_per_word_int[UAV_BURSTCOUNT_W-1 : 0];
// +--------------------------------
// |Backwards Compatibility Signals
// +--------------------------------
assign av_clken = (USE_UAV_CLKEN) ? uav_clken : 1'b1;
assign av_debugaccess = uav_debugaccess;
// +-------------------
// |Passthru Signals
// +-------------------
reg [1 : 0] av_response_delayed;
always @(posedge clk, posedge reset) begin
if (reset) begin
av_response_delayed <= 2'b0;
end else begin
av_response_delayed <= av_response;
end
end
always_comb
begin
if (!USE_READRESPONSE && !USE_WRITERESPONSE) begin
uav_response = '0;
end else begin
if (AV_READLATENCY != 0 || USE_READDATAVALID) begin
uav_response = av_response;
end else begin
uav_response = av_response_delayed;
end
end
end
// assign av_writeresponserequest = uav_writeresponserequest;
assign uav_writeresponsevalid = av_writeresponsevalid;
//-------------------------
//Writedata and Byteenable
//-------------------------
always@* begin
av_byteenable = '0;
av_byteenable = uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
always@* begin
av_writedata = '0;
av_writedata = uav_writedata[AV_DATA_W - 1 : 0];
end
// +-------------------
// |Calculated Signals
// +-------------------
logic [UAV_ADDRESS_W - 1 : 0 ] real_uav_address;
function [BYTEENABLE_ADDRESS_BITS - 1 : 0 ] decode_byteenable;
input [UAV_BYTEENABLE_W - 1 : 0 ] byteenable;
for(int i = 0 ; i < UAV_BYTEENABLE_W; i++ ) begin
if(byteenable[i] == 1) begin
return i;
end
end
return '0;
endfunction
reg [AV_BURSTCOUNT_W - 1 : 0] burstcount_reg;
reg [AV_ADDRESS_W - 1 : 0] address_reg;
always@(posedge clk, posedge reset) begin
if(reset) begin
burstcount_reg <= '0;
address_reg <= '0;
end else begin
burstcount_reg <= burstcount_reg;
address_reg <= address_reg;
if(av_beginbursttransfer) begin
burstcount_reg <= uav_burstcount [ BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
address_reg <= real_uav_address [ ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
end
end
end
logic [BYTEENABLE_ADDRESS_BITS-1:0] temp_wire;
always@* begin
if( AV_REQUIRE_UNALIGNED_ADDRESSES == 1) begin
temp_wire = decode_byteenable(uav_byteenable);
real_uav_address = { uav_address[UAV_ADDRESS_W - 1 : BYTEENABLE_ADDRESS_BITS ], temp_wire[BYTEENABLE_ADDRESS_BITS - 1 : 0 ] };
end else begin
real_uav_address = uav_address;
end
av_address = real_uav_address[ADDRESS_HIGH - 1 + ADDRESS_SHIFT_SELECTOR : ADDRESS_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_address = address_reg;
end
always@* begin
av_burstcount=uav_burstcount[BURSTCOUNT_HIGH - 1 + BURSTCOUNT_SHIFT_SELECTOR : BURSTCOUNT_SHIFT_SELECTOR ];
if( AV_CONSTANT_BURST_BEHAVIOR && !UAV_CONSTANT_BURST_BEHAVIOR && ~av_beginbursttransfer )
av_burstcount = burstcount_reg;
end
always@* begin
av_lock = uav_lock;
end
// -------------------
// Writebyteenable Assignment
// -------------------
always@* begin
av_writebyteenable = { (AV_BYTEENABLE_W){uav_write} } & uav_byteenable[AV_BYTEENABLE_W - 1 : 0];
end
// -------------------
// Waitrequest Assignment
// -------------------
reg av_waitrequest_generated;
reg av_waitrequest_generated_read;
reg av_waitrequest_generated_write;
reg waitrequest_reset_override;
reg [ ( LOG2_OF_LATENCY_SUM ? LOG2_OF_LATENCY_SUM - 1 : 0 ) : 0 ] wait_latency_counter;
always@(posedge reset, posedge clk) begin
if(reset) begin
wait_latency_counter <= '0;
waitrequest_reset_override <= 1'h1;
end else begin
waitrequest_reset_override <= 1'h0;
wait_latency_counter <= '0;
if( ~uav_waitrequest | waitrequest_reset_override )
wait_latency_counter <= '0;
else if( uav_read | uav_write )
wait_latency_counter <= wait_latency_counter + 1'h1;
end
end
always @* begin
av_read = uav_read;
av_write = uav_write;
av_waitrequest_generated = 1'h1;
av_waitrequest_generated_read = 1'h1;
av_waitrequest_generated_write = 1'h1;
if(LOG2_OF_LATENCY_SUM == 1)
av_waitrequest_generated = 0;
if(LOG2_OF_LATENCY_SUM > 1 && !USE_WAITREQUEST) begin
av_read = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_read;
av_write = wait_latency_counter >= AV_SETUP_WAIT_CYCLES && uav_write && wait_latency_counter <= AV_WRITE_WAIT_INDEXED;
av_waitrequest_generated_read = wait_latency_counter != AV_READ_WAIT_INDEXED;
av_waitrequest_generated_write = wait_latency_counter != AV_DATA_HOLD_INDEXED;
if(uav_write)
av_waitrequest_generated = av_waitrequest_generated_write;
else
av_waitrequest_generated = av_waitrequest_generated_read;
end
if(USE_WAITREQUEST) begin
uav_waitrequest = av_waitrequest;
end else begin
uav_waitrequest = av_waitrequest_generated | waitrequest_reset_override;
end
end
// --------------
// Readdata Assignment
// --------------
reg[(AV_DATA_W ? AV_DATA_W -1 : 0 ): 0] av_readdata_pre;
always@(posedge clk, posedge reset) begin
if(reset)
av_readdata_pre <= 'b0;
else
av_readdata_pre <= av_readdata;
end
always@* begin
uav_readdata = {UAV_DATA_W{1'b0}};
if( AV_READLATENCY != 0 || USE_READDATAVALID ) begin
uav_readdata[AV_DATA_W-1:0] = av_readdata;
end else begin
uav_readdata[AV_DATA_W-1:0] = av_readdata_pre;
end
end
// -------------------
// Readdatavalid Assigment
// -------------------
reg[(AV_READLATENCY>0 ? AV_READLATENCY-1:0) :0] read_latency_shift_reg;
reg top_read_latency_shift_reg;
always@* begin
uav_readdatavalid=top_read_latency_shift_reg;
if(USE_READDATAVALID) begin
uav_readdatavalid = av_readdatavalid;
end
end
always@* begin
top_read_latency_shift_reg = uav_read & ~uav_waitrequest & ~waitrequest_reset_override;
if(AV_READLATENCY == 1 || AV_READLATENCY == 0 ) begin
top_read_latency_shift_reg=read_latency_shift_reg;
end
if (AV_READLATENCY > 1) begin
top_read_latency_shift_reg = read_latency_shift_reg[(AV_READLATENCY ? AV_READLATENCY-1 : 0)];
end
end
always@(posedge reset, posedge clk) begin
if (reset) begin
read_latency_shift_reg <= '0;
end else if (av_clken) begin
read_latency_shift_reg[0] <= uav_read && ~uav_waitrequest & ~waitrequest_reset_override;
for (int i=0; i+1 < AV_READLATENCY ; i+=1 ) begin
read_latency_shift_reg[i+1] <= read_latency_shift_reg[i];
end
end
end
// ------------
// Chipselect and OutputEnable
// ------------
reg av_chipselect_pre;
wire cs_extension;
reg av_outputenable_pre;
assign av_chipselect = (uav_read | uav_write) ? 1'b1 : av_chipselect_pre;
assign cs_extension = ( (^ read_latency_shift_reg) & ~top_read_latency_shift_reg ) | ((| read_latency_shift_reg) & ~(^ read_latency_shift_reg));
assign av_outputenable = uav_read ? 1'b1 : av_outputenable_pre;
always@(posedge reset, posedge clk) begin
if(reset)
av_outputenable_pre <= 1'b0;
else if( AV_READLATENCY == 0 && AV_READ_WAIT_INDEXED != 0 )
av_outputenable_pre <= 0;
else
av_outputenable_pre <= cs_extension | uav_read;
end
always@(posedge reset, posedge clk) begin
if(reset) begin
av_chipselect_pre <= 1'b0;
end else begin
av_chipselect_pre <= 1'b0;
if(AV_READLATENCY != 0 && CHIPSELECT_THROUGH_READLATENCY == 1) begin
//The AV_READLATENCY term is only here to prevent chipselect from remaining asserted while read and write fall.
//There is no functional impact as 0 cycle transactions are treated as 1 cycle on the other side of the translator.
if(uav_read) begin
av_chipselect_pre <= 1'b1;
end else if(cs_extension == 1) begin
av_chipselect_pre <= 1'b1;
end
end
end
end
// -------------------
// Begintransfer Assigment
// -------------------
reg end_begintransfer;
always@* begin
av_begintransfer = ( uav_write | uav_read ) & ~end_begintransfer;
end
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_begintransfer <= 1'b0;
end else begin
if(av_begintransfer == 1 && uav_waitrequest && ~waitrequest_reset_override)
end_begintransfer <= 1'b1;
else if(uav_waitrequest)
end_begintransfer <= end_begintransfer;
else
end_begintransfer <= 1'b0;
end
end
// -------------------
// Beginbursttransfer Assigment
// -------------------
reg end_beginbursttransfer;
reg in_transfer;
always@* begin
av_beginbursttransfer = uav_read ? av_begintransfer : (av_begintransfer && ~end_beginbursttransfer && ~in_transfer);
end
always@ ( posedge clk or posedge reset ) begin
if(reset) begin
end_beginbursttransfer <= 1'b0;
in_transfer <= 1'b0;
end else begin
end_beginbursttransfer <= uav_write & ( uav_burstcount != symbols_per_word );
if(uav_write && uav_burstcount == symbols_per_word)
in_transfer <=1'b0;
else if(uav_write)
in_transfer <=1'b1;
end
end
endmodule

34
Top/niosII/synthesis/submodules/altera_reset_controller.sdc
View File

@ -11,20 +11,20 @@
# agreement for further details.
# +---------------------------------------------------
# | Cut the async clear paths
# +---------------------------------------------------
set aclr_counter 0
set clrn_counter 0
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
set aclr_counter [get_collection_size $aclr_collection]
set clrn_counter [get_collection_size $clrn_collection]
if {$aclr_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
}
if {$clrn_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
}
# +---------------------------------------------------
# | Cut the async clear paths
# +---------------------------------------------------
set aclr_counter 0
set clrn_counter 0
set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
set aclr_counter [get_collection_size $aclr_collection]
set clrn_counter [get_collection_size $clrn_collection]
if {$aclr_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr]
}
if {$clrn_counter > 0} {
set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn]
}

612
Top/niosII/synthesis/submodules/altera_reset_controller.v
View File

@ -11,309 +11,309 @@
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule

148
Top/niosII/synthesis/submodules/altera_reset_synchronizer.v
View File

@ -11,77 +11,77 @@
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
// $Id: //acds/rel/18.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule

4
Top/niosII/synthesis/submodules/niosII_cpu.v
View File

@ -10,7 +10,7 @@ module niosII_cpu (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [15:0] d_address, // data_master.address
output wire [17:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
@ -18,7 +18,7 @@ module niosII_cpu (
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [15:0] i_address, // instruction_master.address
output wire [17:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest

56
Top/niosII/synthesis/submodules/niosII_cpu_cpu.v
View File

@ -617,7 +617,7 @@ module niosII_cpu_cpu_nios2_oci_xbrk (
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 13: 0] F_pc;
input [ 15: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
@ -635,7 +635,7 @@ reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 15: 0] cpu_i_address;
wire [ 17: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
@ -821,7 +821,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
)
;
output [ 15: 0] cpu_d_address;
output [ 17: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
@ -837,7 +837,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 15: 0] d_address;
input [ 17: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
@ -845,7 +845,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
input reset_n;
wire [ 15: 0] cpu_d_address;
wire [ 17: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
@ -1201,7 +1201,7 @@ module niosII_cpu_cpu_nios2_oci_dtrace (
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 15: 0] cpu_d_address;
input [ 17: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
@ -2339,7 +2339,7 @@ defparam niosII_cpu_cpu_ociram_sp_ram.lpm_file = "niosII_cpu_cpu_ociram_default_
`endif
//synthesis translate_on
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001010 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001212 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
@ -2403,12 +2403,12 @@ module niosII_cpu_cpu_nios2_oci (
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 13: 0] F_pc;
input [ 15: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 15: 0] d_address;
input [ 17: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
@ -2427,7 +2427,7 @@ reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire [ 15: 0] cpu_d_address;
wire [ 17: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
@ -2864,7 +2864,7 @@ module niosII_cpu_cpu (
)
;
output [ 15: 0] d_address;
output [ 17: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
@ -2874,7 +2874,7 @@ module niosII_cpu_cpu (
output debug_mem_slave_waitrequest;
output debug_reset_request;
output dummy_ci_port;
output [ 15: 0] i_address;
output [ 17: 0] i_address;
output i_read;
input clk;
input [ 31: 0] d_readdata;
@ -2959,7 +2959,7 @@ wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 13: 0] D_jmp_direct_target_waddr;
wire [ 15: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
@ -3110,7 +3110,7 @@ wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 15: 0] E_mem_baddr;
wire [ 17: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
wire E_rf_ecc_recoverable_valid;
@ -3301,15 +3301,15 @@ wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 13: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
reg [ 15: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 13: 0] F_pc_no_crst_nxt;
wire [ 13: 0] F_pc_nxt;
wire [ 13: 0] F_pc_plus_one;
wire [ 15: 0] F_pc_no_crst_nxt;
wire [ 15: 0] F_pc_nxt;
wire [ 15: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 15: 0] F_pcb;
wire [ 15: 0] F_pcb_nxt;
wire [ 15: 0] F_pcb_plus_four;
wire [ 17: 0] F_pcb;
wire [ 17: 0] F_pcb_nxt;
wire [ 17: 0] F_pcb_plus_four;
wire F_valid;
wire [ 71: 0] F_vinst;
reg [ 1: 0] R_compare_op;
@ -3443,7 +3443,7 @@ reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 15: 0] W_mem_baddr;
wire [ 17: 0] W_mem_baddr;
reg W_rf_ecc_recoverable_valid;
reg W_rf_ecc_unrecoverable_valid;
wire W_rf_ecc_valid_any;
@ -3483,7 +3483,7 @@ wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 15: 0] d_address;
wire [ 17: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
@ -3501,7 +3501,7 @@ reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 15: 0] i_address;
wire [ 17: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
@ -3863,8 +3863,8 @@ reg wait_for_one_post_bret_inst;
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 :
(F_pc_sel_nxt == 2'b01)? 8712 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[15 : 2] :
(F_pc_sel_nxt == 2'b01)? 33288 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[17 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
@ -4166,7 +4166,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[15 : 0];
assign E_mem_baddr = E_arith_result[17 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
@ -4489,7 +4489,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result);
assign W_mem_baddr = W_alu_result[15 : 0];
assign W_mem_baddr = W_alu_result[17 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd0);

84
Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_a.mif
View File

@ -1,42 +1,42 @@
WIDTH=32;
DEPTH=32;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
00 : deadbeef;
01 : deadbeef;
02 : deadbeef;
03 : deadbeef;
04 : deadbeef;
05 : deadbeef;
06 : deadbeef;
07 : deadbeef;
08 : deadbeef;
09 : deadbeef;
0a : deadbeef;
0b : deadbeef;
0c : deadbeef;
0d : deadbeef;
0e : deadbeef;
0f : deadbeef;
10 : deadbeef;
11 : deadbeef;
12 : deadbeef;
13 : deadbeef;
14 : deadbeef;
15 : deadbeef;
16 : deadbeef;
17 : deadbeef;
18 : deadbeef;
19 : deadbeef;
1a : deadbeef;
1b : deadbeef;
1c : deadbeef;
1d : deadbeef;
1e : deadbeef;
1f : deadbeef;
END;
WIDTH=32;
DEPTH=32;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
00 : deadbeef;
01 : deadbeef;
02 : deadbeef;
03 : deadbeef;
04 : deadbeef;
05 : deadbeef;
06 : deadbeef;
07 : deadbeef;
08 : deadbeef;
09 : deadbeef;
0a : deadbeef;
0b : deadbeef;
0c : deadbeef;
0d : deadbeef;
0e : deadbeef;
0f : deadbeef;
10 : deadbeef;
11 : deadbeef;
12 : deadbeef;
13 : deadbeef;
14 : deadbeef;
15 : deadbeef;
16 : deadbeef;
17 : deadbeef;
18 : deadbeef;
19 : deadbeef;
1a : deadbeef;
1b : deadbeef;
1c : deadbeef;
1d : deadbeef;
1e : deadbeef;
1f : deadbeef;
END;

84
Top/niosII/synthesis/submodules/niosII_cpu_cpu_rf_ram_b.mif
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@ -1,42 +1,42 @@
WIDTH=32;
DEPTH=32;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
00 : deadbeef;
01 : deadbeef;
02 : deadbeef;
03 : deadbeef;
04 : deadbeef;
05 : deadbeef;
06 : deadbeef;
07 : deadbeef;
08 : deadbeef;
09 : deadbeef;
0a : deadbeef;
0b : deadbeef;
0c : deadbeef;
0d : deadbeef;
0e : deadbeef;
0f : deadbeef;
10 : deadbeef;
11 : deadbeef;
12 : deadbeef;
13 : deadbeef;
14 : deadbeef;
15 : deadbeef;
16 : deadbeef;
17 : deadbeef;
18 : deadbeef;
19 : deadbeef;
1a : deadbeef;
1b : deadbeef;
1c : deadbeef;
1d : deadbeef;
1e : deadbeef;
1f : deadbeef;
END;
WIDTH=32;
DEPTH=32;
ADDRESS_RADIX=HEX;
DATA_RADIX=HEX;
CONTENT BEGIN
00 : deadbeef;
01 : deadbeef;
02 : deadbeef;
03 : deadbeef;
04 : deadbeef;
05 : deadbeef;
06 : deadbeef;
07 : deadbeef;
08 : deadbeef;
09 : deadbeef;
0a : deadbeef;
0b : deadbeef;
0c : deadbeef;
0d : deadbeef;
0e : deadbeef;
0f : deadbeef;
10 : deadbeef;
11 : deadbeef;
12 : deadbeef;
13 : deadbeef;
14 : deadbeef;
15 : deadbeef;
16 : deadbeef;
17 : deadbeef;
18 : deadbeef;
19 : deadbeef;
1a : deadbeef;
1b : deadbeef;
1c : deadbeef;
1d : deadbeef;
1e : deadbeef;
1f : deadbeef;
END;

6
Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v
View File

@ -59,7 +59,7 @@ module niosII_cpu_cpu_test_bench (
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 15: 0] F_pcb;
input [ 17: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
@ -70,11 +70,11 @@ module niosII_cpu_cpu_test_bench (
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 15: 0] d_address;
input [ 17: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 15: 0] i_address;
input [ 17: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;

40962
Top/niosII/synthesis/submodules/niosII_mem.hex
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File diff suppressed because it is too large Load Diff

14
Top/niosII/synthesis/submodules/niosII_mem.v
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@ -48,8 +48,8 @@ module niosII_mem (
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 12: 0] address;
input [ 12: 0] address2;
input [ 14: 0] address;
input [ 14: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
@ -102,9 +102,9 @@ wire wren2;
the_altsyncram.indata_reg_b = "CLOCK0",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.numwords_b = 8192,
the_altsyncram.maximum_depth = 32768,
the_altsyncram.numwords_a = 32768,
the_altsyncram.numwords_b = 32768,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
@ -114,8 +114,8 @@ wire wren2;
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 13,
the_altsyncram.widthad_b = 13,
the_altsyncram.widthad_a = 15,
the_altsyncram.widthad_b = 15,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0";
//s1, which is an e_avalon_slave

1613
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v
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File diff suppressed because it is too large Load Diff

38
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v
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@ -1,12 +1,12 @@
// niosII_mm_interconnect_0_avalon_st_adapter.v
// niosII_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 18.1 625
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module niosII_mm_interconnect_0_avalon_st_adapter #(
module niosII_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
@ -23,7 +23,7 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
@ -33,14 +33,14 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
@ -185,8 +185,8 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
endgenerate
niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
@ -197,6 +197,6 @@ module niosII_mm_interconnect_0_avalon_st_adapter #(
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
);
endmodule

47
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv
View File

@ -28,9 +28,9 @@
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_demux
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// NUM_OUTPUTS: 5
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// NUM_OUTPUTS: 6
// VALID_WIDTH: 1
// ------------------------------------------
@ -46,8 +46,8 @@ module niosII_mm_interconnect_0_cmd_demux
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [92-1 : 0] sink_data, // ST_DATA_W=92
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input [94-1 : 0] sink_data, // ST_DATA_W=94
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -56,40 +56,47 @@ module niosII_mm_interconnect_0_cmd_demux
// Sources
// -------------------
output reg src0_valid,
output reg [92-1 : 0] src0_data, // ST_DATA_W=92
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [92-1 : 0] src1_data, // ST_DATA_W=92
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [92-1 : 0] src2_data, // ST_DATA_W=92
output reg [6-1 : 0] src2_channel, // ST_CHANNEL_W=6
output reg [94-1 : 0] src2_data, // ST_DATA_W=94
output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [92-1 : 0] src3_data, // ST_DATA_W=92
output reg [6-1 : 0] src3_channel, // ST_CHANNEL_W=6
output reg [94-1 : 0] src3_data, // ST_DATA_W=94
output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [92-1 : 0] src4_data, // ST_DATA_W=92
output reg [6-1 : 0] src4_channel, // ST_CHANNEL_W=6
output reg [94-1 : 0] src4_data, // ST_DATA_W=94
output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [94-1 : 0] src5_data, // ST_DATA_W=94
output reg [7-1 : 0] src5_channel, // ST_CHANNEL_W=7
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
// -------------------
// Clock & Reset
@ -101,7 +108,7 @@ module niosII_mm_interconnect_0_cmd_demux
);
localparam NUM_OUTPUTS = 5;
localparam NUM_OUTPUTS = 6;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
@ -143,6 +150,13 @@ module niosII_mm_interconnect_0_cmd_demux
src4_valid = sink_channel[4] && sink_valid;
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid;
end
// -------------------
@ -153,6 +167,7 @@ module niosII_mm_interconnect_0_cmd_demux
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});

18
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv
View File

@ -28,8 +28,8 @@
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_demux_001
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// NUM_OUTPUTS: 2
// VALID_WIDTH: 1
// ------------------------------------------
@ -46,8 +46,8 @@ module niosII_mm_interconnect_0_cmd_demux_001
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [92-1 : 0] sink_data, // ST_DATA_W=92
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input [94-1 : 0] sink_data, // ST_DATA_W=94
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -56,15 +56,15 @@ module niosII_mm_interconnect_0_cmd_demux_001
// Sources
// -------------------
output reg src0_valid,
output reg [92-1 : 0] src0_data, // ST_DATA_W=92
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [92-1 : 0] src1_data, // ST_DATA_W=92
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
@ -109,7 +109,7 @@ module niosII_mm_interconnect_0_cmd_demux_001
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule

22
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv
View File

@ -43,9 +43,9 @@
// ARBITRATION_SHARES: 1
// ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// ------------------------------------------
module niosII_mm_interconnect_0_cmd_mux
@ -54,8 +54,8 @@ module niosII_mm_interconnect_0_cmd_mux
// Sinks
// ----------------------
input sink0_valid,
input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
@ -65,8 +65,8 @@ module niosII_mm_interconnect_0_cmd_mux
// Source
// ----------------------
output src_valid,
output [92-1 : 0] src_data,
output [6-1 : 0] src_channel,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
@ -77,13 +77,13 @@ module niosII_mm_interconnect_0_cmd_mux
input clk,
input reset
);
localparam PAYLOAD_W = 92 + 6 + 2;
localparam PAYLOAD_W = 94 + 7 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 56;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
assign src_valid = sink0_valid;
assign src_data = sink0_data;

30
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv
View File

@ -43,9 +43,9 @@
// ARBITRATION_SHARES: 1 1
// ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// ------------------------------------------
module niosII_mm_interconnect_0_cmd_mux_002
@ -54,15 +54,15 @@ module niosII_mm_interconnect_0_cmd_mux_002
// Sinks
// ----------------------
input sink0_valid,
input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [92-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input [94-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
@ -72,8 +72,8 @@ module niosII_mm_interconnect_0_cmd_mux_002
// Source
// ----------------------
output src_valid,
output [92-1 : 0] src_data,
output [6-1 : 0] src_channel,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
@ -84,13 +84,13 @@ module niosII_mm_interconnect_0_cmd_mux_002
input clk,
input reset
);
localparam PAYLOAD_W = 92 + 6 + 2;
localparam PAYLOAD_W = 94 + 7 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 56;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
// ------------------------------------------
// Signals
@ -122,8 +122,8 @@ module niosII_mm_interconnect_0_cmd_mux_002
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[56];
lock[1] = sink1_data[56];
lock[0] = sink0_data[58];
lock[1] = sink1_data[58];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin

95
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv
View File

@ -44,26 +44,26 @@
module niosII_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 4,
parameter DEFAULT_CHANNEL = 5,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 3
)
(output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[78 - 76 : 0];
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_default_decode
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router
// Command Sink (Input)
// -------------------
input sink_valid,
input [92-1 : 0] sink_data,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router
// Command Source (Output)
// -------------------
output src_valid,
output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 55;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@ -134,17 +134,18 @@ module niosII_mm_interconnect_0_router
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h8000 - 64'h0);
localparam PAD1 = log2ceil(64'h9000 - 64'h8800);
localparam PAD2 = log2ceil(64'h9020 - 64'h9000);
localparam PAD3 = log2ceil(64'h9028 - 64'h9020);
localparam PAD4 = log2ceil(64'h902c - 64'h9028);
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
localparam PAD2 = log2ceil(64'h21040 - 64'h21000);
localparam PAD3 = log2ceil(64'h21060 - 64'h21040);
localparam PAD4 = log2ceil(64'h21068 - 64'h21060);
localparam PAD5 = log2ceil(64'h21070 - 64'h21068);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h902c;
localparam ADDR_RANGE = 64'h21070;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
@ -168,7 +169,7 @@ module niosII_mm_interconnect_0_router
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [6-1 : 0] default_src_channel;
wire [7-1 : 0] default_src_channel;
@ -197,36 +198,42 @@ module niosII_mm_interconnect_0_router
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x8000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 16'h0 ) begin
src_channel = 6'b10000;
// ( 0x0 .. 0x20000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
src_channel = 7'b100000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x8800 .. 0x9000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 16'h8800 ) begin
src_channel = 6'b00100;
// ( 0x20800 .. 0x21000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
src_channel = 7'b000100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x9000 .. 0x9020 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 16'h9000 ) begin
src_channel = 6'b01000;
// ( 0x21000 .. 0x21040 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 && write_transaction ) begin
src_channel = 7'b001000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x9020 .. 0x9028 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 16'h9020 ) begin
src_channel = 6'b00001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
// ( 0x21040 .. 0x21060 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21040 ) begin
src_channel = 7'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x9028 .. 0x902c )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 16'h9028 && write_transaction ) begin
src_channel = 6'b00010;
// ( 0x21060 .. 0x21068 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21060 ) begin
src_channel = 7'b000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
// ( 0x21068 .. 0x21070 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21068 ) begin
src_channel = 7'b000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
end

60
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv
View File

@ -49,21 +49,21 @@ module niosII_mm_interconnect_0_router_001_default_decode
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 2
)
(output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[78 - 76 : 0];
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_001_default_decode
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_001
// Command Sink (Input)
// -------------------
input sink_valid,
input [92-1 : 0] sink_data,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router_001
// Command Source (Output)
// -------------------
output src_valid,
output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_001
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 55;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@ -134,14 +134,14 @@ module niosII_mm_interconnect_0_router_001
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h8000 - 64'h0);
localparam PAD1 = log2ceil(64'h9000 - 64'h8800);
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h9000;
localparam ADDR_RANGE = 64'h21000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
@ -165,7 +165,7 @@ module niosII_mm_interconnect_0_router_001
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [6-1 : 0] default_src_channel;
wire [7-1 : 0] default_src_channel;
@ -189,15 +189,15 @@ module niosII_mm_interconnect_0_router_001
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x8000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 16'h0 ) begin
src_channel = 6'b10;
// ( 0x0 .. 0x20000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
src_channel = 7'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x8800 .. 0x9000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 16'h8800 ) begin
src_channel = 6'b01;
// ( 0x20800 .. 0x21000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
src_channel = 7'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end

44
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv
View File

@ -49,21 +49,21 @@ module niosII_mm_interconnect_0_router_002_default_decode
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[78 - 76 : 0];
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_002_default_decode
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_002
// Command Sink (Input)
// -------------------
input sink_valid,
input [92-1 : 0] sink_data,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router_002
// Command Source (Output)
// -------------------
output src_valid,
output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_002
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 55;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@ -158,7 +158,7 @@ module niosII_mm_interconnect_0_router_002
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [6-1 : 0] default_src_channel;
wire [7-1 : 0] default_src_channel;
@ -185,7 +185,7 @@ module niosII_mm_interconnect_0_router_002
if (destid == 0 ) begin
src_channel = 6'b1;
src_channel = 7'b1;
end

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