fpga-lab-2/Testbench/sigdel
Ivan I. Ovchinnikov dad79c26fb wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
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inc_lut_tb.sv wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
lut_mod_tb.sv wip lab4, tested module 2023-01-27 17:06:29 +03:00
sigdel.qpf wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
sigdel.qsf wip lab4, tested module 2023-01-27 17:06:29 +03:00
sigdel.qws wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
sigdel.sv wip lab4, tested module 2023-01-27 17:06:29 +03:00
sigdel_tb.sv wip lab4, tested module 2023-01-27 17:06:29 +03:00
sine256.mif wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00