2023-01-27 18:04:01 +03:00
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# TCL File Generated by Component Editor 18.1
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2023-02-07 16:10:37 +03:00
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# Tue Feb 07 16:48:35 MSK 2023
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2023-01-27 18:04:01 +03:00
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# DO NOT MODIFY
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#
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# sigdel "Sigma-Delta Modulator" v1.0
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2023-02-07 16:10:37 +03:00
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# 2023.02.07.16:48:35
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2023-01-27 18:04:01 +03:00
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#
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#
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#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module sigdel
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME sigdel
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "User Logic"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME "Sigma-Delta Modulator"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL sigdel
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file phacc.sv SYSTEM_VERILOG PATH ../HDL/phacc.sv
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add_fileset_file sdmod.sv SYSTEM_VERILOG PATH ../HDL/sdmod.sv
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add_fileset_file sigdel.sv SYSTEM_VERILOG PATH ../HDL/sigdel.sv TOP_LEVEL_FILE
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add_fileset_file sinelut.v VERILOG PATH ../HDL/IP/sinelut.v
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add_fileset_file sine256.mif MIF PATH ../HDL/IP/sine256.mif
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#
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# parameters
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#
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add_parameter PHACC_WIDTH INTEGER 14
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set_parameter_property PHACC_WIDTH DEFAULT_VALUE 14
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set_parameter_property PHACC_WIDTH DISPLAY_NAME PHACC_WIDTH
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set_parameter_property PHACC_WIDTH TYPE INTEGER
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set_parameter_property PHACC_WIDTH UNITS None
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set_parameter_property PHACC_WIDTH ALLOWED_RANGES -2147483648:2147483647
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set_parameter_property PHACC_WIDTH HDL_PARAMETER true
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#
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# display items
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#
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#
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# connection point clock
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#
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink clr_n reset_n Input 1
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#
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# connection point conduit_end
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#
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add_interface conduit_end conduit end
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set_interface_property conduit_end associatedClock ""
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set_interface_property conduit_end associatedReset ""
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set_interface_property conduit_end ENABLED true
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set_interface_property conduit_end EXPORT_OF ""
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set_interface_property conduit_end PORT_NAME_MAP ""
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set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
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set_interface_property conduit_end SVD_ADDRESS_GROUP ""
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add_interface_port conduit_end fout writeresponsevalid_n Output 1
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#
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# connection point avalon_slave
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#
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add_interface avalon_slave avalon end
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set_interface_property avalon_slave addressUnits WORDS
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set_interface_property avalon_slave associatedClock clock
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set_interface_property avalon_slave associatedReset reset_sink
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set_interface_property avalon_slave bitsPerSymbol 8
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set_interface_property avalon_slave burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave burstcountUnits WORDS
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set_interface_property avalon_slave explicitAddressSpan 0
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set_interface_property avalon_slave holdTime 0
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set_interface_property avalon_slave linewrapBursts false
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set_interface_property avalon_slave maximumPendingReadTransactions 0
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set_interface_property avalon_slave maximumPendingWriteTransactions 0
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set_interface_property avalon_slave readLatency 0
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set_interface_property avalon_slave readWaitTime 1
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set_interface_property avalon_slave setupTime 0
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set_interface_property avalon_slave timingUnits Cycles
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set_interface_property avalon_slave writeWaitTime 0
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set_interface_property avalon_slave ENABLED true
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set_interface_property avalon_slave EXPORT_OF ""
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set_interface_property avalon_slave PORT_NAME_MAP ""
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set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave wr_n write_n Input 1
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add_interface_port avalon_slave wr_data writedata Input 32
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set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
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