ivan-igorevich
/
fpga-lab-2
0
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sem ram widening correct, generate testbench in PD was needed

This commit is contained in:
Ivan I. Ovchinnikov 2022-12-19 22:48:11 +03:00
parent def7e9c9c4
commit 1589af18e7
34 changed files with 13292 additions and 13110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
HDL/IP/periodram.qip
View File

@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "14.0" set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"] set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"] set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"]

55
HDL/IP/periodram.v
View File

@ -14,24 +14,23 @@
// ************************************************************ // ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// //
// 14.0.2 Build 209 09/17/2014 SJ Full Version // 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************ // ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved. //Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions //Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic //and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing //functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any //(including device programming or simulation files), and any
//associated documentation or information are expressly subject //associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License //to the terms and conditions of the Intel Program License
//Subscription Agreement, the Altera Quartus II License Agreement, //Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other //the Intel FPGA IP License Agreement, or other applicable license
//applicable license agreement, including, without limitation, //agreement, including, without limitation, that your use is for
//that your use is for the sole purpose of programming logic //the sole purpose of programming logic devices manufactured by
//devices manufactured by Altera and sold by Altera or its //Intel and sold by Intel or its authorized distributors. Please
//authorized distributors. Please refer to the applicable //refer to the applicable agreement for further details.
//agreement for further details.
// synopsys translate_off // synopsys translate_off
@ -47,10 +46,10 @@ module periodram (
input clock; input clock;
input [31:0] data; input [31:0] data;
input [3:0] rdaddress; input [1:0] rdaddress;
input [1:0] wraddress; input [1:0] wraddress;
input wren; input wren;
output [7:0] q; output [31:0] q;
`ifndef ALTERA_RESERVED_QIS `ifndef ALTERA_RESERVED_QIS
// synopsys translate_off // synopsys translate_off
`endif `endif
@ -60,8 +59,8 @@ module periodram (
// synopsys translate_on // synopsys translate_on
`endif `endif
wire [7:0] sub_wire0; wire [31:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0]; wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component ( altsyncram altsyncram_component (
.address_a (wraddress), .address_a (wraddress),
@ -81,7 +80,7 @@ module periodram (
.clocken1 (1'b1), .clocken1 (1'b1),
.clocken2 (1'b1), .clocken2 (1'b1),
.clocken3 (1'b1), .clocken3 (1'b1),
.data_b ({8{1'b1}}), .data_b ({32{1'b1}}),
.eccstatus (), .eccstatus (),
.q_a (), .q_a (),
.rden_a (1'b1), .rden_a (1'b1),
@ -96,16 +95,16 @@ module periodram (
altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4, altsyncram_component.numwords_a = 4,
altsyncram_component.numwords_b = 16, altsyncram_component.numwords_b = 4,
altsyncram_component.operation_mode = "DUAL_PORT", altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 2, altsyncram_component.widthad_a = 2,
altsyncram_component.widthad_b = 4, altsyncram_component.widthad_b = 2,
altsyncram_component.width_a = 32, altsyncram_component.width_a = 32,
altsyncram_component.width_b = 8, altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1; altsyncram_component.width_byteena_a = 1;
@ -165,9 +164,9 @@ endmodule
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1" // Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
@ -182,29 +181,29 @@ endmodule
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]" // Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL "rdaddress[1..0]"
// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]" // Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0 // Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0 // Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0 // Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE

2
HDL/dec.sv
View File

@ -1,5 +1,5 @@
module dec module dec
#(m = 8) #(m = 32)
( (
//clock and reset //clock and reset
input logic clk, clrn, input logic clk, clrn,

4
Testbench/dec/dec.qsf
View File

@ -59,9 +59,9 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name QIP_FILE ../../HDL/IP/periodram.qip set_global_assignment -name QIP_FILE ../../HDL/IP/periodram.qip
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/dec.sv set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/dec.sv
set_global_assignment -name SYSTEMVERILOG_FILE dec_tb.sv set_global_assignment -name SYSTEMVERILOG_FILE dec_tb.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dec_tb -section_id eda_simulation set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dec_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
Testbench/dec/dec.qws
View File

Binary file not shown.

151
Top/#niosII_tb.csv# Normal file
View File

@ -0,0 +1,151 @@
# system info niosII_tb on 2022.10.24.18:26:01
system_info:
name,value
DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1666621532
#
#
# Files generated for niosII_tb on 2022.10.24.18:26:01
files:
filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_002,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_004,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_008,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_demux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
niosII_tb.niosII_inst,niosII
niosII_tb.niosII_inst.cpu,niosII_cpu
niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
niosII_tb.niosII_inst.mem,niosII_mem
niosII_tb.niosII_inst.sem,dec
niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_translator,altera_merlin_slave_translator
niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent,altera_merlin_slave_agent
niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent_rsp_fifo,altera_avalon_sc_fifo
niosII_tb.niosII_inst.mm_interconnect_0.router,niosII_mm_interconnect_0_router
niosII_tb.niosII_inst.mm_interconnect_0.router_001,niosII_mm_interconnect_0_router_001
niosII_tb.niosII_inst.mm_interconnect_0.router_002,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_003,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_005,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_006,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_007,niosII_mm_interconnect_0_router_002
niosII_tb.niosII_inst.mm_interconnect_0.router_004,niosII_mm_interconnect_0_router_004
niosII_tb.niosII_inst.mm_interconnect_0.router_008,niosII_mm_interconnect_0_router_008
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux,niosII_mm_interconnect_0_cmd_demux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux_001,niosII_mm_interconnect_0_cmd_demux_001
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_002,niosII_mm_interconnect_0_cmd_demux_001
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_001,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_003,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_004,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_005,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_006,niosII_mm_interconnect_0_cmd_mux
niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_002,niosII_mm_interconnect_0_cmd_mux_002
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_001,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_003,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_004,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_005,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_006,niosII_mm_interconnect_0_rsp_demux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux,niosII_mm_interconnect_0_rsp_mux
niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux_001,niosII_mm_interconnect_0_rsp_mux_001
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006,niosII_mm_interconnect_0_avalon_st_adapter
niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
niosII_tb.niosII_inst.rst_controller,altera_reset_controller
niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source

13
Top/Semafor_hw.tcl
View File

@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1 # TCL File Generated by Component Editor 18.1
# Mon Oct 24 17:47:36 MSK 2022 # Mon Dec 19 20:23:41 MSK 2022
# DO NOT MODIFY # DO NOT MODIFY
# #
# sem "Semafor" v1.0 # sem "Semafor" v1.1
# 2022.10.24.17:47:36 # 2022.12.19.20:23:40
# #
# #
@ -20,7 +20,7 @@ package require -exact qsys 16.1
# #
set_module_property DESCRIPTION "" set_module_property DESCRIPTION ""
set_module_property NAME sem set_module_property NAME sem
set_module_property VERSION 1.0 set_module_property VERSION 1.1
set_module_property INTERNAL false set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "User Logic" set_module_property GROUP "User Logic"
@ -54,12 +54,13 @@ add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
# #
# parameters # parameters
# #
add_parameter m INTEGER 8 add_parameter m INTEGER 32 ""
set_parameter_property m DEFAULT_VALUE 8 set_parameter_property m DEFAULT_VALUE 32
set_parameter_property m DISPLAY_NAME m set_parameter_property m DISPLAY_NAME m
set_parameter_property m TYPE INTEGER set_parameter_property m TYPE INTEGER
set_parameter_property m UNITS None set_parameter_property m UNITS None
set_parameter_property m ALLOWED_RANGES -2147483648:2147483647 set_parameter_property m ALLOWED_RANGES -2147483648:2147483647
set_parameter_property m DESCRIPTION ""
set_parameter_property m HDL_PARAMETER true set_parameter_property m HDL_PARAMETER true

13
Top/Semafor_hw.tcl~
View File

@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1 # TCL File Generated by Component Editor 18.1
# Mon Oct 24 14:36:52 MSK 2022 # Mon Dec 19 20:18:22 MSK 2022
# DO NOT MODIFY # DO NOT MODIFY
# #
# sem "Semafor" v1.0 # sem "Semafor" v1.1
# 2022.10.24.14:36:52 # 2022.12.19.20:18:22
# #
# #
@ -20,7 +20,7 @@ package require -exact qsys 16.1
# #
set_module_property DESCRIPTION "" set_module_property DESCRIPTION ""
set_module_property NAME sem set_module_property NAME sem
set_module_property VERSION 1.0 set_module_property VERSION 1.1
set_module_property INTERNAL false set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "User Logic" set_module_property GROUP "User Logic"
@ -54,12 +54,13 @@ add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
# #
# parameters # parameters
# #
add_parameter m INTEGER 8 add_parameter m INTEGER 32 ""
set_parameter_property m DEFAULT_VALUE 8 set_parameter_property m DEFAULT_VALUE 32
set_parameter_property m DISPLAY_NAME m set_parameter_property m DISPLAY_NAME m
set_parameter_property m TYPE INTEGER set_parameter_property m TYPE INTEGER
set_parameter_property m UNITS None set_parameter_property m UNITS None
set_parameter_property m ALLOWED_RANGES -2147483648:2147483647 set_parameter_property m ALLOWED_RANGES -2147483648:2147483647
set_parameter_property m DESCRIPTION ""
set_parameter_property m HDL_PARAMETER true set_parameter_property m HDL_PARAMETER true

20
Top/niosII.qsys
View File

@ -81,6 +81,22 @@
type = "String"; type = "String";
} }
} }
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element sem element sem
{ {
datum _sortIndex datum _sortIndex
@ -380,8 +396,8 @@
<parameter name="useShallowMemBlocks" value="false" /> <parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" /> <parameter name="writable" value="true" />
</module> </module>
<module name="sem" kind="sem" version="1.0" enabled="1"> <module name="sem" kind="sem" version="1.1" enabled="1">
<parameter name="m" value="8" /> <parameter name="m" value="32" />
</module> </module>
<module <module
name="sys_clk_timer" name="sys_clk_timer"

10
Top/niosII.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS"> <EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.10.31.15:36:09 --> <!-- 2022.12.19.20:24:19 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1667216169</value> <value>1671467059</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -5652,12 +5652,12 @@ parameters are a RESULT of the module parameters. -->
</port> </port>
</interface> </interface>
</module> </module>
<module name="sem" kind="sem" version="1.0" path="sem"> <module name="sem" kind="sem" version="1.1" path="sem">
<!-- Describes a single module. Module parameters are <!-- Describes a single module. Module parameters are
the requested settings for a module instance. --> the requested settings for a module instance. -->
<parameter name="m"> <parameter name="m">
<type>int</type> <type>int</type>
<value>8</value> <value>32</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -8350,7 +8350,7 @@ parameters are a RESULT of the module parameters. -->
<type>com.altera.entityinterfaces.IElementClass</type> <type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype> <subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Semafor</displayName> <displayName>Semafor</displayName>
<version>1.0</version> <version>1.1</version>
</plugin> </plugin>
<plugin> <plugin>
<instanceCount>1</instanceCount> <instanceCount>1</instanceCount>

2
Top/niosII/niosII.bsf
View File

@ -75,7 +75,7 @@ refer to the applicable agreement for further details.
(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0))) (text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0))) (text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0))) (text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
(text " niosII " (rect 262 216 572 442)(font "Arial" )) (text " system " (rect 253 216 554 442)(font "Arial" ))
(line (pt 112 32)(pt 176 32)(line_width 1)) (line (pt 112 32)(pt 176 32)(line_width 1))
(line (pt 176 32)(pt 176 216)(line_width 1)) (line (pt 176 32)(pt 176 216)(line_width 1))
(line (pt 112 216)(pt 176 216)(line_width 1)) (line (pt 112 216)(pt 176 216)(line_width 1))

12
Top/niosII/niosII.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2022.10.24.17:48:01</td> <td class="l">2022.12.17.15:20:08</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</a> altera_avalon_onchip_memory2 18.1 </a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160; <br/>&#160;&#160;
<a href="#module_sem"><b>sem</b> <a href="#module_sem"><b>sem</b>
</a> sem 1.0 </a> sem 1.1
<br/>&#160;&#160; <br/>&#160;&#160;
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b> <a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span> </a> altera_avalon_timer 18.1</span>
@ -1766,7 +1766,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a name="module_sem"> </a> <a name="module_sem"> </a>
<div> <div>
<hr/> <hr/>
<h2>sem</h2>sem v1.0 <h2>sem</h2>sem v1.1
<br/> <br/>
<div class="greydiv"> <div class="greydiv">
<table class="connectionboxes"> <table class="connectionboxes">
@ -1821,7 +1821,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table> <table>
<tr> <tr>
<td class="parametername">m</td> <td class="parametername">m</td>
<td class="parametervalue">8</td> <td class="parametervalue">32</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">deviceFamily</td> <td class="parametername">deviceFamily</td>
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div> </div>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0,01 seconds</td> <td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,04 seconds</td> <td class="r">rendering took 0,11 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

178
Top/niosII/niosII.xml
View File

File diff suppressed because one or more lines are too long

12
Top/niosII/synthesis/niosII.debuginfo
View File

@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS"> <EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2022.10.24.17:48:33 --> <!-- 2022.12.17.15:20:44 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="clockCrossingAdapter"> <parameter name="clockCrossingAdapter">
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type> <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@ -53,7 +53,7 @@
</parameter> </parameter>
<parameter name="generationId"> <parameter name="generationId">
<type>int</type> <type>int</type>
<value>1666619281</value> <value>1671276008</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -5673,12 +5673,12 @@ parameters are a RESULT of the module parameters. -->
</port> </port>
</interface> </interface>
</module> </module>
<module name="sem" kind="sem" version="1.0" path="sem"> <module name="sem" kind="sem" version="1.1" path="sem">
<!-- Describes a single module. Module parameters are <!-- Describes a single module. Module parameters are
the requested settings for a module instance. --> the requested settings for a module instance. -->
<parameter name="m"> <parameter name="m">
<type>int</type> <type>int</type>
<value>8</value> <value>32</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -12834,7 +12834,7 @@ parameters are a RESULT of the module parameters. -->
<type>com.altera.entityinterfaces.IElementClass</type> <type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype> <subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Semafor</displayName> <displayName>Semafor</displayName>
<version>1.0</version> <version>1.1</version>
</plugin> </plugin>
<plugin> <plugin>
<instanceCount>1</instanceCount> <instanceCount>1</instanceCount>
@ -12925,5 +12925,5 @@ parameters are a RESULT of the module parameters. -->
<version>18.1</version> <version>18.1</version>
</plugin> </plugin>
<reportVersion>18.1 625</reportVersion> <reportVersion>18.1 625</reportVersion>
<uniqueIdentifier>7A31C1D08890000001840A4024CB</uniqueIdentifier> <uniqueIdentifier>7A31C1D08890000001851FD02AF4</uniqueIdentifier>
</EnsembleReport> </EnsembleReport>

8
Top/niosII/synthesis/niosII.qip
View File

@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys" set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"] set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1666619281" set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1671276008"
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"] set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"] set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY2NjYxOTI4MQ==::QXV0byBHRU5FUkFUSU9OX0lE" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3MTI3NjAwOA==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U=" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxMTVGMjlDNw==::QXV0byBERVZJQ0U="
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::Nw==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@ -666,8 +666,8 @@ set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_NAME "Z
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "U2VtYWZvcg==" set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "U2VtYWZvcg=="
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_VERSION "MS4w" set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_VERSION "MS4x"
set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_PARAMETER "bQ==::OA==::bQ==" set_global_assignment -entity "dec" -library "niosII" -name IP_COMPONENT_PARAMETER "bQ==::MzI=::bQ=="
set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21lbQ==" set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21lbQ=="
set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00pIEludGVsIEZQR0EgSVA=" set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00pIEludGVsIEZQR0EgSVA="
set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off" set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"

2
Top/niosII/synthesis/niosII.v
View File

@ -137,7 +137,7 @@ module niosII (
); );
dec #( dec #(
.m (8) .m (32)
) sem ( ) sem (
.clk (clk_clk), // clock.clk .clk (clk_clk), // clock.clk
.ctl_wr (mm_interconnect_0_sem_ctl_slave_write), // ctl_slave.write .ctl_wr (mm_interconnect_0_sem_ctl_slave_write), // ctl_slave.write

2
Top/niosII/synthesis/submodules/dec.sv
View File

@ -1,5 +1,5 @@
module dec module dec
#(m = 8) #(m = 32)
( (
//clock and reset //clock and reset
input logic clk, clrn, input logic clk, clrn,

55
Top/niosII/synthesis/submodules/periodram.v
View File

@ -14,24 +14,23 @@
// ************************************************************ // ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// //
// 14.0.2 Build 209 09/17/2014 SJ Full Version // 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************ // ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved. //Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions //Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic //and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing //functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any //(including device programming or simulation files), and any
//associated documentation or information are expressly subject //associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License //to the terms and conditions of the Intel Program License
//Subscription Agreement, the Altera Quartus II License Agreement, //Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other //the Intel FPGA IP License Agreement, or other applicable license
//applicable license agreement, including, without limitation, //agreement, including, without limitation, that your use is for
//that your use is for the sole purpose of programming logic //the sole purpose of programming logic devices manufactured by
//devices manufactured by Altera and sold by Altera or its //Intel and sold by Intel or its authorized distributors. Please
//authorized distributors. Please refer to the applicable //refer to the applicable agreement for further details.
//agreement for further details.
// synopsys translate_off // synopsys translate_off
@ -47,10 +46,10 @@ module periodram (
input clock; input clock;
input [31:0] data; input [31:0] data;
input [3:0] rdaddress; input [1:0] rdaddress;
input [1:0] wraddress; input [1:0] wraddress;
input wren; input wren;
output [7:0] q; output [31:0] q;
`ifndef ALTERA_RESERVED_QIS `ifndef ALTERA_RESERVED_QIS
// synopsys translate_off // synopsys translate_off
`endif `endif
@ -60,8 +59,8 @@ module periodram (
// synopsys translate_on // synopsys translate_on
`endif `endif
wire [7:0] sub_wire0; wire [31:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0]; wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component ( altsyncram altsyncram_component (
.address_a (wraddress), .address_a (wraddress),
@ -81,7 +80,7 @@ module periodram (
.clocken1 (1'b1), .clocken1 (1'b1),
.clocken2 (1'b1), .clocken2 (1'b1),
.clocken3 (1'b1), .clocken3 (1'b1),
.data_b ({8{1'b1}}), .data_b ({32{1'b1}}),
.eccstatus (), .eccstatus (),
.q_a (), .q_a (),
.rden_a (1'b1), .rden_a (1'b1),
@ -96,16 +95,16 @@ module periodram (
altsyncram_component.intended_device_family = "Cyclone IV E", altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4, altsyncram_component.numwords_a = 4,
altsyncram_component.numwords_b = 16, altsyncram_component.numwords_b = 4,
altsyncram_component.operation_mode = "DUAL_PORT", altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 2, altsyncram_component.widthad_a = 2,
altsyncram_component.widthad_b = 4, altsyncram_component.widthad_b = 2,
altsyncram_component.width_a = 32, altsyncram_component.width_a = 32,
altsyncram_component.width_b = 8, altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1; altsyncram_component.width_byteena_a = 1;
@ -165,9 +164,9 @@ endmodule
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1" // Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8" // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8" // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
@ -182,29 +181,29 @@ endmodule
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4" // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2" // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "2"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]" // Retrieval info: USED_PORT: rdaddress 0 0 2 0 INPUT NODEFVAL "rdaddress[1..0]"
// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]" // Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0 // Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0 // Retrieval info: CONNECT: @address_b 0 0 2 0 rdaddress 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0 // Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE

2
Top/niosII/testbench/mentor/msim_setup.tcl
View File

@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2022.10.24.18:26:02 # ACDS 18.1 625 win32 2022.12.19.20:25:08
# ---------------------------------------- # ----------------------------------------
# Initialize variables # Initialize variables

12
Top/niosII/testbench/niosII.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2022.10.24.18:25:23</td> <td class="l">2022.12.19.20:24:19</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</a> altera_avalon_onchip_memory2 18.1 </a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160; <br/>&#160;&#160;
<a href="#module_sem"><b>sem</b> <a href="#module_sem"><b>sem</b>
</a> sem 1.0 </a> sem 1.1
<br/>&#160;&#160; <br/>&#160;&#160;
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b> <a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span> </a> altera_avalon_timer 18.1</span>
@ -1766,7 +1766,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a name="module_sem"> </a> <a name="module_sem"> </a>
<div> <div>
<hr/> <hr/>
<h2>sem</h2>sem v1.0 <h2>sem</h2>sem v1.1
<br/> <br/>
<div class="greydiv"> <div class="greydiv">
<table class="connectionboxes"> <table class="connectionboxes">
@ -1821,7 +1821,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table> <table>
<tr> <tr>
<td class="parametername">m</td> <td class="parametername">m</td>
<td class="parametervalue">8</td> <td class="parametervalue">32</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">deviceFamily</td> <td class="parametername">deviceFamily</td>
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div> </div>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0,00 seconds</td> <td class="l">generation took 0,01 seconds</td>
<td class="r">rendering took 0,04 seconds</td> <td class="r">rendering took 0,07 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

12
Top/niosII/testbench/niosII_tb.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2022.10.24.18:25:32</td> <td class="l">2022.12.19.20:24:29</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -101,7 +101,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</a> altera_avalon_onchip_memory2 18.1 </a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160; <br/>&#160;&#160;
<a href="#module_niosII_inst_sem"><b>niosII_inst_sem</b> <a href="#module_niosII_inst_sem"><b>niosII_inst_sem</b>
</a> sem 1.0 </a> sem 1.1
<br/>&#160;&#160; <br/>&#160;&#160;
<a href="#module_niosII_inst_sys_clk_timer"><b>niosII_inst_sys_clk_timer</b> <a href="#module_niosII_inst_sys_clk_timer"><b>niosII_inst_sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span> </a> altera_avalon_timer 18.1</span>
@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table> <table>
<tr> <tr>
<td class="parametername">AUTO_GENERATION_ID</td> <td class="parametername">AUTO_GENERATION_ID</td>
<td class="parametervalue">1666621532</td> <td class="parametervalue">1671467069</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">AUTO_UNIQUE_ID</td> <td class="parametername">AUTO_UNIQUE_ID</td>
@ -1982,7 +1982,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a name="module_niosII_inst_sem"> </a> <a name="module_niosII_inst_sem"> </a>
<div> <div>
<hr/> <hr/>
<h2>niosII_inst_sem</h2>sem v1.0 <h2>niosII_inst_sem</h2>sem v1.1
<br/> <br/>
<div class="greydiv"> <div class="greydiv">
<table class="connectionboxes"> <table class="connectionboxes">
@ -2037,7 +2037,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table> <table>
<tr> <tr>
<td class="parametername">m</td> <td class="parametername">m</td>
<td class="parametervalue">8</td> <td class="parametervalue">32</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">deviceFamily</td> <td class="parametername">deviceFamily</td>
@ -2360,7 +2360,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0,00 seconds</td> <td class="l">generation took 0,00 seconds</td>
<td class="r">rendering took 0,05 seconds</td> <td class="r">rendering took 0,04 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

4
Top/niosII/testbench/synopsys/vcs/vcs_setup.sh
View File

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 18.1 625 win32 2022.10.24.18:26:02 # ACDS 18.1 625 win32 2022.12.19.20:25:08
# ---------------------------------------- # ----------------------------------------
# vcs - auto-generated simulation script # vcs - auto-generated simulation script
@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2022.10.24.18:26:02 # ACDS 18.1 625 win32 2022.12.19.20:25:08
# ---------------------------------------- # ----------------------------------------
# initialize variables # initialize variables
TOP_LEVEL_NAME="niosII_tb" TOP_LEVEL_NAME="niosII_tb"

4
Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh
View File

@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 18.1 625 win32 2022.10.24.18:26:03 # ACDS 18.1 625 win32 2022.12.19.20:25:08
# ---------------------------------------- # ----------------------------------------
# vcsmx - auto-generated simulation script # vcsmx - auto-generated simulation script
@ -107,7 +107,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2022.10.24.18:26:03 # ACDS 18.1 625 win32 2022.12.19.20:25:08
# ---------------------------------------- # ----------------------------------------
# initialize variables # initialize variables
TOP_LEVEL_NAME="niosII_tb" TOP_LEVEL_NAME="niosII_tb"

6
Top/niosII_tb.csv
View File

@ -1,12 +1,12 @@
# system info niosII_tb on 2022.10.24.18:26:01 # system info niosII_tb on 2022.12.19.20:25:06
system_info: system_info:
name,value name,value
DEVICE,EP4CE115F29C7 DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1666621532 GENERATION_ID,1671467069
# #
# #
# Files generated for niosII_tb on 2022.10.24.18:26:01 # Files generated for niosII_tb on 2022.12.19.20:25:06
files: files:
filepath,kind,attributes,module,is_top filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true

1 # system info niosII_tb on 2022.10.24.18:26:01 # system info niosII_tb on 2022.12.19.20:25:06
2 system_info: system_info:
3 name,value name,value
4 DEVICE,EP4CE115F29C7 DEVICE,EP4CE115F29C7
5 DEVICE_FAMILY,Cyclone IV E DEVICE_FAMILY,Cyclone IV E
6 GENERATION_ID,1666621532 GENERATION_ID,1671467069
7 # #
8 # #
9 # Files generated for niosII_tb on 2022.10.24.18:26:01 # Files generated for niosII_tb on 2022.12.19.20:25:06
10 files: files:
11 filepath,kind,attributes,module,is_top filepath,kind,attributes,module,is_top
12 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true

3
Top/semafor.qsf
View File

@ -50,10 +50,11 @@ set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)" set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name QSYS_FILE niosII.qsys
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SOURCE_FILE niosII/niosII.cmp
set_global_assignment -name QSYS_FILE niosII.qsys
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf
View File

Binary file not shown.

908
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map
View File

File diff suppressed because it is too large Load Diff

11499
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump
View File

File diff suppressed because it is too large Load Diff

11597
Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat
View File

File diff suppressed because it is too large Load Diff

314
Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym
View File

@ -7,163 +7,163 @@
00000230 T _start 00000230 T _start
00000244 t alt_after_alt_main 00000244 t alt_after_alt_main
00000248 T main 00000248 T main
00000330 T _puts_r 00000334 T _puts_r
000003f0 T puts 000003f4 T puts
00000404 T strlen 00000408 T strlen
0000049c t __fp_unlock 000004a0 t __fp_unlock
000004a4 T _cleanup_r 000004a8 T _cleanup_r
000004b0 t __sinit.part.1 000004b4 t __sinit.part.1
0000064c t __fp_lock 00000650 t __fp_lock
00000654 T __sfmoreglue 00000658 T __sfmoreglue
000006cc T __sfp 000006d0 T __sfp
000007e4 T _cleanup 000007e8 T _cleanup
000007fc T __sinit 00000800 T __sinit
0000080c T __sfp_lock_acquire 00000810 T __sfp_lock_acquire
00000810 T __sfp_lock_release 00000814 T __sfp_lock_release
00000814 T __sinit_lock_acquire 00000818 T __sinit_lock_acquire
00000818 T __sinit_lock_release 0000081c T __sinit_lock_release
0000081c T __fp_lock_all 00000820 T __fp_lock_all
00000834 T __fp_unlock_all 00000838 T __fp_unlock_all
0000084c T __sfvwrite_r 00000850 T __sfvwrite_r
00000d14 T _fwalk 00000d18 T _fwalk
00000dd8 T _fwalk_reent 00000ddc T _fwalk_reent
00000e9c T _malloc_r 00000ea0 T _malloc_r
000016a8 T memchr 000016ac T memchr
0000178c T memcpy 00001790 T memcpy
000018d4 T memmove 000018d8 T memmove
00001a30 T memset 00001a34 T memset
00001b58 T _realloc_r 00001b5c T _realloc_r
000020bc T _sbrk_r 000020c0 T _sbrk_r
00002110 T __sread 00002114 T __sread
00002164 T __seofread 00002168 T __seofread
0000216c T __swrite 00002170 T __swrite
000021e8 T __sseek 000021ec T __sseek
00002244 T __sclose 00002248 T __sclose
0000224c T _write_r 00002250 T _write_r
000022ac T __swsetup_r 000022b0 T __swsetup_r
00002400 T _close_r 00002404 T _close_r
00002454 T _fclose_r 00002458 T _fclose_r
00002544 T fclose 00002548 T fclose
00002558 T __sflush_r 0000255c T __sflush_r
00002774 T _fflush_r 00002778 T _fflush_r
000027d0 T fflush 000027d4 T fflush
00002800 T _malloc_trim_r 00002804 T _malloc_trim_r
00002924 T _free_r 00002928 T _free_r
00002c34 T _lseek_r 00002c38 T _lseek_r
00002c94 T __smakebuf_r 00002c98 T __smakebuf_r
00002e50 T _read_r 00002e54 T _read_r
00002eb0 T _fstat_r 00002eb4 T _fstat_r
00002f0c T _isatty_r 00002f10 T _isatty_r
00002f60 T __divsi3 00002f64 T __divsi3
00002fe4 T __modsi3 00002fe8 T __modsi3
00003058 T __udivsi3 0000305c T __udivsi3
000030bc T __umodsi3 000030c0 T __umodsi3
00003114 T __mulsi3 00003118 T __mulsi3
0000313c t alt_get_errno 00003140 t alt_get_errno
00003178 T close 0000317c T close
00003250 T alt_dcache_flush 00003254 T alt_dcache_flush
00003278 t alt_dev_null_write 0000327c t alt_dev_null_write
000032a4 t alt_get_errno 000032a8 t alt_get_errno
000032e0 T fstat 000032e4 T fstat
00003398 t alt_get_errno 0000339c t alt_get_errno
000033d4 T isatty 000033d8 T isatty
00003480 t alt_get_errno 00003484 t alt_get_errno
000034bc T lseek 000034c0 T lseek
00003598 T alt_main 0000359c T alt_main
00003614 T __malloc_lock 00003618 T __malloc_lock
00003638 T __malloc_unlock 0000363c T __malloc_unlock
0000365c t alt_get_errno 00003660 t alt_get_errno
00003698 T read 0000369c T read
0000379c T alt_release_fd 000037a0 T alt_release_fd
00003820 T sbrk 00003824 T sbrk
000038d0 t alt_get_errno 000038d4 t alt_get_errno
0000390c T write 00003910 T write
00003a0c t alt_dev_reg 00003a10 t alt_dev_reg
00003a40 T alt_irq_init 00003a44 T alt_irq_init
00003a78 T alt_sys_init 00003a7c T alt_sys_init
00003ad8 T altera_avalon_jtag_uart_read_fd 00003adc T altera_avalon_jtag_uart_read_fd
00003b38 T altera_avalon_jtag_uart_write_fd 00003b3c T altera_avalon_jtag_uart_write_fd
00003b98 T altera_avalon_jtag_uart_close_fd 00003b9c T altera_avalon_jtag_uart_close_fd
00003be8 T altera_avalon_jtag_uart_ioctl_fd 00003bec T altera_avalon_jtag_uart_ioctl_fd
00003c3c T altera_avalon_jtag_uart_init 00003c40 T altera_avalon_jtag_uart_init
00003cfc t altera_avalon_jtag_uart_irq 00003d00 t altera_avalon_jtag_uart_irq
00003f08 t altera_avalon_jtag_uart_timeout 00003f0c t altera_avalon_jtag_uart_timeout
00003fa8 T altera_avalon_jtag_uart_close 00003fac T altera_avalon_jtag_uart_close
00004010 T altera_avalon_jtag_uart_ioctl 00004014 T altera_avalon_jtag_uart_ioctl
00004100 T altera_avalon_jtag_uart_read 00004104 T altera_avalon_jtag_uart_read
0000431c T altera_avalon_jtag_uart_write 00004320 T altera_avalon_jtag_uart_write
00004540 t alt_avalon_timer_sc_irq 00004544 t alt_avalon_timer_sc_irq
000045b8 T alt_avalon_timer_sc_init 000045bc T alt_avalon_timer_sc_init
00004634 T alt_alarm_start 00004638 T alt_alarm_start
00004760 t alt_get_errno 00004764 t alt_get_errno
0000479c T alt_dev_llist_insert 000047a0 T alt_dev_llist_insert
00004840 T _do_ctors 00004844 T _do_ctors
000048a0 T _do_dtors 000048a4 T _do_dtors
00004900 T alt_ic_isr_register 00004904 T alt_ic_isr_register
00004950 T alt_ic_irq_enable 00004954 T alt_ic_irq_enable
000049d8 T alt_ic_irq_disable 000049dc T alt_ic_irq_disable
00004a64 T alt_ic_irq_enabled 00004a68 T alt_ic_irq_enabled
00004ab0 T alt_iic_isr_register 00004ab4 T alt_iic_isr_register
00004ba0 t alt_open_fd 00004ba4 t alt_open_fd
00004c84 T alt_io_redirect 00004c88 T alt_io_redirect
00004d00 t alt_get_errno 00004d04 t alt_get_errno
00004d3c t alt_file_locked 00004d40 t alt_file_locked
00004e28 T open 00004e2c T open
00004f84 T alt_alarm_stop 00004f88 T alt_alarm_stop
00005020 T alt_tick 00005024 T alt_tick
00005128 T altera_nios2_gen2_irq_init 0000512c T altera_nios2_gen2_irq_init
0000514c T alt_find_dev 00005150 T alt_find_dev
000051dc T alt_find_file 000051e0 T alt_find_file
000052e4 T alt_get_fd 000052e8 T alt_get_fd
000053a8 T alt_exception_cause_generated_bad_addr 000053ac T alt_exception_cause_generated_bad_addr
00005444 T atexit 00005448 T atexit
00005458 T exit 0000545c T exit
00005490 T memcmp 00005494 T memcmp
0000550c T __register_exitproc 00005510 T __register_exitproc
00005624 T __call_exitprocs 00005628 T __call_exitprocs
000057a4 T _exit 000057a8 T _exit
000057d8 A __CTOR_END__ 000057dc A __CTOR_END__
000057d8 A __CTOR_LIST__ 000057dc A __CTOR_LIST__
000057d8 A __DTOR_END__ 000057dc A __DTOR_END__
000057d8 A __DTOR_LIST__ 000057dc A __DTOR_LIST__
000057d8 R divisors 000057dc R divisors
00005824 g impure_data 00005858 g impure_data
00005c48 G __malloc_av_ 00005c7c G __malloc_av_
00006050 G alt_dev_null 00006084 G alt_dev_null
00006078 G alt_fd_list 000060ac G alt_fd_list
000061f8 g jtag_uart 0000622c g jtag_uart
00007258 G _global_impure_ptr 0000728c G _global_impure_ptr
0000725c G _impure_ptr 00007290 G _impure_ptr
00007260 G __malloc_sbrk_base 00007294 G __malloc_sbrk_base
00007264 G __malloc_trim_threshold 00007298 G __malloc_trim_threshold
00007268 G alt_fs_list 0000729c G alt_fs_list
00007270 G alt_dev_list 000072a4 G alt_dev_list
00007278 G alt_max_fd 000072ac G alt_max_fd
0000727c G alt_errno 000072b0 G alt_errno
00007280 g heap_end 000072b4 g heap_end
00007284 G alt_priority_mask 000072b8 G alt_priority_mask
00007288 G alt_alarm_list 000072bc G alt_alarm_list
00007290 A __bss_start 000072c4 A __bss_start
00007290 B __malloc_max_total_mem 000072c4 B __malloc_max_total_mem
00007290 A _edata 000072c4 A _edata
00007294 B __malloc_max_sbrked_mem 000072c8 B __malloc_max_sbrked_mem
00007298 B __malloc_top_pad 000072cc B __malloc_top_pad
0000729c B errno 000072d0 B errno
000072a0 B alt_argc 000072d4 B alt_argc
000072a4 B alt_argv 000072d8 B alt_argv
000072a8 B alt_envp 000072dc B alt_envp
000072ac B alt_irq_active 000072e0 B alt_irq_active
000072b0 B _alt_tick_rate 000072e4 B _alt_tick_rate
000072b4 B _alt_nticks 000072e8 B _alt_nticks
000072b8 B alt_instruction_exception_handler 000072ec B alt_instruction_exception_handler
000072bc B __malloc_current_mallinfo 000072f0 B __malloc_current_mallinfo
000072e4 B alt_irq 00007318 B alt_irq
000073e4 A __alt_heap_start 00007418 A __alt_heap_start
000073e4 A __alt_stack_base 00007418 A __alt_stack_base
000073e4 A __bss_end 00007418 A __bss_end
000073e4 A _end 00007418 A _end
000073e4 A end 00007418 A end
0000f258 A _gp 0000f28c A _gp
00020000 A __alt_data_end 00020000 A __alt_data_end
00020000 A __alt_heap_limit 00020000 A __alt_heap_limit
00020000 A __alt_stack_pointer 00020000 A __alt_stack_pointer

1482
Top/software/semafor/mem_init/niosII_mem.hex
View File

File diff suppressed because it is too large Load Diff

10
Top/software/semafor/sem.c
View File

@ -5,11 +5,11 @@
#define TIME_SETS 4 #define TIME_SETS 4
#define TIME_STATES 4 #define TIME_STATES 4
const alt_u8 divisors[TIME_SETS][TIME_STATES] = { const alt_u32 divisors[TIME_SETS][TIME_STATES] = {
{100,100, 50,10}, {0x100000, 0x100000, 0x50000, 0x10000},
{100,200,100,10}, {0x100000, 0x200000, 0x100000, 0x10000},
{150,250,200,10}, {0x150000, 0x250000, 0x200000, 0x10000},
{250,250,250,10} {0x250000, 0x250000, 0x250000, 0x10000}
}; };
int main() int main()

4
Top/software/semafor_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema"> <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType> <BspType>hal</BspType>
<BspVersion>default</BspVersion> <BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>31.10.2022 15:40:20</BspGeneratedTimeStamp> <BspGeneratedTimeStamp>17.12.2022 15:27:50</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1667216420635</BspGeneratedUnixTimeStamp> <BspGeneratedUnixTimeStamp>1671276470966</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation> <BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile> <BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile> <SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>

4
Top/software/semafor_bsp/summary.html
View File

@ -22,10 +22,10 @@
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td> <td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>31.10.2022 15:40:20</td> <td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>17.12.2022 15:27:50</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1667216420635</td> <td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671276470966</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td> <td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>