added ram hex(no luck)
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parent
f6e75a12d5
commit
6291090406
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@ -92,6 +92,13 @@ module periodram (
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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`ifdef NO_PLI
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altsyncram_component.init_file = "periodram.rif"
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`else
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altsyncram_component.init_file = "periodram.hex"
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`endif
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,
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altsyncram_component.init_file_layout = "PORT_B",
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.intended_device_family = "Cyclone IV E",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 16,
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altsyncram_component.numwords_a = 16,
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@ -120,7 +127,7 @@ endmodule
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// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
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@ -145,7 +152,7 @@ endmodule
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
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// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
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// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
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// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
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// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
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@ -178,6 +185,8 @@ endmodule
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
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// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
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// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
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@ -64,4 +64,5 @@ set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulatio
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
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set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
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set_global_assignment -name HEX_FILE periodram.hex
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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Binary file not shown.
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@ -0,0 +1,17 @@
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:040000000000006498
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:040001000000006497
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:0400020000000032C8
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:040003000000000AEF
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:040004000000006494
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:04000500000000C82F
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:040006000000006492
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:040007000000000AEB
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:04000800000000965E
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:04000900000000FAF9
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:04000A00000000C82A
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:04000B000000000AE7
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:04000C00000000FAF6
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:04000D00000000FAF5
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:04000E00000000FAF4
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:04000F000000000AE3
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:00000001FF
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@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
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<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
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<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
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<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
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<!-- 2022.12.21.21:03:50 -->
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<!-- 2022.12.22.17:19:01 -->
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<!-- A collection of modules and connections -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<type>java.lang.Integer</type>
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<value>1671642230</value>
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<value>1671715140</value>
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<derived>false</derived>
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<derived>false</derived>
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<enabled>true</enabled>
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<enabled>true</enabled>
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<visible>false</visible>
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<visible>false</visible>
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@ -4,14 +4,16 @@ module niosII_tb (
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wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
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wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
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wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
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wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
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reg train;
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wire red, yellow, green;
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niosII niosii_inst (
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niosII niosii_inst (
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.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
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.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
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.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
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.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
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.sem_export_train (), // sem_export.train
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.sem_export_train (train), // sem_export.train
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.sem_export_red (), // .red
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.sem_export_red (red), // .red
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.sem_export_yellow (), // .yellow
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.sem_export_yellow (yellow), // .yellow
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.sem_export_green () // .green
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.sem_export_green (green) // .green
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);
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);
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altera_avalon_clock_source #(
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altera_avalon_clock_source #(
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@ -33,9 +35,9 @@ module niosII_tb (
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train = 0;
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train = 0;
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wait (niosii_inst_reset_bfm_reset_reset);
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wait (niosii_inst_reset_bfm_reset_reset);
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forever begin
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forever begin
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repeat (29000) @(posedge niosII_inst_clk_bfm_clk_clk);
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repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk);
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train = 1;
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train = 1;
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repeat (10) @(posedge niosII_inst_clk_bfm_clk_clk);
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repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
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train = 0;
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train = 0;
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end
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end
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end
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end
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@ -2,8 +2,8 @@
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<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
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<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
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<BspType>hal</BspType>
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<BspType>hal</BspType>
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<BspVersion>default</BspVersion>
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<BspVersion>default</BspVersion>
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<BspGeneratedTimeStamp>21.12.2022 21:06:52</BspGeneratedTimeStamp>
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<BspGeneratedTimeStamp>22.12.2022 17:21:19</BspGeneratedTimeStamp>
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<BspGeneratedUnixTimeStamp>1671642412929</BspGeneratedUnixTimeStamp>
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<BspGeneratedUnixTimeStamp>1671715279678</BspGeneratedUnixTimeStamp>
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<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
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<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation>
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<BspSettingsFile>settings.bsp</BspSettingsFile>
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<BspSettingsFile>settings.bsp</BspSettingsFile>
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<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
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<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile>
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@ -22,10 +22,10 @@
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<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
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<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
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</tr>
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</tr>
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<tr mode="wrap">
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<tr mode="wrap">
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<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>21.12.2022 21:06:52</td>
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<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>22.12.2022 17:21:19</td>
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</tr>
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</tr>
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<tr mode="wrap">
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<tr mode="wrap">
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<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671642412929</td>
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<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671715279678</td>
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</tr>
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</tr>
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<tr mode="wrap">
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<tr mode="wrap">
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<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
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<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td>
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