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work board parameters

This commit is contained in:
Ivan I. Ovchinnikov 2023-02-07 13:31:34 +03:00
parent dad79c26fb
commit b551fd0a26
44 changed files with 10099 additions and 25745 deletions
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36
Top/niosII.qsys
View File

@ -29,7 +29,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "133120"; value = "34816";
type = "String"; type = "String";
} }
} }
@ -45,7 +45,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "135200"; value = "36896";
type = "String"; type = "String";
} }
} }
@ -117,7 +117,7 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "135208"; value = "36904";
type = "String"; type = "String";
} }
} }
@ -133,16 +133,16 @@
{ {
datum baseAddress datum baseAddress
{ {
value = "135168"; value = "36864";
type = "String"; type = "String";
} }
} }
} }
]]></parameter> ]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" /> <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE115F29C7" /> <parameter name="device" value="EP4CE15F23C8" />
<parameter name="deviceFamily" value="Cyclone IV E" /> <parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="7" /> <parameter name="deviceSpeedGrade" value="8" />
<parameter name="fabricMode" value="QSYS" /> <parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" /> <parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" /> <parameter name="generationId" value="0" />
@ -174,8 +174,8 @@
<module name="cpu" kind="altera_nios2_gen2" version="18.1" enabled="1"> <module name="cpu" kind="altera_nios2_gen2" version="18.1" enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" /> <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" /> <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_DEVICE" value="EP4CE115F29C7" /> <parameter name="AUTO_DEVICE" value="EP4CE15F23C8" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" /> <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
<parameter name="bht_ramBlockType" value="Automatic" /> <parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" /> <parameter name="breakOffset" value="32" />
<parameter name="breakSlave" value="None" /> <parameter name="breakSlave" value="None" />
@ -188,10 +188,10 @@
<parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" /> <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" /> <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" /> <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
<parameter name="dataAddrWidth" value="18" /> <parameter name="dataAddrWidth" value="16" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" /> <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" /> <parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21020' end='0x21028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x21028' end='0x2102C' type='sigdel.avalon_slave' /></address-map>]]></parameter> <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" /> <parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" /> <parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" /> <parameter name="data_master_paddr_base" value="0" />
@ -229,8 +229,8 @@
<parameter name="icache_size" value="4096" /> <parameter name="icache_size" value="4096" />
<parameter name="icache_tagramBlockType" value="Automatic" /> <parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Tiny" /> <parameter name="impl" value="Tiny" />
<parameter name="instAddrWidth" value="18" /> <parameter name="instAddrWidth" value="16" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter> <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" /> <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" /> <parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" /> <parameter name="instruction_master_high_performance_paddr_base" value="0" />
@ -388,7 +388,7 @@
<parameter name="initMemContent" value="true" /> <parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_mem.hex" /> <parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" /> <parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="131072" /> <parameter name="memorySize" value="32768" />
<parameter name="readDuringWriteMode" value="DONT_CARE" /> <parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" /> <parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" /> <parameter name="simAllowMRAMContentsFile" value="false" />
@ -425,7 +425,7 @@
start="cpu.data_master" start="cpu.data_master"
end="jtag_uart.avalon_jtag_slave"> end="jtag_uart.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021020" /> <parameter name="baseAddress" value="0x9020" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection <connection
@ -434,7 +434,7 @@
start="cpu.data_master" start="cpu.data_master"
end="sigdel_0.avalon_slave"> end="sigdel_0.avalon_slave">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021028" /> <parameter name="baseAddress" value="0x9028" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection <connection
@ -443,7 +443,7 @@
start="cpu.data_master" start="cpu.data_master"
end="cpu.debug_mem_slave"> end="cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00020800" /> <parameter name="baseAddress" value="0x8800" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection <connection
@ -452,7 +452,7 @@
start="cpu.data_master" start="cpu.data_master"
end="sys_clk_timer.s1"> end="sys_clk_timer.s1">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021000" /> <parameter name="baseAddress" value="0x9000" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2"> <connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2">
@ -466,7 +466,7 @@
start="cpu.instruction_master" start="cpu.instruction_master"
end="cpu.debug_mem_slave"> end="cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" /> <parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00020800" /> <parameter name="baseAddress" value="0x8800" />
<parameter name="defaultConnection" value="false" /> <parameter name="defaultConnection" value="false" />
</connection> </connection>
<connection <connection

76
Top/niosII.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS"> <EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) --> <!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2023.01.27.19:00:16 --> <!-- 2023.02.07.13:18:47 -->
<!-- A collection of modules and connections --> <!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID"> <parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type> <type>java.lang.Integer</type>
<value>1674831615</value> <value>1675761526</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -32,7 +32,7 @@
</parameter> </parameter>
<parameter name="AUTO_DEVICE"> <parameter name="AUTO_DEVICE">
<type>java.lang.String</type> <type>java.lang.String</type>
<value>EP4CE115F29C7</value> <value>EP4CE15F23C8</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -41,7 +41,7 @@
</parameter> </parameter>
<parameter name="AUTO_DEVICE_SPEEDGRADE"> <parameter name="AUTO_DEVICE_SPEEDGRADE">
<type>java.lang.String</type> <type>java.lang.String</type>
<value>7</value> <value>8</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -436,7 +436,7 @@ the requested settings for a module instance. -->
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.CMacro.BREAK_ADDR</name> <name>embeddedsw.CMacro.BREAK_ADDR</name>
<value>0x00020820</value> <value>0x00008820</value>
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</name> <name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</name>
@ -460,7 +460,7 @@ the requested settings for a module instance. -->
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.CMacro.DATA_ADDR_WIDTH</name> <name>embeddedsw.CMacro.DATA_ADDR_WIDTH</name>
<value>18</value> <value>16</value>
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.CMacro.DCACHE_LINE_SIZE</name> <name>embeddedsw.CMacro.DCACHE_LINE_SIZE</name>
@ -532,7 +532,7 @@ the requested settings for a module instance. -->
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.CMacro.INST_ADDR_WIDTH</name> <name>embeddedsw.CMacro.INST_ADDR_WIDTH</name>
<value>18</value> <value>16</value>
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.CMacro.OCI_VERSION</name> <name>embeddedsw.CMacro.OCI_VERSION</name>
@ -1772,7 +1772,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="breakAbsoluteAddr"> <parameter name="breakAbsoluteAddr">
<type>int</type> <type>int</type>
<value>133152</value> <value>34848</value>
<derived>true</derived> <derived>true</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -1884,7 +1884,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="instAddrWidth"> <parameter name="instAddrWidth">
<type>int</type> <type>int</type>
<value>18</value> <value>16</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -1904,7 +1904,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="dataAddrWidth"> <parameter name="dataAddrWidth">
<type>int</type> <type>int</type>
<value>18</value> <value>16</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -2014,7 +2014,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="instSlaveMapParam"> <parameter name="instSlaveMapParam">
<type>java.lang.String</type> <type>java.lang.String</type>
<value><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></value> <value><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -2034,7 +2034,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="dataSlaveMapParam"> <parameter name="dataSlaveMapParam">
<type>java.lang.String</type> <type>java.lang.String</type>
<value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21020' end='0x21028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x21028' end='0x2102C' type='sigdel.avalon_slave' /></address-map>]]></value> <value><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /></address-map>]]></value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -2222,7 +2222,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="AUTO_DEVICE"> <parameter name="AUTO_DEVICE">
<type>java.lang.String</type> <type>java.lang.String</type>
<value>EP4CE115F29C7</value> <value>EP4CE15F23C8</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -2231,7 +2231,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="AUTO_DEVICE_SPEEDGRADE"> <parameter name="AUTO_DEVICE_SPEEDGRADE">
<type>java.lang.String</type> <type>java.lang.String</type>
<value>7</value> <value>8</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -2655,7 +2655,7 @@ parameters are a RESULT of the module parameters. -->
<port> <port>
<name>d_address</name> <name>d_address</name>
<direction>Output</direction> <direction>Output</direction>
<width>18</width> <width>16</width>
<role>address</role> <role>address</role>
</port> </port>
<port> <port>
@ -2705,7 +2705,7 @@ parameters are a RESULT of the module parameters. -->
<moduleName>jtag_uart</moduleName> <moduleName>jtag_uart</moduleName>
<slaveName>avalon_jtag_slave</slaveName> <slaveName>avalon_jtag_slave</slaveName>
<name>jtag_uart.avalon_jtag_slave</name> <name>jtag_uart.avalon_jtag_slave</name>
<baseAddress>135200</baseAddress> <baseAddress>36896</baseAddress>
<span>8</span> <span>8</span>
</memoryBlock> </memoryBlock>
<memoryBlock> <memoryBlock>
@ -2713,7 +2713,7 @@ parameters are a RESULT of the module parameters. -->
<moduleName>sigdel_0</moduleName> <moduleName>sigdel_0</moduleName>
<slaveName>avalon_slave</slaveName> <slaveName>avalon_slave</slaveName>
<name>sigdel_0.avalon_slave</name> <name>sigdel_0.avalon_slave</name>
<baseAddress>135208</baseAddress> <baseAddress>36904</baseAddress>
<span>4</span> <span>4</span>
</memoryBlock> </memoryBlock>
<memoryBlock> <memoryBlock>
@ -2721,7 +2721,7 @@ parameters are a RESULT of the module parameters. -->
<moduleName>cpu</moduleName> <moduleName>cpu</moduleName>
<slaveName>debug_mem_slave</slaveName> <slaveName>debug_mem_slave</slaveName>
<name>cpu.debug_mem_slave</name> <name>cpu.debug_mem_slave</name>
<baseAddress>133120</baseAddress> <baseAddress>34816</baseAddress>
<span>2048</span> <span>2048</span>
</memoryBlock> </memoryBlock>
<memoryBlock> <memoryBlock>
@ -2729,7 +2729,7 @@ parameters are a RESULT of the module parameters. -->
<moduleName>sys_clk_timer</moduleName> <moduleName>sys_clk_timer</moduleName>
<slaveName>s1</slaveName> <slaveName>s1</slaveName>
<name>sys_clk_timer.s1</name> <name>sys_clk_timer.s1</name>
<baseAddress>135168</baseAddress> <baseAddress>36864</baseAddress>
<span>32</span> <span>32</span>
</memoryBlock> </memoryBlock>
<memoryBlock> <memoryBlock>
@ -2738,7 +2738,7 @@ parameters are a RESULT of the module parameters. -->
<slaveName>s2</slaveName> <slaveName>s2</slaveName>
<name>mem.s2</name> <name>mem.s2</name>
<baseAddress>0</baseAddress> <baseAddress>0</baseAddress>
<span>131072</span> <span>32768</span>
</memoryBlock> </memoryBlock>
</interface> </interface>
<interface name="instruction_master" kind="avalon_master" version="18.1"> <interface name="instruction_master" kind="avalon_master" version="18.1">
@ -3006,7 +3006,7 @@ parameters are a RESULT of the module parameters. -->
<port> <port>
<name>i_address</name> <name>i_address</name>
<direction>Output</direction> <direction>Output</direction>
<width>18</width> <width>16</width>
<role>address</role> <role>address</role>
</port> </port>
<port> <port>
@ -3032,7 +3032,7 @@ parameters are a RESULT of the module parameters. -->
<moduleName>cpu</moduleName> <moduleName>cpu</moduleName>
<slaveName>debug_mem_slave</slaveName> <slaveName>debug_mem_slave</slaveName>
<name>cpu.debug_mem_slave</name> <name>cpu.debug_mem_slave</name>
<baseAddress>133120</baseAddress> <baseAddress>34816</baseAddress>
<span>2048</span> <span>2048</span>
</memoryBlock> </memoryBlock>
<memoryBlock> <memoryBlock>
@ -3041,7 +3041,7 @@ parameters are a RESULT of the module parameters. -->
<slaveName>s1</slaveName> <slaveName>s1</slaveName>
<name>mem.s1</name> <name>mem.s1</name>
<baseAddress>0</baseAddress> <baseAddress>0</baseAddress>
<span>131072</span> <span>32768</span>
</memoryBlock> </memoryBlock>
</interface> </interface>
<interface name="irq" kind="interrupt_receiver" version="18.1"> <interface name="irq" kind="interrupt_receiver" version="18.1">
@ -4460,7 +4460,7 @@ the requested settings for a module instance. -->
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.CMacro.SIZE_VALUE</name> <name>embeddedsw.CMacro.SIZE_VALUE</name>
<value>131072</value> <value>32768</value>
</assignment> </assignment>
<assignment> <assignment>
<name>embeddedsw.CMacro.WRITABLE</name> <name>embeddedsw.CMacro.WRITABLE</name>
@ -4592,7 +4592,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="memorySize"> <parameter name="memorySize">
<type>long</type> <type>long</type>
<value>131072</value> <value>32768</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -4731,7 +4731,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="derived_set_addr_width"> <parameter name="derived_set_addr_width">
<type>int</type> <type>int</type>
<value>15</value> <value>13</value>
<derived>true</derived> <derived>true</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -4739,7 +4739,7 @@ the requested settings for a module instance. -->
</parameter> </parameter>
<parameter name="derived_set_addr_width2"> <parameter name="derived_set_addr_width2">
<type>int</type> <type>int</type>
<value>15</value> <value>13</value>
<derived>true</derived> <derived>true</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -4831,7 +4831,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="addressSpan"> <parameter name="addressSpan">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>131072</value> <value>32768</value>
<derived>true</derived> <derived>true</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -4919,7 +4919,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="explicitAddressSpan"> <parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>131072</value> <value>32768</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -5130,7 +5130,7 @@ parameters are a RESULT of the module parameters. -->
<port> <port>
<name>address</name> <name>address</name>
<direction>Input</direction> <direction>Input</direction>
<width>15</width> <width>13</width>
<role>address</role> <role>address</role>
</port> </port>
<port> <port>
@ -5208,7 +5208,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="addressSpan"> <parameter name="addressSpan">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>131072</value> <value>32768</value>
<derived>true</derived> <derived>true</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>false</visible> <visible>false</visible>
@ -5296,7 +5296,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="explicitAddressSpan"> <parameter name="explicitAddressSpan">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>131072</value> <value>32768</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -5507,7 +5507,7 @@ parameters are a RESULT of the module parameters. -->
<port> <port>
<name>address2</name> <name>address2</name>
<direction>Input</direction> <direction>Input</direction>
<width>15</width> <width>13</width>
<role>address</role> <role>address</role>
</port> </port>
<port> <port>
@ -6952,7 +6952,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="baseAddress"> <parameter name="baseAddress">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>0x00021020</value> <value>0x9020</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -7003,7 +7003,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="baseAddress"> <parameter name="baseAddress">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>0x00021028</value> <value>0x9028</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -7054,7 +7054,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="baseAddress"> <parameter name="baseAddress">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>0x00020800</value> <value>0x8800</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -7105,7 +7105,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="baseAddress"> <parameter name="baseAddress">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>0x00021000</value> <value>0x9000</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>
@ -7207,7 +7207,7 @@ parameters are a RESULT of the module parameters. -->
</parameter> </parameter>
<parameter name="baseAddress"> <parameter name="baseAddress">
<type>java.math.BigInteger</type> <type>java.math.BigInteger</type>
<value>0x00020800</value> <value>0x8800</value>
<derived>false</derived> <derived>false</derived>
<enabled>true</enabled> <enabled>true</enabled>
<visible>true</visible> <visible>true</visible>

40
Top/niosII/niosII.html
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2023.01.27.18:49:31</td> <td class="l">2023.02.07.13:18:47</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -131,8 +131,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">debug_mem_slave&#160;</td> <td class="slaveb">debug_mem_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00020800</td> <td class="addr"><span style="color:#989898">0x</span>00008800</td>
<td class="addr"><span style="color:#989898">0x</span>00020800</td> <td class="addr"><span style="color:#989898">0x</span>00008800</td>
</tr> </tr>
<tr> <tr>
<td class="slavemodule">&#160; <td class="slavemodule">&#160;
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">avalon_jtag_slave&#160;</td> <td class="slaveb">avalon_jtag_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021020</td> <td class="addr"><span style="color:#989898">0x</span>00009020</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
@ -175,7 +175,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">avalon_slave&#160;</td> <td class="slaveb">avalon_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021028</td> <td class="addr"><span style="color:#989898">0x</span>00009028</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
<tr> <tr>
@ -188,7 +188,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="slaveb">s1&#160;</td> <td class="slaveb">s1&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021000</td> <td class="addr"><span style="color:#989898">0x</span>00009000</td>
<td class="empty"></td> <td class="empty"></td>
</tr> </tr>
</table> </table>
@ -976,7 +976,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">breakAbsoluteAddr</td> <td class="parametername">breakAbsoluteAddr</td>
<td class="parametervalue">133152</td> <td class="parametervalue">34848</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">mmu_TLBMissExcAbsAddr</td> <td class="parametername">mmu_TLBMissExcAbsAddr</td>
@ -1032,7 +1032,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">instAddrWidth</td> <td class="parametername">instAddrWidth</td>
<td class="parametervalue">18</td> <td class="parametervalue">16</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">faAddrWidth</td> <td class="parametername">faAddrWidth</td>
@ -1040,7 +1040,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">dataAddrWidth</td> <td class="parametername">dataAddrWidth</td>
<td class="parametervalue">18</td> <td class="parametervalue">16</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">tightlyCoupledDataMaster0AddrWidth</td> <td class="parametername">tightlyCoupledDataMaster0AddrWidth</td>
@ -1084,7 +1084,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">instSlaveMapParam</td> <td class="parametername">instSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td> <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">faSlaveMapParam</td> <td class="parametername">faSlaveMapParam</td>
@ -1092,7 +1092,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">dataSlaveMapParam</td> <td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21020' end='0x21028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='sigdel_0.avalon_slave' start='0x21028' end='0x2102C' type='sigdel.avalon_slave' /&gt;&lt;/address-map&gt;</td> <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /&gt;&lt;/address-map&gt;</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td> <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -1168,11 +1168,11 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">AUTO_DEVICE</td> <td class="parametername">AUTO_DEVICE</td>
<td class="parametervalue">EP4CE115F29C7</td> <td class="parametervalue">EP4CE15F23C8</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">AUTO_DEVICE_SPEEDGRADE</td> <td class="parametername">AUTO_DEVICE_SPEEDGRADE</td>
<td class="parametervalue">7</td> <td class="parametervalue">8</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">AUTO_CLK_CLOCK_DOMAIN</td> <td class="parametername">AUTO_CLK_CLOCK_DOMAIN</td>
@ -1205,7 +1205,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">BREAK_ADDR</td> <td class="parametername">BREAK_ADDR</td>
<td class="parametervalue">0x00020820</td> <td class="parametervalue">0x00008820</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">CPU_ARCH_NIOS2_R1</td> <td class="parametername">CPU_ARCH_NIOS2_R1</td>
@ -1229,7 +1229,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">DATA_ADDR_WIDTH</td> <td class="parametername">DATA_ADDR_WIDTH</td>
<td class="parametervalue">18</td> <td class="parametervalue">16</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">DCACHE_LINE_SIZE</td> <td class="parametername">DCACHE_LINE_SIZE</td>
@ -1301,7 +1301,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">INST_ADDR_WIDTH</td> <td class="parametername">INST_ADDR_WIDTH</td>
<td class="parametervalue">18</td> <td class="parametervalue">16</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">OCI_VERSION</td> <td class="parametername">OCI_VERSION</td>
@ -1576,7 +1576,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">memorySize</td> <td class="parametername">memorySize</td>
<td class="parametervalue">131072</td> <td class="parametervalue">32768</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">readDuringWriteMode</td> <td class="parametername">readDuringWriteMode</td>
@ -1644,11 +1644,11 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">derived_set_addr_width</td> <td class="parametername">derived_set_addr_width</td>
<td class="parametervalue">15</td> <td class="parametervalue">13</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">derived_set_addr_width2</td> <td class="parametername">derived_set_addr_width2</td>
<td class="parametervalue">15</td> <td class="parametervalue">13</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">derived_set_data_width</td> <td class="parametername">derived_set_data_width</td>
@ -1737,7 +1737,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr> </tr>
<tr> <tr>
<td class="parametername">SIZE_VALUE</td> <td class="parametername">SIZE_VALUE</td>
<td class="parametervalue">131072</td> <td class="parametervalue">32768</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">WRITABLE</td> <td class="parametername">WRITABLE</td>

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8
Top/niosII/synthesis/niosII.v
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@ -12,14 +12,14 @@ module niosII (
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [17:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address wire [15:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [17:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address wire [15:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
@ -45,14 +45,14 @@ module niosII (
wire [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata; // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata wire [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata; // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata
wire mm_interconnect_0_mem_s2_chipselect; // mm_interconnect_0:mem_s2_chipselect -> mem:chipselect2 wire mm_interconnect_0_mem_s2_chipselect; // mm_interconnect_0:mem_s2_chipselect -> mem:chipselect2
wire [31:0] mm_interconnect_0_mem_s2_readdata; // mem:readdata2 -> mm_interconnect_0:mem_s2_readdata wire [31:0] mm_interconnect_0_mem_s2_readdata; // mem:readdata2 -> mm_interconnect_0:mem_s2_readdata
wire [14:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2 wire [12:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2
wire [3:0] mm_interconnect_0_mem_s2_byteenable; // mm_interconnect_0:mem_s2_byteenable -> mem:byteenable2 wire [3:0] mm_interconnect_0_mem_s2_byteenable; // mm_interconnect_0:mem_s2_byteenable -> mem:byteenable2
wire mm_interconnect_0_mem_s2_write; // mm_interconnect_0:mem_s2_write -> mem:write2 wire mm_interconnect_0_mem_s2_write; // mm_interconnect_0:mem_s2_write -> mem:write2
wire [31:0] mm_interconnect_0_mem_s2_writedata; // mm_interconnect_0:mem_s2_writedata -> mem:writedata2 wire [31:0] mm_interconnect_0_mem_s2_writedata; // mm_interconnect_0:mem_s2_writedata -> mem:writedata2
wire mm_interconnect_0_mem_s2_clken; // mm_interconnect_0:mem_s2_clken -> mem:clken2 wire mm_interconnect_0_mem_s2_clken; // mm_interconnect_0:mem_s2_clken -> mem:clken2
wire mm_interconnect_0_mem_s1_chipselect; // mm_interconnect_0:mem_s1_chipselect -> mem:chipselect wire mm_interconnect_0_mem_s1_chipselect; // mm_interconnect_0:mem_s1_chipselect -> mem:chipselect
wire [31:0] mm_interconnect_0_mem_s1_readdata; // mem:readdata -> mm_interconnect_0:mem_s1_readdata wire [31:0] mm_interconnect_0_mem_s1_readdata; // mem:readdata -> mm_interconnect_0:mem_s1_readdata
wire [14:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address wire [12:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address
wire [3:0] mm_interconnect_0_mem_s1_byteenable; // mm_interconnect_0:mem_s1_byteenable -> mem:byteenable wire [3:0] mm_interconnect_0_mem_s1_byteenable; // mm_interconnect_0:mem_s1_byteenable -> mem:byteenable
wire mm_interconnect_0_mem_s1_write; // mm_interconnect_0:mem_s1_write -> mem:write wire mm_interconnect_0_mem_s1_write; // mm_interconnect_0:mem_s1_write -> mem:write
wire [31:0] mm_interconnect_0_mem_s1_writedata; // mm_interconnect_0:mem_s1_writedata -> mem:writedata wire [31:0] mm_interconnect_0_mem_s1_writedata; // mm_interconnect_0:mem_s1_writedata -> mem:writedata

4
Top/niosII/synthesis/submodules/niosII_cpu.v
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@ -10,7 +10,7 @@ module niosII_cpu (
input wire clk, // clk.clk input wire clk, // clk.clk
input wire reset_n, // reset.reset_n input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req input wire reset_req, // .reset_req
output wire [17:0] d_address, // data_master.address output wire [15:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata input wire [31:0] d_readdata, // .readdata
@ -18,7 +18,7 @@ module niosII_cpu (
output wire d_write, // .write output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [17:0] i_address, // instruction_master.address output wire [15:0] i_address, // instruction_master.address
output wire i_read, // .read output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest input wire i_waitrequest, // .waitrequest

56
Top/niosII/synthesis/submodules/niosII_cpu_cpu.v
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@ -617,7 +617,7 @@ module niosII_cpu_cpu_nios2_oci_xbrk (
output xbrk_trigout; output xbrk_trigout;
input D_valid; input D_valid;
input E_valid; input E_valid;
input [ 15: 0] F_pc; input [ 13: 0] F_pc;
input clk; input clk;
input reset_n; input reset_n;
input trigger_state_0; input trigger_state_0;
@ -635,7 +635,7 @@ reg E_xbrk_goto1;
reg E_xbrk_traceoff; reg E_xbrk_traceoff;
reg E_xbrk_traceon; reg E_xbrk_traceon;
reg E_xbrk_trigout; reg E_xbrk_trigout;
wire [ 17: 0] cpu_i_address; wire [ 15: 0] cpu_i_address;
wire xbrk0_armed; wire xbrk0_armed;
wire xbrk0_break_hit; wire xbrk0_break_hit;
wire xbrk0_goto0_hit; wire xbrk0_goto0_hit;
@ -821,7 +821,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
) )
; ;
output [ 17: 0] cpu_d_address; output [ 15: 0] cpu_d_address;
output cpu_d_read; output cpu_d_read;
output [ 31: 0] cpu_d_readdata; output [ 31: 0] cpu_d_readdata;
output cpu_d_wait; output cpu_d_wait;
@ -837,7 +837,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
input [ 31: 0] E_st_data; input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered; input [ 31: 0] av_ld_data_aligned_filtered;
input clk; input clk;
input [ 17: 0] d_address; input [ 15: 0] d_address;
input d_read; input d_read;
input d_waitrequest; input d_waitrequest;
input d_write; input d_write;
@ -845,7 +845,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
input reset_n; input reset_n;
wire [ 17: 0] cpu_d_address; wire [ 15: 0] cpu_d_address;
wire cpu_d_read; wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata; wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait; wire cpu_d_wait;
@ -1201,7 +1201,7 @@ module niosII_cpu_cpu_nios2_oci_dtrace (
output [ 35: 0] atm; output [ 35: 0] atm;
output [ 35: 0] dtm; output [ 35: 0] dtm;
input clk; input clk;
input [ 17: 0] cpu_d_address; input [ 15: 0] cpu_d_address;
input cpu_d_read; input cpu_d_read;
input [ 31: 0] cpu_d_readdata; input [ 31: 0] cpu_d_readdata;
input cpu_d_wait; input cpu_d_wait;
@ -2339,7 +2339,7 @@ defparam niosII_cpu_cpu_ociram_sp_ram.lpm_file = "niosII_cpu_cpu_ociram_default_
`endif `endif
//synthesis translate_on //synthesis translate_on
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 : assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001212 : (MonAReg[4 : 2] == 3'd1)? 32'h00001010 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 : (MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 : (MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 : (MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
@ -2403,12 +2403,12 @@ module niosII_cpu_cpu_nios2_oci (
input D_valid; input D_valid;
input [ 31: 0] E_st_data; input [ 31: 0] E_st_data;
input E_valid; input E_valid;
input [ 15: 0] F_pc; input [ 13: 0] F_pc;
input [ 8: 0] address_nxt; input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered; input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt; input [ 3: 0] byteenable_nxt;
input clk; input clk;
input [ 17: 0] d_address; input [ 15: 0] d_address;
input d_read; input d_read;
input d_waitrequest; input d_waitrequest;
input d_write; input d_write;
@ -2427,7 +2427,7 @@ reg [ 8: 0] address;
wire [ 35: 0] atm; wire [ 35: 0] atm;
wire [ 31: 0] break_readreg; wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable; reg [ 3: 0] byteenable;
wire [ 17: 0] cpu_d_address; wire [ 15: 0] cpu_d_address;
wire cpu_d_read; wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata; wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait; wire cpu_d_wait;
@ -2864,7 +2864,7 @@ module niosII_cpu_cpu (
) )
; ;
output [ 17: 0] d_address; output [ 15: 0] d_address;
output [ 3: 0] d_byteenable; output [ 3: 0] d_byteenable;
output d_read; output d_read;
output d_write; output d_write;
@ -2874,7 +2874,7 @@ module niosII_cpu_cpu (
output debug_mem_slave_waitrequest; output debug_mem_slave_waitrequest;
output debug_reset_request; output debug_reset_request;
output dummy_ci_port; output dummy_ci_port;
output [ 17: 0] i_address; output [ 15: 0] i_address;
output i_read; output i_read;
input clk; input clk;
input [ 31: 0] d_readdata; input [ 31: 0] d_readdata;
@ -2959,7 +2959,7 @@ wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz; wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op; wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx; wire [ 5: 0] D_iw_opx;
wire [ 15: 0] D_jmp_direct_target_waddr; wire [ 13: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op; wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw; wire [ 1: 0] D_logic_op_raw;
wire D_mem16; wire D_mem16;
@ -3110,7 +3110,7 @@ wire E_ld_stall;
wire [ 31: 0] E_logic_result; wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0; wire E_logic_result_is_0;
wire E_lt; wire E_lt;
wire [ 17: 0] E_mem_baddr; wire [ 15: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en; wire [ 3: 0] E_mem_byte_en;
reg E_new_inst; reg E_new_inst;
wire E_rf_ecc_recoverable_valid; wire E_rf_ecc_recoverable_valid;
@ -3301,15 +3301,15 @@ wire F_op_wrprs;
wire F_op_xor; wire F_op_xor;
wire F_op_xorhi; wire F_op_xorhi;
wire F_op_xori; wire F_op_xori;
reg [ 15: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */; reg [ 13: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en; wire F_pc_en;
wire [ 15: 0] F_pc_no_crst_nxt; wire [ 13: 0] F_pc_no_crst_nxt;
wire [ 15: 0] F_pc_nxt; wire [ 13: 0] F_pc_nxt;
wire [ 15: 0] F_pc_plus_one; wire [ 13: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt; wire [ 1: 0] F_pc_sel_nxt;
wire [ 17: 0] F_pcb; wire [ 15: 0] F_pcb;
wire [ 17: 0] F_pcb_nxt; wire [ 15: 0] F_pcb_nxt;
wire [ 17: 0] F_pcb_plus_four; wire [ 15: 0] F_pcb_plus_four;
wire F_valid; wire F_valid;
wire [ 71: 0] F_vinst; wire [ 71: 0] F_vinst;
reg [ 1: 0] R_compare_op; reg [ 1: 0] R_compare_op;
@ -3443,7 +3443,7 @@ reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt; wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg; reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt; wire [ 31: 0] W_ipending_reg_nxt;
wire [ 17: 0] W_mem_baddr; wire [ 15: 0] W_mem_baddr;
reg W_rf_ecc_recoverable_valid; reg W_rf_ecc_recoverable_valid;
reg W_rf_ecc_unrecoverable_valid; reg W_rf_ecc_unrecoverable_valid;
wire W_rf_ecc_valid_any; wire W_rf_ecc_valid_any;
@ -3483,7 +3483,7 @@ wire av_ld_rshift8;
reg av_ld_waiting_for_data; reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt; wire av_ld_waiting_for_data_nxt;
wire av_sign_bit; wire av_sign_bit;
wire [ 17: 0] d_address; wire [ 15: 0] d_address;
reg [ 3: 0] d_byteenable; reg [ 3: 0] d_byteenable;
reg d_read; reg d_read;
wire d_read_nxt; wire d_read_nxt;
@ -3501,7 +3501,7 @@ reg hbreak_enabled;
reg hbreak_pending; reg hbreak_pending;
wire hbreak_pending_nxt; wire hbreak_pending_nxt;
wire hbreak_req; wire hbreak_req;
wire [ 17: 0] i_address; wire [ 15: 0] i_address;
reg i_read; reg i_read;
wire i_read_nxt; wire i_read_nxt;
wire [ 31: 0] iactive; wire [ 31: 0] iactive;
@ -3863,8 +3863,8 @@ reg wait_for_one_post_bret_inst;
2'b11; 2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 : assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 :
(F_pc_sel_nxt == 2'b01)? 33288 : (F_pc_sel_nxt == 2'b01)? 8712 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[17 : 2] : (F_pc_sel_nxt == 2'b10)? E_arith_result[15 : 2] :
F_pc_plus_one; F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt; assign F_pc_nxt = F_pc_no_crst_nxt;
@ -4166,7 +4166,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
E_arith_src1 - E_arith_src2 : E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2; E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[17 : 0]; assign E_mem_baddr = E_arith_result[15 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) : assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) : (R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) : (R_logic_op == 2'b10)? (E_src1 | E_src2) :
@ -4489,7 +4489,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
assign W_wr_data = W_wr_data_non_zero; assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result); assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result);
assign W_mem_baddr = W_alu_result[17 : 0]; assign W_mem_baddr = W_alu_result[15 : 0];
assign W_status_reg = W_status_reg_pie; assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst & assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd0); (D_iw_control_regnum == 5'd0);

6
Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v
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@ -59,7 +59,7 @@ module niosII_cpu_cpu_test_bench (
input [ 5: 0] D_iw_opx; input [ 5: 0] D_iw_opx;
input D_valid; input D_valid;
input E_valid; input E_valid;
input [ 17: 0] F_pcb; input [ 15: 0] F_pcb;
input F_valid; input F_valid;
input R_ctrl_ld; input R_ctrl_ld;
input R_ctrl_ld_non_io; input R_ctrl_ld_non_io;
@ -70,11 +70,11 @@ module niosII_cpu_cpu_test_bench (
input [ 31: 0] W_wr_data; input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered; input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk; input clk;
input [ 17: 0] d_address; input [ 15: 0] d_address;
input [ 3: 0] d_byteenable; input [ 3: 0] d_byteenable;
input d_read; input d_read;
input d_write; input d_write;
input [ 17: 0] i_address; input [ 15: 0] i_address;
input i_read; input i_read;
input [ 31: 0] i_readdata; input [ 31: 0] i_readdata;
input i_waitrequest; input i_waitrequest;

24576
Top/niosII/synthesis/submodules/niosII_mem.hex
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14
Top/niosII/synthesis/submodules/niosII_mem.v
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@ -48,8 +48,8 @@ module niosII_mem (
output [ 31: 0] readdata; output [ 31: 0] readdata;
output [ 31: 0] readdata2; output [ 31: 0] readdata2;
input [ 14: 0] address; input [ 12: 0] address;
input [ 14: 0] address2; input [ 12: 0] address2;
input [ 3: 0] byteenable; input [ 3: 0] byteenable;
input [ 3: 0] byteenable2; input [ 3: 0] byteenable2;
input chipselect; input chipselect;
@ -102,9 +102,9 @@ wire wren2;
the_altsyncram.indata_reg_b = "CLOCK0", the_altsyncram.indata_reg_b = "CLOCK0",
the_altsyncram.init_file = INIT_FILE, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32768, the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 32768, the_altsyncram.numwords_a = 8192,
the_altsyncram.numwords_b = 32768, the_altsyncram.numwords_b = 8192,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT", the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.outdata_reg_b = "UNREGISTERED",
@ -114,8 +114,8 @@ wire wren2;
the_altsyncram.width_b = 32, the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4, the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 15, the_altsyncram.widthad_a = 13,
the_altsyncram.widthad_b = 15, the_altsyncram.widthad_b = 13,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0"; the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0";
//s1, which is an e_avalon_slave //s1, which is an e_avalon_slave

596
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v
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14
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv
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@ -28,7 +28,7 @@
// ------------------------------------------ // ------------------------------------------
// Generation parameters: // Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_demux // output_name: niosII_mm_interconnect_0_cmd_demux
// ST_DATA_W: 94 // ST_DATA_W: 92
// ST_CHANNEL_W: 6 // ST_CHANNEL_W: 6
// NUM_OUTPUTS: 5 // NUM_OUTPUTS: 5
// VALID_WIDTH: 1 // VALID_WIDTH: 1
@ -46,7 +46,7 @@ module niosII_mm_interconnect_0_cmd_demux
// Sink // Sink
// ------------------- // -------------------
input [1-1 : 0] sink_valid, input [1-1 : 0] sink_valid,
input [94-1 : 0] sink_data, // ST_DATA_W=94 input [92-1 : 0] sink_data, // ST_DATA_W=92
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6 input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket, input sink_startofpacket,
input sink_endofpacket, input sink_endofpacket,
@ -56,35 +56,35 @@ module niosII_mm_interconnect_0_cmd_demux
// Sources // Sources
// ------------------- // -------------------
output reg src0_valid, output reg src0_valid,
output reg [94-1 : 0] src0_data, // ST_DATA_W=94 output reg [92-1 : 0] src0_data, // ST_DATA_W=92
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6 output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket, output reg src0_startofpacket,
output reg src0_endofpacket, output reg src0_endofpacket,
input src0_ready, input src0_ready,
output reg src1_valid, output reg src1_valid,
output reg [94-1 : 0] src1_data, // ST_DATA_W=94 output reg [92-1 : 0] src1_data, // ST_DATA_W=92
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6 output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket, output reg src1_startofpacket,
output reg src1_endofpacket, output reg src1_endofpacket,
input src1_ready, input src1_ready,
output reg src2_valid, output reg src2_valid,
output reg [94-1 : 0] src2_data, // ST_DATA_W=94 output reg [92-1 : 0] src2_data, // ST_DATA_W=92
output reg [6-1 : 0] src2_channel, // ST_CHANNEL_W=6 output reg [6-1 : 0] src2_channel, // ST_CHANNEL_W=6
output reg src2_startofpacket, output reg src2_startofpacket,
output reg src2_endofpacket, output reg src2_endofpacket,
input src2_ready, input src2_ready,
output reg src3_valid, output reg src3_valid,
output reg [94-1 : 0] src3_data, // ST_DATA_W=94 output reg [92-1 : 0] src3_data, // ST_DATA_W=92
output reg [6-1 : 0] src3_channel, // ST_CHANNEL_W=6 output reg [6-1 : 0] src3_channel, // ST_CHANNEL_W=6
output reg src3_startofpacket, output reg src3_startofpacket,
output reg src3_endofpacket, output reg src3_endofpacket,
input src3_ready, input src3_ready,
output reg src4_valid, output reg src4_valid,
output reg [94-1 : 0] src4_data, // ST_DATA_W=94 output reg [92-1 : 0] src4_data, // ST_DATA_W=92
output reg [6-1 : 0] src4_channel, // ST_CHANNEL_W=6 output reg [6-1 : 0] src4_channel, // ST_CHANNEL_W=6
output reg src4_startofpacket, output reg src4_startofpacket,
output reg src4_endofpacket, output reg src4_endofpacket,

8
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv
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@ -28,7 +28,7 @@
// ------------------------------------------ // ------------------------------------------
// Generation parameters: // Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_demux_001 // output_name: niosII_mm_interconnect_0_cmd_demux_001
// ST_DATA_W: 94 // ST_DATA_W: 92
// ST_CHANNEL_W: 6 // ST_CHANNEL_W: 6
// NUM_OUTPUTS: 2 // NUM_OUTPUTS: 2
// VALID_WIDTH: 1 // VALID_WIDTH: 1
@ -46,7 +46,7 @@ module niosII_mm_interconnect_0_cmd_demux_001
// Sink // Sink
// ------------------- // -------------------
input [1-1 : 0] sink_valid, input [1-1 : 0] sink_valid,
input [94-1 : 0] sink_data, // ST_DATA_W=94 input [92-1 : 0] sink_data, // ST_DATA_W=92
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6 input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket, input sink_startofpacket,
input sink_endofpacket, input sink_endofpacket,
@ -56,14 +56,14 @@ module niosII_mm_interconnect_0_cmd_demux_001
// Sources // Sources
// ------------------- // -------------------
output reg src0_valid, output reg src0_valid,
output reg [94-1 : 0] src0_data, // ST_DATA_W=94 output reg [92-1 : 0] src0_data, // ST_DATA_W=92
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6 output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket, output reg src0_startofpacket,
output reg src0_endofpacket, output reg src0_endofpacket,
input src0_ready, input src0_ready,
output reg src1_valid, output reg src1_valid,
output reg [94-1 : 0] src1_data, // ST_DATA_W=94 output reg [92-1 : 0] src1_data, // ST_DATA_W=92
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6 output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket, output reg src1_startofpacket,
output reg src1_endofpacket, output reg src1_endofpacket,

14
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv
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@ -43,8 +43,8 @@
// ARBITRATION_SHARES: 1 // ARBITRATION_SHARES: 1
// ARBITRATION_SCHEME "round-robin" // ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1 // PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 58 (arbitration locking enabled) // PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 94 // ST_DATA_W: 92
// ST_CHANNEL_W: 6 // ST_CHANNEL_W: 6
// ------------------------------------------ // ------------------------------------------
@ -54,7 +54,7 @@ module niosII_mm_interconnect_0_cmd_mux
// Sinks // Sinks
// ---------------------- // ----------------------
input sink0_valid, input sink0_valid,
input [94-1 : 0] sink0_data, input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel, input [6-1: 0] sink0_channel,
input sink0_startofpacket, input sink0_startofpacket,
input sink0_endofpacket, input sink0_endofpacket,
@ -65,7 +65,7 @@ module niosII_mm_interconnect_0_cmd_mux
// Source // Source
// ---------------------- // ----------------------
output src_valid, output src_valid,
output [94-1 : 0] src_data, output [92-1 : 0] src_data,
output [6-1 : 0] src_channel, output [6-1 : 0] src_channel,
output src_startofpacket, output src_startofpacket,
output src_endofpacket, output src_endofpacket,
@ -77,13 +77,13 @@ module niosII_mm_interconnect_0_cmd_mux
input clk, input clk,
input reset input reset
); );
localparam PAYLOAD_W = 94 + 6 + 2; localparam PAYLOAD_W = 92 + 6 + 2;
localparam NUM_INPUTS = 1; localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1; localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1; localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 94; localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6; localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 58; localparam PKT_TRANS_LOCK = 56;
assign src_valid = sink0_valid; assign src_valid = sink0_valid;
assign src_data = sink0_data; assign src_data = sink0_data;

20
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv
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@ -43,8 +43,8 @@
// ARBITRATION_SHARES: 1 1 // ARBITRATION_SHARES: 1 1
// ARBITRATION_SCHEME "round-robin" // ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1 // PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 58 (arbitration locking enabled) // PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 94 // ST_DATA_W: 92
// ST_CHANNEL_W: 6 // ST_CHANNEL_W: 6
// ------------------------------------------ // ------------------------------------------
@ -54,14 +54,14 @@ module niosII_mm_interconnect_0_cmd_mux_002
// Sinks // Sinks
// ---------------------- // ----------------------
input sink0_valid, input sink0_valid,
input [94-1 : 0] sink0_data, input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel, input [6-1: 0] sink0_channel,
input sink0_startofpacket, input sink0_startofpacket,
input sink0_endofpacket, input sink0_endofpacket,
output sink0_ready, output sink0_ready,
input sink1_valid, input sink1_valid,
input [94-1 : 0] sink1_data, input [92-1 : 0] sink1_data,
input [6-1: 0] sink1_channel, input [6-1: 0] sink1_channel,
input sink1_startofpacket, input sink1_startofpacket,
input sink1_endofpacket, input sink1_endofpacket,
@ -72,7 +72,7 @@ module niosII_mm_interconnect_0_cmd_mux_002
// Source // Source
// ---------------------- // ----------------------
output src_valid, output src_valid,
output [94-1 : 0] src_data, output [92-1 : 0] src_data,
output [6-1 : 0] src_channel, output [6-1 : 0] src_channel,
output src_startofpacket, output src_startofpacket,
output src_endofpacket, output src_endofpacket,
@ -84,13 +84,13 @@ module niosII_mm_interconnect_0_cmd_mux_002
input clk, input clk,
input reset input reset
); );
localparam PAYLOAD_W = 94 + 6 + 2; localparam PAYLOAD_W = 92 + 6 + 2;
localparam NUM_INPUTS = 2; localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1; localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1; localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 94; localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6; localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 58; localparam PKT_TRANS_LOCK = 56;
// ------------------------------------------ // ------------------------------------------
// Signals // Signals
@ -122,8 +122,8 @@ module niosII_mm_interconnect_0_cmd_mux_002
// ------------------------------------------ // ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock; reg [NUM_INPUTS - 1 : 0] lock;
always @* begin always @* begin
lock[0] = sink0_data[58]; lock[0] = sink0_data[56];
lock[1] = sink1_data[58]; lock[1] = sink1_data[56];
end end
reg [NUM_INPUTS - 1 : 0] locked = '0; reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin always @(posedge clk or posedge reset) begin

56
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv
View File

@ -49,14 +49,14 @@ module niosII_mm_interconnect_0_router_default_decode
DEFAULT_RD_CHANNEL = -1, DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 3 DEFAULT_DESTID = 3
) )
(output [80 - 78 : 0] default_destination_id, (output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel, output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel, output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel output [6-1 : 0] default_src_channel
); );
assign default_destination_id = assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0]; DEFAULT_DESTID[78 - 76 : 0];
generate generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router
// Command Sink (Input) // Command Sink (Input)
// ------------------- // -------------------
input sink_valid, input sink_valid,
input [94-1 : 0] sink_data, input [92-1 : 0] sink_data,
input sink_startofpacket, input sink_startofpacket,
input sink_endofpacket, input sink_endofpacket,
output sink_ready, output sink_ready,
@ -102,7 +102,7 @@ module niosII_mm_interconnect_0_router
// Command Source (Output) // Command Source (Output)
// ------------------- // -------------------
output src_valid, output src_valid,
output reg [94-1 : 0] src_data, output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel, output reg [6-1 : 0] src_channel,
output src_startofpacket, output src_startofpacket,
output src_endofpacket, output src_endofpacket,
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router
// ------------------------------------------------------- // -------------------------------------------------------
// Local parameters and variables // Local parameters and variables
// ------------------------------------------------------- // -------------------------------------------------------
localparam PKT_ADDR_H = 53; localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_L = 36; localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80; localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 78; localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 84; localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 82; localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 94; localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6; localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0; localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 56; localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 57; localparam PKT_TRANS_READ = 55;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@ -134,17 +134,17 @@ module niosII_mm_interconnect_0_router
// Figure out the number of bits to mask off for each slave span // Figure out the number of bits to mask off for each slave span
// during address decoding // during address decoding
// ------------------------------------------------------- // -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20000 - 64'h0); localparam PAD0 = log2ceil(64'h8000 - 64'h0);
localparam PAD1 = log2ceil(64'h21000 - 64'h20800); localparam PAD1 = log2ceil(64'h9000 - 64'h8800);
localparam PAD2 = log2ceil(64'h21020 - 64'h21000); localparam PAD2 = log2ceil(64'h9020 - 64'h9000);
localparam PAD3 = log2ceil(64'h21028 - 64'h21020); localparam PAD3 = log2ceil(64'h9028 - 64'h9020);
localparam PAD4 = log2ceil(64'h2102c - 64'h21028); localparam PAD4 = log2ceil(64'h902c - 64'h9028);
// ------------------------------------------------------- // -------------------------------------------------------
// Work out which address bits are significant based on the // Work out which address bits are significant based on the
// address range of the slaves. If the required width is too // address range of the slaves. If the required width is too
// large or too small, we use the address field width instead. // large or too small, we use the address field width instead.
// ------------------------------------------------------- // -------------------------------------------------------
localparam ADDR_RANGE = 64'h2102c; localparam ADDR_RANGE = 64'h902c;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ? (RANGE_ADDR_WIDTH == 0) ?
@ -197,32 +197,32 @@ module niosII_mm_interconnect_0_router
// Sets the channel and destination ID based on the address // Sets the channel and destination ID based on the address
// -------------------------------------------------- // --------------------------------------------------
// ( 0x0 .. 0x20000 ) // ( 0x0 .. 0x8000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin if ( {address[RG:PAD0],{PAD0{1'b0}}} == 16'h0 ) begin
src_channel = 6'b10000; src_channel = 6'b10000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end end
// ( 0x20800 .. 0x21000 ) // ( 0x8800 .. 0x9000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin if ( {address[RG:PAD1],{PAD1{1'b0}}} == 16'h8800 ) begin
src_channel = 6'b00100; src_channel = 6'b00100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end end
// ( 0x21000 .. 0x21020 ) // ( 0x9000 .. 0x9020 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 ) begin if ( {address[RG:PAD2],{PAD2{1'b0}}} == 16'h9000 ) begin
src_channel = 6'b01000; src_channel = 6'b01000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end end
// ( 0x21020 .. 0x21028 ) // ( 0x9020 .. 0x9028 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21020 ) begin if ( {address[RG:PAD3],{PAD3{1'b0}}} == 16'h9020 ) begin
src_channel = 6'b00001; src_channel = 6'b00001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end end
// ( 0x21028 .. 0x2102c ) // ( 0x9028 .. 0x902c )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21028 && write_transaction ) begin if ( {address[RG:PAD4],{PAD4{1'b0}}} == 16'h9028 && write_transaction ) begin
src_channel = 6'b00010; src_channel = 6'b00010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end end

38
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv
View File

@ -49,14 +49,14 @@ module niosII_mm_interconnect_0_router_001_default_decode
DEFAULT_RD_CHANNEL = -1, DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 2 DEFAULT_DESTID = 2
) )
(output [80 - 78 : 0] default_destination_id, (output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel, output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel, output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel output [6-1 : 0] default_src_channel
); );
assign default_destination_id = assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0]; DEFAULT_DESTID[78 - 76 : 0];
generate generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_001
// Command Sink (Input) // Command Sink (Input)
// ------------------- // -------------------
input sink_valid, input sink_valid,
input [94-1 : 0] sink_data, input [92-1 : 0] sink_data,
input sink_startofpacket, input sink_startofpacket,
input sink_endofpacket, input sink_endofpacket,
output sink_ready, output sink_ready,
@ -102,7 +102,7 @@ module niosII_mm_interconnect_0_router_001
// Command Source (Output) // Command Source (Output)
// ------------------- // -------------------
output src_valid, output src_valid,
output reg [94-1 : 0] src_data, output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel, output reg [6-1 : 0] src_channel,
output src_startofpacket, output src_startofpacket,
output src_endofpacket, output src_endofpacket,
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_001
// ------------------------------------------------------- // -------------------------------------------------------
// Local parameters and variables // Local parameters and variables
// ------------------------------------------------------- // -------------------------------------------------------
localparam PKT_ADDR_H = 53; localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_L = 36; localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80; localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 78; localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 84; localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 82; localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 94; localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6; localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0; localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 56; localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 57; localparam PKT_TRANS_READ = 55;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@ -134,14 +134,14 @@ module niosII_mm_interconnect_0_router_001
// Figure out the number of bits to mask off for each slave span // Figure out the number of bits to mask off for each slave span
// during address decoding // during address decoding
// ------------------------------------------------------- // -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20000 - 64'h0); localparam PAD0 = log2ceil(64'h8000 - 64'h0);
localparam PAD1 = log2ceil(64'h21000 - 64'h20800); localparam PAD1 = log2ceil(64'h9000 - 64'h8800);
// ------------------------------------------------------- // -------------------------------------------------------
// Work out which address bits are significant based on the // Work out which address bits are significant based on the
// address range of the slaves. If the required width is too // address range of the slaves. If the required width is too
// large or too small, we use the address field width instead. // large or too small, we use the address field width instead.
// ------------------------------------------------------- // -------------------------------------------------------
localparam ADDR_RANGE = 64'h21000; localparam ADDR_RANGE = 64'h9000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE); localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) || localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ? (RANGE_ADDR_WIDTH == 0) ?
@ -189,14 +189,14 @@ module niosII_mm_interconnect_0_router_001
// Sets the channel and destination ID based on the address // Sets the channel and destination ID based on the address
// -------------------------------------------------- // --------------------------------------------------
// ( 0x0 .. 0x20000 ) // ( 0x0 .. 0x8000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin if ( {address[RG:PAD0],{PAD0{1'b0}}} == 16'h0 ) begin
src_channel = 6'b10; src_channel = 6'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end end
// ( 0x20800 .. 0x21000 ) // ( 0x8800 .. 0x9000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin if ( {address[RG:PAD1],{PAD1{1'b0}}} == 16'h8800 ) begin
src_channel = 6'b01; src_channel = 6'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0; src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end end

24
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv
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@ -49,14 +49,14 @@ module niosII_mm_interconnect_0_router_002_default_decode
DEFAULT_RD_CHANNEL = -1, DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0 DEFAULT_DESTID = 0
) )
(output [80 - 78 : 0] default_destination_id, (output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel, output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel, output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel output [6-1 : 0] default_src_channel
); );
assign default_destination_id = assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0]; DEFAULT_DESTID[78 - 76 : 0];
generate generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_002
// Command Sink (Input) // Command Sink (Input)
// ------------------- // -------------------
input sink_valid, input sink_valid,
input [94-1 : 0] sink_data, input [92-1 : 0] sink_data,
input sink_startofpacket, input sink_startofpacket,
input sink_endofpacket, input sink_endofpacket,
output sink_ready, output sink_ready,
@ -102,7 +102,7 @@ module niosII_mm_interconnect_0_router_002
// Command Source (Output) // Command Source (Output)
// ------------------- // -------------------
output src_valid, output src_valid,
output reg [94-1 : 0] src_data, output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel, output reg [6-1 : 0] src_channel,
output src_startofpacket, output src_startofpacket,
output src_endofpacket, output src_endofpacket,
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_002
// ------------------------------------------------------- // -------------------------------------------------------
// Local parameters and variables // Local parameters and variables
// ------------------------------------------------------- // -------------------------------------------------------
localparam PKT_ADDR_H = 53; localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_L = 36; localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80; localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 78; localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 84; localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 82; localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 94; localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6; localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 1; localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 56; localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 57; localparam PKT_TRANS_READ = 55;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;

24
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv
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@ -49,14 +49,14 @@ module niosII_mm_interconnect_0_router_004_default_decode
DEFAULT_RD_CHANNEL = -1, DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0 DEFAULT_DESTID = 0
) )
(output [80 - 78 : 0] default_destination_id, (output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel, output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel, output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel output [6-1 : 0] default_src_channel
); );
assign default_destination_id = assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0]; DEFAULT_DESTID[78 - 76 : 0];
generate generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_004
// Command Sink (Input) // Command Sink (Input)
// ------------------- // -------------------
input sink_valid, input sink_valid,
input [94-1 : 0] sink_data, input [92-1 : 0] sink_data,
input sink_startofpacket, input sink_startofpacket,
input sink_endofpacket, input sink_endofpacket,
output sink_ready, output sink_ready,
@ -102,7 +102,7 @@ module niosII_mm_interconnect_0_router_004
// Command Source (Output) // Command Source (Output)
// ------------------- // -------------------
output src_valid, output src_valid,
output reg [94-1 : 0] src_data, output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel, output reg [6-1 : 0] src_channel,
output src_startofpacket, output src_startofpacket,
output src_endofpacket, output src_endofpacket,
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_004
// ------------------------------------------------------- // -------------------------------------------------------
// Local parameters and variables // Local parameters and variables
// ------------------------------------------------------- // -------------------------------------------------------
localparam PKT_ADDR_H = 53; localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_L = 36; localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80; localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 78; localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 84; localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 82; localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 94; localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6; localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 1; localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 56; localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 57; localparam PKT_TRANS_READ = 55;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1; localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1; localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;

6
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv
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@ -28,7 +28,7 @@
// ------------------------------------------ // ------------------------------------------
// Generation parameters: // Generation parameters:
// output_name: niosII_mm_interconnect_0_rsp_demux // output_name: niosII_mm_interconnect_0_rsp_demux
// ST_DATA_W: 94 // ST_DATA_W: 92
// ST_CHANNEL_W: 6 // ST_CHANNEL_W: 6
// NUM_OUTPUTS: 1 // NUM_OUTPUTS: 1
// VALID_WIDTH: 1 // VALID_WIDTH: 1
@ -46,7 +46,7 @@ module niosII_mm_interconnect_0_rsp_demux
// Sink // Sink
// ------------------- // -------------------
input [1-1 : 0] sink_valid, input [1-1 : 0] sink_valid,
input [94-1 : 0] sink_data, // ST_DATA_W=94 input [92-1 : 0] sink_data, // ST_DATA_W=92
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6 input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket, input sink_startofpacket,
input sink_endofpacket, input sink_endofpacket,
@ -56,7 +56,7 @@ module niosII_mm_interconnect_0_rsp_demux
// Sources // Sources
// ------------------- // -------------------
output reg src0_valid, output reg src0_valid,
output reg [94-1 : 0] src0_data, // ST_DATA_W=94 output reg [92-1 : 0] src0_data, // ST_DATA_W=92
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6 output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket, output reg src0_startofpacket,
output reg src0_endofpacket, output reg src0_endofpacket,

32
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv
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@ -43,8 +43,8 @@
// ARBITRATION_SHARES: 1 1 1 1 1 // ARBITRATION_SHARES: 1 1 1 1 1
// ARBITRATION_SCHEME "no-arb" // ARBITRATION_SCHEME "no-arb"
// PIPELINE_ARB: 0 // PIPELINE_ARB: 0
// PKT_TRANS_LOCK: 58 (arbitration locking enabled) // PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 94 // ST_DATA_W: 92
// ST_CHANNEL_W: 6 // ST_CHANNEL_W: 6
// ------------------------------------------ // ------------------------------------------
@ -54,35 +54,35 @@ module niosII_mm_interconnect_0_rsp_mux
// Sinks // Sinks
// ---------------------- // ----------------------
input sink0_valid, input sink0_valid,
input [94-1 : 0] sink0_data, input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel, input [6-1: 0] sink0_channel,
input sink0_startofpacket, input sink0_startofpacket,
input sink0_endofpacket, input sink0_endofpacket,
output sink0_ready, output sink0_ready,
input sink1_valid, input sink1_valid,
input [94-1 : 0] sink1_data, input [92-1 : 0] sink1_data,
input [6-1: 0] sink1_channel, input [6-1: 0] sink1_channel,
input sink1_startofpacket, input sink1_startofpacket,
input sink1_endofpacket, input sink1_endofpacket,
output sink1_ready, output sink1_ready,
input sink2_valid, input sink2_valid,
input [94-1 : 0] sink2_data, input [92-1 : 0] sink2_data,
input [6-1: 0] sink2_channel, input [6-1: 0] sink2_channel,
input sink2_startofpacket, input sink2_startofpacket,
input sink2_endofpacket, input sink2_endofpacket,
output sink2_ready, output sink2_ready,
input sink3_valid, input sink3_valid,
input [94-1 : 0] sink3_data, input [92-1 : 0] sink3_data,
input [6-1: 0] sink3_channel, input [6-1: 0] sink3_channel,
input sink3_startofpacket, input sink3_startofpacket,
input sink3_endofpacket, input sink3_endofpacket,
output sink3_ready, output sink3_ready,
input sink4_valid, input sink4_valid,
input [94-1 : 0] sink4_data, input [92-1 : 0] sink4_data,
input [6-1: 0] sink4_channel, input [6-1: 0] sink4_channel,
input sink4_startofpacket, input sink4_startofpacket,
input sink4_endofpacket, input sink4_endofpacket,
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_rsp_mux
// Source // Source
// ---------------------- // ----------------------
output src_valid, output src_valid,
output [94-1 : 0] src_data, output [92-1 : 0] src_data,
output [6-1 : 0] src_channel, output [6-1 : 0] src_channel,
output src_startofpacket, output src_startofpacket,
output src_endofpacket, output src_endofpacket,
@ -105,13 +105,13 @@ module niosII_mm_interconnect_0_rsp_mux
input clk, input clk,
input reset input reset
); );
localparam PAYLOAD_W = 94 + 6 + 2; localparam PAYLOAD_W = 92 + 6 + 2;
localparam NUM_INPUTS = 5; localparam NUM_INPUTS = 5;
localparam SHARE_COUNTER_W = 1; localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0; localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 94; localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6; localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 58; localparam PKT_TRANS_LOCK = 56;
// ------------------------------------------ // ------------------------------------------
// Signals // Signals
@ -146,11 +146,11 @@ module niosII_mm_interconnect_0_rsp_mux
// ------------------------------------------ // ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock; reg [NUM_INPUTS - 1 : 0] lock;
always @* begin always @* begin
lock[0] = sink0_data[58]; lock[0] = sink0_data[56];
lock[1] = sink1_data[58]; lock[1] = sink1_data[56];
lock[2] = sink2_data[58]; lock[2] = sink2_data[56];
lock[3] = sink3_data[58]; lock[3] = sink3_data[56];
lock[4] = sink4_data[58]; lock[4] = sink4_data[56];
end end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));

20
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv
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@ -43,8 +43,8 @@
// ARBITRATION_SHARES: 1 1 // ARBITRATION_SHARES: 1 1
// ARBITRATION_SCHEME "no-arb" // ARBITRATION_SCHEME "no-arb"
// PIPELINE_ARB: 0 // PIPELINE_ARB: 0
// PKT_TRANS_LOCK: 58 (arbitration locking enabled) // PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 94 // ST_DATA_W: 92
// ST_CHANNEL_W: 6 // ST_CHANNEL_W: 6
// ------------------------------------------ // ------------------------------------------
@ -54,14 +54,14 @@ module niosII_mm_interconnect_0_rsp_mux_001
// Sinks // Sinks
// ---------------------- // ----------------------
input sink0_valid, input sink0_valid,
input [94-1 : 0] sink0_data, input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel, input [6-1: 0] sink0_channel,
input sink0_startofpacket, input sink0_startofpacket,
input sink0_endofpacket, input sink0_endofpacket,
output sink0_ready, output sink0_ready,
input sink1_valid, input sink1_valid,
input [94-1 : 0] sink1_data, input [92-1 : 0] sink1_data,
input [6-1: 0] sink1_channel, input [6-1: 0] sink1_channel,
input sink1_startofpacket, input sink1_startofpacket,
input sink1_endofpacket, input sink1_endofpacket,
@ -72,7 +72,7 @@ module niosII_mm_interconnect_0_rsp_mux_001
// Source // Source
// ---------------------- // ----------------------
output src_valid, output src_valid,
output [94-1 : 0] src_data, output [92-1 : 0] src_data,
output [6-1 : 0] src_channel, output [6-1 : 0] src_channel,
output src_startofpacket, output src_startofpacket,
output src_endofpacket, output src_endofpacket,
@ -84,13 +84,13 @@ module niosII_mm_interconnect_0_rsp_mux_001
input clk, input clk,
input reset input reset
); );
localparam PAYLOAD_W = 94 + 6 + 2; localparam PAYLOAD_W = 92 + 6 + 2;
localparam NUM_INPUTS = 2; localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1; localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0; localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 94; localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6; localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 58; localparam PKT_TRANS_LOCK = 56;
// ------------------------------------------ // ------------------------------------------
// Signals // Signals
@ -119,8 +119,8 @@ module niosII_mm_interconnect_0_rsp_mux_001
// ------------------------------------------ // ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock; reg [NUM_INPUTS - 1 : 0] lock;
always @* begin always @* begin
lock[0] = sink0_data[58]; lock[0] = sink0_data[56];
lock[1] = sink1_data[58]; lock[1] = sink1_data[56];
end end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant)); assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));

11
Top/semafor.qsf
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@ -37,7 +37,7 @@
set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7 set_global_assignment -name DEVICE EP4CE15F23C8
set_global_assignment -name TOP_LEVEL_ENTITY top set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:55 OCTOBER 18, 2022" set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:55 OCTOBER 18, 2022"
@ -46,17 +46,11 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)" set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_location_assignment PIN_Y2 -to clk
set_location_assignment PIN_M23 -to train
set_location_assignment PIN_G19 -to yellow
set_location_assignment PIN_F19 -to red
set_location_assignment PIN_G21 -to green
set_global_assignment -name SYSTEMVERILOG_FILE top.sv set_global_assignment -name SYSTEMVERILOG_FILE top.sv
set_global_assignment -name QIP_FILE niosII/synthesis/niosII.qip set_global_assignment -name QIP_FILE niosII/synthesis/niosII.qip
@ -64,4 +58,7 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_location_assignment PIN_T2 -to CLOCK_50
set_location_assignment PIN_E3 -to LEDG[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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@ -0,0 +1,90 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505">
<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505" moduleId="org.eclipse.cdt.core.settings"/>
</buildSystem>
<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505">
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505." name="/" resourcePath="">
<toolChain id="altera.nios2.linux.gcc4.369748947" name="Linux Nios II GCC4" superClass="altera.nios2.linux.gcc4">
<targetPlatform id="altera.nios2.linux.gcc4.1270664660" name="Nios II" osList="linux" superClass="altera.nios2.linux.gcc4"/>
<builder buildPath="${workspace_loc://deltasigma}" id="altera.tool.gnu.builder.1746673051" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder"/>
<tool id="altera.tool.gnu.c.compiler.754191929" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler">
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.872290592" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.cpp.compiler.1100567708" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler">
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1394337200" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.archiver.1341986491" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver"/>
<tool id="altera.tool.gnu.c.linker.1132604299" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker"/>
<tool id="altera.tool.gnu.cpp.linker.395670393" name="Nios II GCC C++ Linker" superClass="altera.tool.gnu.cpp.linker">
<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.179960318" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="altera.tool.gnu.assembler.453471012" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler">
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.616300943" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
</tool>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="deltasigma.null.2123671809" name="deltasigma"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505.;altera.tool.gnu.cpp.compiler.1100567708;cdt.managedbuild.tool.gnu.cpp.compiler.input.1394337200">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505.;altera.tool.gnu.c.compiler.754191929;cdt.managedbuild.tool.gnu.c.compiler.input.872290592">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
<buildTargets>
<target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>mem_init_install</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
<target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>mem_init_generate</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
<target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>help</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
</buildTargets>
</storageModule>
</cproject>

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@ -0,0 +1,40 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>deltasigma</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>com.altera.sbtgui.project.SBTGUINature</nature>
<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
</natures>
</projectDescription>

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@ -0,0 +1,22 @@
/*
* main.c
*
*
* Created on: Feb 7, 2023
* Author: ovchinnikov_ii@RISDE.ru
*/
#include <stdio.h>
#include "alt_types.h"
#include "system.h"
#include "io.h"
#define IOWR_DELSIG_CTL(base, data) IOWR(base, 0, data)
int main() {
IOWR_DELSIG_CTL(SIGDEL_0_BASE, 0x250000);
printf("Ready\n");
while (1) {}
return 0;
}

0
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62
Top/software/semafor_bsp/Makefile
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@ -19,27 +19,27 @@ SPACE := $(empty) $(empty)
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
# The adjust-path macro # The adjust-path macro
#
# If COMSPEC is defined, Make is launched from Windows through
# Cygwin. This adjust-path macro will call 'cygpath -u' on all
# paths to ensure they are readable by Make.
# #
# If Make is launched from Windows through # If COMSPEC is not defined, Make is launched from *nix, and no adjustment
# Windows Subsystem for Linux (WSL). The adjust-path macro converts absolute windows # is necessary
# paths into unix style paths (Example: c:/dir -> /c/dir).
# The adjust_path_mixed function converts WSL path to Windows path.
# This will ensure paths are readable by GNU Make.
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
UNAME = $(shell uname -r) ifndef COMSPEC
ifeq ($(findstring Microsoft,$(UNAME)),Microsoft) ifdef ComSpec
WINDOWS_EXE = .exe COMSPEC = $(ComSpec)
endif endif # ComSpec
endif # !COMSPEC
eq = $(and $(findstring $(1),$(2)),$(findstring $(2),$(1))) ifdef COMSPEC
adjust-path = $(subst $(SPACE),\$(SPACE),$(shell cygpath -u "$1"))
ifdef WINDOWS_EXE adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$(shell cygpath -m "$1"))
adjust-path = $(if $1,$(shell wslpath "$1"),) else
adjust-path-mixed = $(if $(call eq,$(shell echo $1 | head -c 5),/mnt/),$(shell echo $1 | sed 's/\/mnt\///g;s/\//:\//1'),$1) adjust-path = $(subst $(SPACE),\$(SPACE),$1)
else # !WINDOWS_EXE adjust-path-mixed = $(subst $(SPACE),\$(SPACE),$1)
adjust-path = $1
adjust-path-mixed = $1
endif endif
#------------------------------------------------------------------------------ #------------------------------------------------------------------------------
@ -62,7 +62,7 @@ all:
BSP_ROOT_DIR := . BSP_ROOT_DIR := .
# Define absolute path to the root of the BSP. # Define absolute path to the root of the BSP.
ABS_BSP_ROOT := $(shell pwd) ABS_BSP_ROOT := $(call adjust-path-mixed,$(shell pwd))
# Stash all BSP object files here # Stash all BSP object files here
OBJ_DIR := ./obj OBJ_DIR := ./obj
@ -93,12 +93,12 @@ OBJ_DIR := ./obj
# This following VERSION comment indicates the version of the tool used to # This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well. # generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 20.1 # ACDS_VERSION: 18.1
ACDS_VERSION := 20.1 ACDS_VERSION := 18.1
# This following BUILD_NUMBER comment indicates the build number of the tool # This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile. # used to generate this makefile.
# BUILD_NUMBER: 720 # BUILD_NUMBER: 625
SETTINGS_FILE := settings.bsp SETTINGS_FILE := settings.bsp
SOPC_FILE := ../../niosII.sopcinfo SOPC_FILE := ../../niosII.sopcinfo
@ -112,10 +112,10 @@ SOPC_FILE := ../../niosII.sopcinfo
#------------------------------------------------------------------------------- #-------------------------------------------------------------------------------
# Archiver command. Creates library files. # Archiver command. Creates library files.
AR = nios2-elf-ar$(WINDOWS_EXE) AR = nios2-elf-ar
# Assembler command. Note that CC is used for .S files. # Assembler command. Note that CC is used for .S files.
AS = nios2-elf-gcc$(WINDOWS_EXE) AS = nios2-elf-gcc
# Custom flags only passed to the archiver. This content of this variable is # Custom flags only passed to the archiver. This content of this variable is
# directly passed to the archiver rather than the more standard "ARFLAGS". The # directly passed to the archiver rather than the more standard "ARFLAGS". The
@ -145,10 +145,10 @@ BSP_CFLAGS_OPTIMIZATION = -O0
BSP_CFLAGS_WARNINGS = -Wall BSP_CFLAGS_WARNINGS = -Wall
# C compiler command. # C compiler command.
CC = nios2-elf-gcc$(WINDOWS_EXE) -xc CC = nios2-elf-gcc -xc
# C++ compiler command. # C++ compiler command.
CXX = nios2-elf-gcc$(WINDOWS_EXE) -xc++ CXX = nios2-elf-gcc -xc++
# Command used to remove files during 'clean' target. # Command used to remove files during 'clean' target.
RM = rm -f RM = rm -f
@ -516,13 +516,13 @@ build_post_process :
# Skip this check when clean is the only target # Skip this check when clean is the only target
ifneq ($(MAKECMDGOALS),clean) ifneq ($(MAKECMDGOALS),clean)
ifneq ($(wildcard $(call adjust-path,$(SETTINGS_FILE))),$(call adjust-path,$(SETTINGS_FILE))) ifneq ($(wildcard $(SETTINGS_FILE)),$(SETTINGS_FILE))
$(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.) $(warning Warning: BSP Settings File $(SETTINGS_FILE) could not be found.)
endif endif
Makefile: $(wildcard $(call adjust-path,$(SETTINGS_FILE))) Makefile: $(wildcard $(SETTINGS_FILE))
@$(ECHO) Makefile not up to date. @$(ECHO) Makefile not up to date.
@$(ECHO) $(call adjust-path,$(SETTINGS_FILE)) has been modified since the BSP Makefile was generated. @$(ECHO) $(SETTINGS_FILE) has been modified since the BSP Makefile was generated.
@$(ECHO) @$(ECHO)
@$(ECHO) Generate the BSP to update the Makefile, and then build again. @$(ECHO) Generate the BSP to update the Makefile, and then build again.
@$(ECHO) @$(ECHO)
@ -535,13 +535,13 @@ Makefile: $(wildcard $(call adjust-path,$(SETTINGS_FILE)))
@$(ECHO) @$(ECHO)
@exit 1 @exit 1
ifneq ($(wildcard $(call adjust-path,$(SOPC_FILE))),$(call adjust-path,$(SOPC_FILE))) ifneq ($(wildcard $(SOPC_FILE)),$(SOPC_FILE))
$(warning Warning: SOPC File $(SOPC_FILE) could not be found.) $(warning Warning: SOPC File $(SOPC_FILE) could not be found.)
endif endif
public.mk: $(wildcard $(call adjust-path,$(SOPC_FILE))) public.mk: $(wildcard $(SOPC_FILE))
@$(ECHO) Makefile not up to date. @$(ECHO) Makefile not up to date.
@$(ECHO) $(call adjust-path,$(SOPC_FILE)) has been modified since the BSP was generated. @$(ECHO) $(SOPC_FILE) has been modified since the BSP was generated.
@$(ECHO) @$(ECHO)
@$(ECHO) Generate the BSP to update the Makefile, and then build again. @$(ECHO) Generate the BSP to update the Makefile, and then build again.
@$(ECHO) @$(ECHO)

BIN
Top/software/semafor_bsp/libhal_bsp.a
View File

Binary file not shown.

4
Top/software/semafor_bsp/linker.h
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII' * Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo * SOPC Builder design path: ../../niosII.sopcinfo
* *
* Generated: Wed Oct 19 16:14:31 MSK 2022 * Generated: Tue Feb 07 13:28:19 MSK 2023
*/ */
/* /*
@ -66,7 +66,7 @@
*/ */
#define MEM_REGION_BASE 0x20 #define MEM_REGION_BASE 0x20
#define MEM_REGION_SPAN 131040 #define MEM_REGION_SPAN 32736
#define RESET_REGION_BASE 0x0 #define RESET_REGION_BASE 0x0
#define RESET_REGION_SPAN 32 #define RESET_REGION_SPAN 32

8
Top/software/semafor_bsp/linker.x
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII' * Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo * SOPC Builder design path: ../../niosII.sopcinfo
* *
* Generated: Wed Oct 19 16:14:31 MSK 2022 * Generated: Tue Feb 07 13:28:19 MSK 2023
*/ */
/* /*
@ -51,7 +51,7 @@
MEMORY MEMORY
{ {
reset : ORIGIN = 0x0, LENGTH = 32 reset : ORIGIN = 0x0, LENGTH = 32
mem : ORIGIN = 0x20, LENGTH = 131040 mem : ORIGIN = 0x20, LENGTH = 32736
} }
/* Define symbols for each memory base-address */ /* Define symbols for each memory base-address */
@ -334,7 +334,7 @@ SECTIONS
/* /*
* Don't override this, override the __alt_stack_* symbols instead. * Don't override this, override the __alt_stack_* symbols instead.
*/ */
__alt_data_end = 0x20000; __alt_data_end = 0x8000;
/* /*
* The next two symbols define the location of the default stack. You can * The next two symbols define the location of the default stack. You can
@ -350,4 +350,4 @@ PROVIDE( __alt_stack_limit = __alt_stack_base );
* Override this symbol to put the heap in a different memory. * Override this symbol to put the heap in a different memory.
*/ */
PROVIDE( __alt_heap_start = end ); PROVIDE( __alt_heap_start = end );
PROVIDE( __alt_heap_limit = 0x20000 ); PROVIDE( __alt_heap_limit = 0x8000 );

76
Top/software/semafor_bsp/mem_init.mk
View File

@ -22,32 +22,6 @@
# #
######################################################################### #########################################################################
#------------------------------------------------------------------------------
# The adjust-path macro
#
# If Make is launched from Windows through
# Windows Subsystem for Linux (WSL). The adjust-path macro converts absolute windows
# paths into unix style paths (Example: c:/dir -> /c/dir).
# The adjust_path_mixed function converts WSL path to Windows path.
# This will ensure paths are readable by GNU Make.
#------------------------------------------------------------------------------
UNAME = $(shell uname -r)
ifeq ($(findstring Microsoft,$(UNAME)),Microsoft)
WINDOWS_EXE = .exe
endif
eq = $(and $(findstring $(1),$(2)),$(findstring $(2),$(1)))
ifdef WINDOWS_EXE
adjust-path = $(if $1,$(shell wslpath "$1"),)
adjust-path-mixed = $(if $(call eq,$(shell echo $1 | head -c 5),/mnt/),$(shell echo $1 | sed 's/\/mnt\///g;s/\//:\//1'),$1)
else # !WINDOWS_EXE
adjust-path = $1
adjust-path-mixed = $1
endif
ifeq ($(MEM_INIT_FILE),) ifeq ($(MEM_INIT_FILE),)
# MEM_INIT_FILE should be set equal to the working relative path to this # MEM_INIT_FILE should be set equal to the working relative path to this
# mem_init.mk makefile fragment # mem_init.mk makefile fragment
@ -59,11 +33,11 @@ ELF2DAT := elf2dat
endif endif
ifeq ($(ELF2HEX),) ifeq ($(ELF2HEX),)
ELF2HEX := elf2hex$(WINDOWS_EXE) ELF2HEX := elf2hex
endif endif
ifeq ($(ELF2FLASH),) ifeq ($(ELF2FLASH),)
ELF2FLASH := elf2flash$(WINDOWS_EXE) ELF2FLASH := elf2flash
endif endif
ifeq ($(FLASH2DAT),) ifeq ($(FLASH2DAT),)
@ -71,11 +45,11 @@ FLASH2DAT := flash2dat
endif endif
ifeq ($(ALT_FILE_CONVERT),) ifeq ($(ALT_FILE_CONVERT),)
ALT_FILE_CONVERT := alt-file-convert$(WINDOWS_EXE) ALT_FILE_CONVERT := alt-file-convert
endif endif
ifeq ($(NM),) ifeq ($(NM),)
NM := nios2-elf-nm$(WINDOWS_EXE) NM := nios2-elf-nm
endif endif
ifeq ($(MKDIR),) ifeq ($(MKDIR),)
@ -113,16 +87,9 @@ MEM_INIT_QIP_FILE ?= $(MEM_INIT_DIR)/meminit.qip
#------------------------------------- #-------------------------------------
BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2 BOOT_LOADER_PATH ?= $(SOPC_KIT_NIOS2)/components/altera_nios2
BOOT_LOADER_CFI_LOC ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec BOOT_LOADER_CFI ?= $(BOOT_LOADER_PATH)/boot_loader_cfi.srec
BOOT_LOADER_CFI_BE_LOC ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec BOOT_LOADER_CFI_BE ?= $(BOOT_LOADER_PATH)/boot_loader_cfi_be.srec
ifdef WINDOWS_EXE
BOOT_LOADER_CFI=$(shell wslpath -w $(BOOT_LOADER_CFI_LOC))
BOOT_LOADER_CFI_BE=$(shell wslpath -w $(BOOT_LOADER_CFI_BE_LOC))
else # !WINDOWS_EXE
BOOT_LOADER_CFI=$(BOOT_LOADER_CFI_LOC)
BOOT_LOADER_CFI_BE=$(BOOT_LOADER_CFI_BE_LOC)
endif
#------------------------------------- #-------------------------------------
# Default Target # Default Target
@ -183,12 +150,12 @@ flash2dat_extra_args = $(mem_pad_flag) $(mem_reloc_input_flag)
# This following VERSION comment indicates the version of the tool used to # This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well. # generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 20.1 # ACDS_VERSION: 18.1
ACDS_VERSION := 20.1 ACDS_VERSION := 18.1
# This following BUILD_NUMBER comment indicates the build number of the tool # This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile. # used to generate this makefile.
# BUILD_NUMBER: 720 # BUILD_NUMBER: 625
# Optimize for simulation # Optimize for simulation
SIM_OPTIMIZE ?= 0 SIM_OPTIMIZE ?= 0
@ -214,8 +181,8 @@ HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).dat
SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym SYM_FILES += $(HDL_SIM_DIR)/$(MEM_0).sym
HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym HDL_SIM_INSTALL_FILES += $(HDL_SIM_INSTALL_DIR)/$(MEM_0).sym
$(MEM_0)_START := 0x00000000 $(MEM_0)_START := 0x00000000
$(MEM_0)_END := 0x0001ffff $(MEM_0)_END := 0x00007fff
$(MEM_0)_SPAN := 0x00020000 $(MEM_0)_SPAN := 0x00008000
$(MEM_0)_HIERARCHICAL_PATH := mem $(MEM_0)_HIERARCHICAL_PATH := mem
$(MEM_0)_WIDTH := 32 $(MEM_0)_WIDTH := 32
$(MEM_0)_HEX_DATA_WIDTH := 32 $(MEM_0)_HEX_DATA_WIDTH := 32
@ -292,25 +259,25 @@ flash: check_elf_exists $(FLASH_FILES)
#------------------------------------- #-------------------------------------
.PHONY: check_elf_exists .PHONY: check_elf_exists
check_elf_exists: $(call adjust-path,$(ELF)) check_elf_exists: $(ELF)
ifeq ($(ELF),) ifeq ($(ELF),)
$(error ELF var not set in mem_init.mk) $(error ELF var not set in mem_init.mk)
endif endif
$(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(call adjust-path,$(ELF)) $(filter-out $(FLASH_DAT_FILES),$(DAT_FILES)): %.dat: $(ELF)
$(post-process-info) $(post-process-info)
@$(MKDIR) $(@D) @$(MKDIR) $(@D)
$(ELF2DAT) --infile=$(call adjust-path-mixed,$<) --outfile=$@ \ $(ELF2DAT) --infile=$< --outfile=$@ \
--base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \ --base=$(mem_start_address) --end=$(mem_end_address) --width=$(mem_width) \
$(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args) $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2dat_extra_args)
$(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat $(foreach i,0 1 2 3 4 5 6 7,%_lane$(i).dat): %.dat
@true @true
ELF_TO_HEX_CMD_NO_BOOTLOADER = $(ELF2HEX) $(call adjust-path-mixed,$<) $(mem_start_address) $(mem_end_address) --width=$(mem_hex_width) \ ELF_TO_HEX_CMD_NO_BOOTLOADER = $(ELF2HEX) $< $(mem_start_address) $(mem_end_address) --width=$(mem_hex_width) \
$(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@ $(mem_endianness) --create-lanes=$(mem_create_lanes) $(elf2hex_extra_args) $@
ELF_TO_HEX_CMD_WITH_BOOTLOADER = $(ALT_FILE_CONVERT) -I $(NIOS2_ELF_FORMAT) -O hex --input=$(call adjust-path-mixed,$<) --output=$@ \ ELF_TO_HEX_CMD_WITH_BOOTLOADER = $(ALT_FILE_CONVERT) -I $(NIOS2_ELF_FORMAT) -O hex --input=$< --output=$@ \
--base=$(mem_start_address) --end=$(mem_end_address) --reset=$(RESET_ADDRESS) \ --base=$(mem_start_address) --end=$(mem_end_address) --reset=$(RESET_ADDRESS) \
--out-data-width=$(mem_hex_width) $(flash_mem_boot_loader_flag) --out-data-width=$(mem_hex_width) $(flash_mem_boot_loader_flag)
@ -319,20 +286,21 @@ ELF_TO_HEX_CMD = $(strip $(if $(flash_mem_boot_loader_flag), \
$(ELF_TO_HEX_CMD_NO_BOOTLOADER) \ $(ELF_TO_HEX_CMD_NO_BOOTLOADER) \
)) ))
$(HEX_FILES): %.hex: $(call adjust-path,$(ELF)) $(HEX_FILES): %.hex: $(ELF)
$(post-process-info) $(post-process-info)
@$(MKDIR) $(@D) @$(MKDIR) $(@D)
$(ELF_TO_HEX_CMD) $(ELF_TO_HEX_CMD)
$(SYM_FILES): %.sym: $(call adjust-path,$(ELF)) $(SYM_FILES): %.sym: $(ELF)
$(post-process-info) $(post-process-info)
@$(MKDIR) $(@D) @$(MKDIR) $(@D)
$(NM) -n $(call adjust-path-mixed,$<) > $@ $(NM) -n $< > $@
$(FLASH_FILES): %.flash: $(call adjust-path,$(ELF)) $(FLASH_FILES): %.flash: $(ELF)
$(post-process-info) $(post-process-info)
@$(MKDIR) $(@D) @$(MKDIR) $(@D)
$(ELF2FLASH) --input=$(call adjust-path-mixed,$<) --output=$@ --sim_optimize=$(SIM_OPTIMIZE) $(elf2flash_extra_args) $(ELF2FLASH) --input=$< --outfile=$@ --sim_optimize=$(SIM_OPTIMIZE) $(mem_endianness) \
$(elf2flash_extra_args)
# #
# Function generate_spd_entry # Function generate_spd_entry

4
Top/software/semafor_bsp/memory.gdb
View File

@ -3,7 +3,7 @@
# Machine generated for CPU 'cpu' in SOPC Builder design 'niosII' # Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
# SOPC Builder design path: ../../niosII.sopcinfo # SOPC Builder design path: ../../niosII.sopcinfo
# #
# Generated: Wed Oct 19 15:19:38 MSK 2022 # Generated: Tue Feb 07 13:28:19 MSK 2023
# DO NOT MODIFY THIS FILE # DO NOT MODIFY THIS FILE
# #
@ -47,4 +47,4 @@
# by allowing GDB to cache memory contents on the host. # by allowing GDB to cache memory contents on the host.
# mem # mem
memory 0x0 0x20000 cache memory 0x0 0x8000 cache

6
Top/software/semafor_bsp/public.mk
View File

@ -77,12 +77,12 @@ ALT_CPPFLAGS += -pipe
# This following VERSION comment indicates the version of the tool used to # This following VERSION comment indicates the version of the tool used to
# generate this makefile. A makefile variable is provided for VERSION as well. # generate this makefile. A makefile variable is provided for VERSION as well.
# ACDS_VERSION: 20.1 # ACDS_VERSION: 18.1
ACDS_VERSION := 20.1 ACDS_VERSION := 18.1
# This following BUILD_NUMBER comment indicates the build number of the tool # This following BUILD_NUMBER comment indicates the build number of the tool
# used to generate this makefile. # used to generate this makefile.
# BUILD_NUMBER: 720 # BUILD_NUMBER: 625
# Qsys--generated SOPCINFO file. Required for resolving node instance ID's with # Qsys--generated SOPCINFO file. Required for resolving node instance ID's with
# design component names. # design component names.

32
Top/software/semafor_bsp/settings.bsp
View File

@ -2,9 +2,9 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema"> <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType> <BspType>hal</BspType>
<BspVersion>default</BspVersion> <BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Jan 24, 2023 12:06:33 PM</BspGeneratedTimeStamp> <BspGeneratedTimeStamp>Feb 7, 2023 2:27:07 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1674551193679</BspGeneratedUnixTimeStamp> <BspGeneratedUnixTimeStamp>1675765627575</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>/run/media/user/B225-3235/Lab2/Top/software/semafor_bsp</BspGeneratedLocation> <BspGeneratedLocation>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile> <BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../niosII.sopcinfo</SopcDesignFile> <SopcDesignFile>../../niosII.sopcinfo</SopcDesignFile>
<JdiFile>default</JdiFile> <JdiFile>default</JdiFile>
@ -900,34 +900,28 @@
</Setting> </Setting>
<MemoryMap> <MemoryMap>
<slaveDescriptor>mem</slaveDescriptor> <slaveDescriptor>mem</slaveDescriptor>
<addressRange>0x00000000 - 0x0001FFFF</addressRange> <addressRange>0x00000000 - 0x00007FFF</addressRange>
<addressSpan>131072</addressSpan> <addressSpan>32768</addressSpan>
<attributes>memory</attributes> <attributes>memory</attributes>
</MemoryMap> </MemoryMap>
<MemoryMap>
<slaveDescriptor>sem_ram_slave</slaveDescriptor>
<addressRange>0x00021000 - 0x0002103F</addressRange>
<addressSpan>64</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap> <MemoryMap>
<slaveDescriptor>sys_clk_timer</slaveDescriptor> <slaveDescriptor>sys_clk_timer</slaveDescriptor>
<addressRange>0x00021040 - 0x0002105F</addressRange> <addressRange>0x00009000 - 0x0000901F</addressRange>
<addressSpan>32</addressSpan> <addressSpan>32</addressSpan>
<attributes>timer</attributes> <attributes>timer</attributes>
</MemoryMap> </MemoryMap>
<MemoryMap>
<slaveDescriptor>sem_ctl_slave</slaveDescriptor>
<addressRange>0x00021060 - 0x00021067</addressRange>
<addressSpan>8</addressSpan>
<attributes/>
</MemoryMap>
<MemoryMap> <MemoryMap>
<slaveDescriptor>jtag_uart</slaveDescriptor> <slaveDescriptor>jtag_uart</slaveDescriptor>
<addressRange>0x00021068 - 0x0002106F</addressRange> <addressRange>0x00009020 - 0x00009027</addressRange>
<addressSpan>8</addressSpan> <addressSpan>8</addressSpan>
<attributes>printable</attributes> <attributes>printable</attributes>
</MemoryMap> </MemoryMap>
<MemoryMap>
<slaveDescriptor>sigdel_0</slaveDescriptor>
<addressRange>0x00009028 - 0x0000902B</addressRange>
<addressSpan>4</addressSpan>
<attributes/>
</MemoryMap>
<LinkerSection> <LinkerSection>
<sectionName>.text</sectionName> <sectionName>.text</sectionName>
<regionName>mem</regionName> <regionName>mem</regionName>

17
Top/software/semafor_bsp/summary.html
View File

@ -22,13 +22,13 @@
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td> <td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Jan 24, 2023 12:06:33 PM</td> <td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Feb 7, 2023 2:27:07 PM</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1674551193679</td> <td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1675765627575</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>/run/media/user/B225-3235/Lab2/Top/software/semafor_bsp</td> <td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</td>
</tr> </tr>
</table> </table>
<br> <br>
@ -38,19 +38,16 @@
<th align="left" width="20%">Slave Descriptor</th><th align="left" width="40%">Address Range</th><th align="left" width="20%">Size</th><th align="left" width="20%">Attributes</th> <th align="left" width="20%">Slave Descriptor</th><th align="left" width="40%">Address Range</th><th align="left" width="20%">Size</th><th align="left" width="20%">Attributes</th>
</tr> </tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'"> <tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>jtag_uart</td><td>0x00021068 - 0x0002106F</td><td>8</td><td class="listing">printable</td> <td>sigdel_0</td><td>0x00009028 - 0x0000902B</td><td>4</td><td class="listing">&nbsp;</td>
</tr> </tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'"> <tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>sem_ctl_slave</td><td>0x00021060 - 0x00021067</td><td>8</td><td class="listing">&nbsp;</td> <td>jtag_uart</td><td>0x00009020 - 0x00009027</td><td>8</td><td class="listing">printable</td>
</tr> </tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'"> <tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>sys_clk_timer</td><td>0x00021040 - 0x0002105F</td><td>32</td><td class="listing">timer</td> <td>sys_clk_timer</td><td>0x00009000 - 0x0000901F</td><td>32</td><td class="listing">timer</td>
</tr> </tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'"> <tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>sem_ram_slave</td><td>0x00021000 - 0x0002103F</td><td>64</td><td class="listing">&nbsp;</td> <td>mem</td><td>0x00000000 - 0x00007FFF</td><td>32768</td><td class="listing">memory</td>
</tr>
<tr mode="wrap" STYLE="display: 'block'; font-family: 'courier'; color: '#000000'; font-weight: '500'; font-size: '14'; margin-top: '10pt'; text-align: 'left'">
<td>mem</td><td>0x00000000 - 0x0001FFFF</td><td>131072</td><td class="listing">memory</td>
</tr> </tr>
</table> </table>
<br> <br>

60
Top/software/semafor_bsp/system.h
View File

@ -4,7 +4,7 @@
* Machine generated for CPU 'cpu' in SOPC Builder design 'niosII' * Machine generated for CPU 'cpu' in SOPC Builder design 'niosII'
* SOPC Builder design path: ../../niosII.sopcinfo * SOPC Builder design path: ../../niosII.sopcinfo
* *
* Generated: Thu Dec 22 22:44:18 MSK 2022 * Generated: Tue Feb 07 13:28:19 MSK 2023
*/ */
/* /*
@ -62,13 +62,13 @@
#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2" #define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
#define ALT_CPU_BIG_ENDIAN 0 #define ALT_CPU_BIG_ENDIAN 0
#define ALT_CPU_BREAK_ADDR 0x00020820 #define ALT_CPU_BREAK_ADDR 0x00008820
#define ALT_CPU_CPU_ARCH_NIOS2_R1 #define ALT_CPU_CPU_ARCH_NIOS2_R1
#define ALT_CPU_CPU_FREQ 50000000u #define ALT_CPU_CPU_FREQ 50000000u
#define ALT_CPU_CPU_ID_SIZE 1 #define ALT_CPU_CPU_ID_SIZE 1
#define ALT_CPU_CPU_ID_VALUE 0x00000000 #define ALT_CPU_CPU_ID_VALUE 0x00000000
#define ALT_CPU_CPU_IMPLEMENTATION "tiny" #define ALT_CPU_CPU_IMPLEMENTATION "tiny"
#define ALT_CPU_DATA_ADDR_WIDTH 0x12 #define ALT_CPU_DATA_ADDR_WIDTH 0x10
#define ALT_CPU_DCACHE_LINE_SIZE 0 #define ALT_CPU_DCACHE_LINE_SIZE 0
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0 #define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_DCACHE_SIZE 0 #define ALT_CPU_DCACHE_SIZE 0
@ -87,7 +87,7 @@
#define ALT_CPU_ICACHE_LINE_SIZE 0 #define ALT_CPU_ICACHE_LINE_SIZE 0
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0 #define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
#define ALT_CPU_ICACHE_SIZE 0 #define ALT_CPU_ICACHE_SIZE 0
#define ALT_CPU_INST_ADDR_WIDTH 0x12 #define ALT_CPU_INST_ADDR_WIDTH 0x10
#define ALT_CPU_NAME "cpu" #define ALT_CPU_NAME "cpu"
#define ALT_CPU_OCI_VERSION 1 #define ALT_CPU_OCI_VERSION 1
#define ALT_CPU_RESET_ADDR 0x00000000 #define ALT_CPU_RESET_ADDR 0x00000000
@ -99,13 +99,13 @@
*/ */
#define NIOS2_BIG_ENDIAN 0 #define NIOS2_BIG_ENDIAN 0
#define NIOS2_BREAK_ADDR 0x00020820 #define NIOS2_BREAK_ADDR 0x00008820
#define NIOS2_CPU_ARCH_NIOS2_R1 #define NIOS2_CPU_ARCH_NIOS2_R1
#define NIOS2_CPU_FREQ 50000000u #define NIOS2_CPU_FREQ 50000000u
#define NIOS2_CPU_ID_SIZE 1 #define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0x00000000 #define NIOS2_CPU_ID_VALUE 0x00000000
#define NIOS2_CPU_IMPLEMENTATION "tiny" #define NIOS2_CPU_IMPLEMENTATION "tiny"
#define NIOS2_DATA_ADDR_WIDTH 0x12 #define NIOS2_DATA_ADDR_WIDTH 0x10
#define NIOS2_DCACHE_LINE_SIZE 0 #define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0 #define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_DCACHE_SIZE 0 #define NIOS2_DCACHE_SIZE 0
@ -123,7 +123,7 @@
#define NIOS2_ICACHE_LINE_SIZE 0 #define NIOS2_ICACHE_LINE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0 #define NIOS2_ICACHE_LINE_SIZE_LOG2 0
#define NIOS2_ICACHE_SIZE 0 #define NIOS2_ICACHE_SIZE 0
#define NIOS2_INST_ADDR_WIDTH 0x12 #define NIOS2_INST_ADDR_WIDTH 0x10
#define NIOS2_OCI_VERSION 1 #define NIOS2_OCI_VERSION 1
#define NIOS2_RESET_ADDR 0x00000000 #define NIOS2_RESET_ADDR 0x00000000
@ -137,7 +137,7 @@
#define __ALTERA_AVALON_ONCHIP_MEMORY2 #define __ALTERA_AVALON_ONCHIP_MEMORY2
#define __ALTERA_AVALON_TIMER #define __ALTERA_AVALON_TIMER
#define __ALTERA_NIOS2_GEN2 #define __ALTERA_NIOS2_GEN2
#define __SEM #define __SIGDEL
/* /*
@ -156,19 +156,19 @@
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1 #define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
#define ALT_NUM_INTERRUPT_CONTROLLERS 1 #define ALT_NUM_INTERRUPT_CONTROLLERS 1
#define ALT_STDERR "/dev/jtag_uart" #define ALT_STDERR "/dev/jtag_uart"
#define ALT_STDERR_BASE 0x21068 #define ALT_STDERR_BASE 0x9020
#define ALT_STDERR_DEV jtag_uart #define ALT_STDERR_DEV jtag_uart
#define ALT_STDERR_IS_JTAG_UART #define ALT_STDERR_IS_JTAG_UART
#define ALT_STDERR_PRESENT #define ALT_STDERR_PRESENT
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart" #define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN "/dev/jtag_uart" #define ALT_STDIN "/dev/jtag_uart"
#define ALT_STDIN_BASE 0x21068 #define ALT_STDIN_BASE 0x9020
#define ALT_STDIN_DEV jtag_uart #define ALT_STDIN_DEV jtag_uart
#define ALT_STDIN_IS_JTAG_UART #define ALT_STDIN_IS_JTAG_UART
#define ALT_STDIN_PRESENT #define ALT_STDIN_PRESENT
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart" #define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT "/dev/jtag_uart" #define ALT_STDOUT "/dev/jtag_uart"
#define ALT_STDOUT_BASE 0x21068 #define ALT_STDOUT_BASE 0x9020
#define ALT_STDOUT_DEV jtag_uart #define ALT_STDOUT_DEV jtag_uart
#define ALT_STDOUT_IS_JTAG_UART #define ALT_STDOUT_IS_JTAG_UART
#define ALT_STDOUT_PRESENT #define ALT_STDOUT_PRESENT
@ -193,7 +193,7 @@
*/ */
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart #define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
#define JTAG_UART_BASE 0x21068 #define JTAG_UART_BASE 0x9020
#define JTAG_UART_IRQ 1 #define JTAG_UART_IRQ 1
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0 #define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
#define JTAG_UART_NAME "/dev/jtag_uart" #define JTAG_UART_NAME "/dev/jtag_uart"
@ -228,38 +228,24 @@
#define MEM_READ_DURING_WRITE_MODE "DONT_CARE" #define MEM_READ_DURING_WRITE_MODE "DONT_CARE"
#define MEM_SINGLE_CLOCK_OP 1 #define MEM_SINGLE_CLOCK_OP 1
#define MEM_SIZE_MULTIPLE 1 #define MEM_SIZE_MULTIPLE 1
#define MEM_SIZE_VALUE 131072 #define MEM_SIZE_VALUE 32768
#define MEM_SPAN 131072 #define MEM_SPAN 32768
#define MEM_TYPE "altera_avalon_onchip_memory2" #define MEM_TYPE "altera_avalon_onchip_memory2"
#define MEM_WRITABLE 1 #define MEM_WRITABLE 1
/* /*
* sem_ctl_slave configuration * sigdel_0 configuration
* *
*/ */
#define ALT_MODULE_CLASS_sem_ctl_slave sem #define ALT_MODULE_CLASS_sigdel_0 sigdel
#define SEM_CTL_SLAVE_BASE 0x21060 #define SIGDEL_0_BASE 0x9028
#define SEM_CTL_SLAVE_IRQ -1 #define SIGDEL_0_IRQ -1
#define SEM_CTL_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1 #define SIGDEL_0_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SEM_CTL_SLAVE_NAME "/dev/sem_ctl_slave" #define SIGDEL_0_NAME "/dev/sigdel_0"
#define SEM_CTL_SLAVE_SPAN 8 #define SIGDEL_0_SPAN 4
#define SEM_CTL_SLAVE_TYPE "sem" #define SIGDEL_0_TYPE "sigdel"
/*
* sem_ram_slave configuration
*
*/
#define ALT_MODULE_CLASS_sem_ram_slave sem
#define SEM_RAM_SLAVE_BASE 0x21000
#define SEM_RAM_SLAVE_IRQ -1
#define SEM_RAM_SLAVE_IRQ_INTERRUPT_CONTROLLER_ID -1
#define SEM_RAM_SLAVE_NAME "/dev/sem_ram_slave"
#define SEM_RAM_SLAVE_SPAN 64
#define SEM_RAM_SLAVE_TYPE "sem"
/* /*
@ -269,7 +255,7 @@
#define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer #define ALT_MODULE_CLASS_sys_clk_timer altera_avalon_timer
#define SYS_CLK_TIMER_ALWAYS_RUN 0 #define SYS_CLK_TIMER_ALWAYS_RUN 0
#define SYS_CLK_TIMER_BASE 0x21040 #define SYS_CLK_TIMER_BASE 0x9000
#define SYS_CLK_TIMER_COUNTER_SIZE 32 #define SYS_CLK_TIMER_COUNTER_SIZE 32
#define SYS_CLK_TIMER_FIXED_PERIOD 0 #define SYS_CLK_TIMER_FIXED_PERIOD 0
#define SYS_CLK_TIMER_FREQ 50000000 #define SYS_CLK_TIMER_FREQ 50000000