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done lr4, programmed hardware

This commit is contained in:
Ivan I. Ovchinnikov 2023-02-07 16:10:37 +03:00
parent b551fd0a26
commit e53eb0ff97
21 changed files with 256 additions and 97 deletions
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8
HDL/sdmod.sv
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@ -7,17 +7,17 @@ module sdmod (
logic out;
logic signed [7:0] eps;
logic signed [7:0] un;
logic signed [8:0] un;
always_ff @(posedge clk, negedge reset) begin
if (~reset) begin
un <= 8'd0;
un <= 9'd0;
end else begin
un <= val - eps;
end
end
assign out = (un >= $signed(8'd0)) ? 1'd1 : 1'd0;
assign eps = (un >= $signed(8'd0)) ? $signed(8'd126) - un : $signed(-8'd126) - un;
assign out = (un >= $signed(9'd0)) ? 1'd1 : 1'd0;
assign eps = (un >= $signed(9'd0)) ? $signed(9'd126) - un : $signed(-9'd126) - un;
assign daco = out;
endmodule

4
HDL/sigdel.sv
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@ -1,7 +1,7 @@
//top-level module
module sigdel
#(
PHACC_WIDTH = 14
PHACC_WIDTH = 27
) (
//clock and reset
input logic clk, clr_n,
@ -24,7 +24,7 @@ module sigdel
end
end
phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
phacc phacc_inst (.phinc(1'b1), .clk(clk), .reset(clr_n), .phase(phase));
defparam phacc_inst.WIDTH = PHACC_WIDTH;
sinelut sinelut_inst (

10
Testbench/sigdel/sigdel.qsf
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@ -37,16 +37,15 @@
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22A7
set_global_assignment -name DEVICE EP4CE15F23C8
set_global_assignment -name TOP_LEVEL_ENTITY sigdel
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:16:23 JANUARY 27, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
@ -74,4 +73,7 @@ set_global_assignment -name EDA_TEST_BENCH_NAME sigdel_tb -section_id eda_simula
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sigdel_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sigdel_tb -section_id sigdel_tb
set_global_assignment -name EDA_TEST_BENCH_FILE sigdel_tb.sv -section_id sigdel_tb
set_location_assignment PIN_T2 -to clk
set_location_assignment PIN_E4 -to clr_n
set_location_assignment PIN_E3 -to fout
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Testbench/sigdel/sigdel.qws
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10
Top/niosII.qsys
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@ -105,6 +105,14 @@
type = "String";
}
}
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element sigdel_0
{
datum _sortIndex
@ -401,7 +409,7 @@
<parameter name="writable" value="true" />
</module>
<module name="sigdel_0" kind="sigdel" version="1.0" enabled="1">
<parameter name="PHACC_WIDTH" value="14" />
<parameter name="PHACC_WIDTH" value="26" />
</module>
<module
name="sys_clk_timer"

6
Top/niosII.sopcinfo
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@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="niosII" version="1.0" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2023.02.07.13:18:47 -->
<!-- 2023.02.07.17:03:00 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1675761526</value>
<value>1675774980</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
@ -5649,7 +5649,7 @@ parameters are a RESULT of the module parameters. -->
the requested settings for a module instance. -->
<parameter name="PHACC_WIDTH">
<type>int</type>
<value>14</value>
<value>26</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>

6
Top/niosII/niosII.html
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@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2023.02.07.13:18:47</td>
<td class="l">2023.02.07.17:03:00</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -1800,7 +1800,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table>
<tr>
<td class="parametername">PHACC_WIDTH</td>
<td class="parametervalue">14</td>
<td class="parametervalue">26</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
@ -2018,7 +2018,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.02 seconds</td>
<td class="r">rendering took 0.03 seconds</td>
</tr>
</table>
</body>

126
Top/niosII/niosII.xml
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8
Top/niosII/synthesis/niosII.debuginfo
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@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="niosII" kind="system" version="18.1" fabric="QSYS">
<!-- Format version 18.1 625 (Future versions may contain additional information.) -->
<!-- 2023.02.07.13:18:51 -->
<!-- 2023.02.07.17:03:05 -->
<!-- A collection of modules and connections -->
<parameter name="clockCrossingAdapter">
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
@ -53,7 +53,7 @@
</parameter>
<parameter name="generationId">
<type>int</type>
<value>1675761526</value>
<value>1675774980</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -5678,7 +5678,7 @@ parameters are a RESULT of the module parameters. -->
the requested settings for a module instance. -->
<parameter name="PHACC_WIDTH">
<type>int</type>
<value>14</value>
<value>26</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
@ -12167,5 +12167,5 @@ parameters are a RESULT of the module parameters. -->
<version>18.1</version>
</plugin>
<reportVersion>18.1 625</reportVersion>
<uniqueIdentifier>CE053227F4B7000001862B2BACF3</uniqueIdentifier>
<uniqueIdentifier>CE053227F4B7000001862BF8F68D</uniqueIdentifier>
</EnsembleReport>

6
Top/niosII/synthesis/niosII.qip
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@ -2,7 +2,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_NAME "Qsy
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_VERSION "18.1"
set_global_assignment -entity "niosII" -library "niosII" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "niosII" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../niosII.sopcinfo"]
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1675761526"
set_global_assignment -entity "niosII" -library "niosII" -name SLD_INFO "QSYS_NAME niosII HAS_SOPCINFO 1 GENERATION_ID 1675774980"
set_global_assignment -library "niosII" -name MISC_FILE [file join $::quartus(qip_path) "../niosII.cmp"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.regmap"]
set_global_assignment -library "niosII" -name SLD_FILE [file join $::quartus(qip_path) "niosII.debuginfo"]
@ -16,7 +16,7 @@ set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_DISP
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "On"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3NTc2MTUyNg==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY3NTc3NDk4MA==::QXV0byBHRU5FUkFUSU9OX0lE"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ"
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0UxNUYyM0M4::QXV0byBERVZJQ0U="
set_global_assignment -entity "niosII" -library "niosII" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
@ -667,7 +667,7 @@ set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_DISP
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_INTERNAL "Off"
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_VERSION "MS4w"
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_PARAMETER "UEhBQ0NfV0lEVEg=::MTQ=::UEhBQ0NfV0lEVEg="
set_global_assignment -entity "sigdel" -library "niosII" -name IP_COMPONENT_PARAMETER "UEhBQ0NfV0lEVEg=::MjY=::UEhBQ0NfV0lEVEg="
set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_NAME "bmlvc0lJX21lbQ=="
set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00pIEludGVsIEZQR0EgSVA="
set_global_assignment -entity "niosII_mem" -library "niosII" -name IP_COMPONENT_REPORT_HIERARCHY "Off"

2
Top/niosII/synthesis/niosII.v
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@ -128,7 +128,7 @@ module niosII (
);
sigdel #(
.PHACC_WIDTH (14)
.PHACC_WIDTH (26)
) sigdel_0 (
.clk (clk_clk), // clock.clk
.clr_n (~rst_controller_reset_out_reset), // reset_sink.reset_n

2
Top/semafor.qsf
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@ -61,4 +61,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_location_assignment PIN_T2 -to CLOCK_50
set_location_assignment PIN_E3 -to LEDG[0]
set_location_assignment PIN_C21 -to FOUTA
set_location_assignment PIN_E4 -to nreset
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Top/semafor.qws
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4
Top/sigdel_hw.tcl
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@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1
# Fri Jan 27 18:48:38 MSK 2023
# Tue Feb 07 16:48:35 MSK 2023
# DO NOT MODIFY
#
# sigdel "Sigma-Delta Modulator" v1.0
# 2023.01.27.18:48:38
# 2023.02.07.16:48:35
#
#

143
Top/sigdel_hw.tcl~ Normal file
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@ -0,0 +1,143 @@
# TCL File Generated by Component Editor 18.1
# Fri Jan 27 18:48:38 MSK 2023
# DO NOT MODIFY
#
# sigdel "Sigma-Delta Modulator" v1.0
# 2023.01.27.18:48:38
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module sigdel
#
set_module_property DESCRIPTION ""
set_module_property NAME sigdel
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "User Logic"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "Sigma-Delta Modulator"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL sigdel
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file phacc.sv SYSTEM_VERILOG PATH ../HDL/phacc.sv
add_fileset_file sdmod.sv SYSTEM_VERILOG PATH ../HDL/sdmod.sv
add_fileset_file sigdel.sv SYSTEM_VERILOG PATH ../HDL/sigdel.sv TOP_LEVEL_FILE
add_fileset_file sinelut.v VERILOG PATH ../HDL/IP/sinelut.v
add_fileset_file sine256.mif MIF PATH ../HDL/IP/sine256.mif
#
# parameters
#
add_parameter PHACC_WIDTH INTEGER 14
set_parameter_property PHACC_WIDTH DEFAULT_VALUE 14
set_parameter_property PHACC_WIDTH DISPLAY_NAME PHACC_WIDTH
set_parameter_property PHACC_WIDTH TYPE INTEGER
set_parameter_property PHACC_WIDTH UNITS None
set_parameter_property PHACC_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property PHACC_WIDTH HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset_sink
#
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
add_interface_port reset_sink clr_n reset_n Input 1
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock ""
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end fout writeresponsevalid_n Output 1
#
# connection point avalon_slave
#
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock
set_interface_property avalon_slave associatedReset reset_sink
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits WORDS
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 0
set_interface_property avalon_slave readWaitTime 1
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
set_interface_property avalon_slave ENABLED true
set_interface_property avalon_slave EXPORT_OF ""
set_interface_property avalon_slave PORT_NAME_MAP ""
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave wr_n write_n Input 1
add_interface_port avalon_slave wr_data writedata Input 32
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0

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Top/software/deltasigma/deltasigma.elf
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2
Top/software/deltasigma/deltasigma.objdump
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@ -489,7 +489,7 @@ Disassembly of section .text:
26c: dfc00115 stw ra,4(sp)
270: df000015 stw fp,0(sp)
274: d839883a mov fp,sp
278: 00c00974 movhi r3,37
278: 00c80004 movi r3,8192
27c: 00a40a14 movui r2,36904
280: 10c00035 stwio r3,0(r2)
284: 01000034 movhi r4,0

2
Top/software/deltasigma/main.c
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@ -15,7 +15,7 @@
int main() {
IOWR_DELSIG_CTL(SIGDEL_0_BASE, 0x250000);
IOWR_DELSIG_CTL(SIGDEL_0_BASE, 0x2000);
printf("Ready\n");
while (1) {}
return 0;

4
Top/software/semafor_bsp/settings.bsp
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@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Feb 7, 2023 2:27:07 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1675765627575</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Feb 7, 2023 4:54:12 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1675774452122</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../niosII.sopcinfo</SopcDesignFile>

4
Top/software/semafor_bsp/summary.html
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@ -22,10 +22,10 @@
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Feb 7, 2023 2:27:07 PM</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Feb 7, 2023 4:54:12 PM</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1675765627575</td>
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1675774452122</td>
</tr>
<tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</td>

6
Top/top.sv
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@ -18,6 +18,9 @@ module top
(
// reset
nreset,
//////////// CLOCK //////////
CLOCK_50,
CLOCK2_50,
@ -34,6 +37,7 @@ output FOUTA;
input CLOCK_50;
input CLOCK2_50;
input CLOCK3_50;
input nreset;
//////////// LED //////////
output [8:0] LEDG;
@ -42,7 +46,7 @@ output [17:0] LEDR;
niosII u0 (
.clk_clk (CLOCK_50), // clk.clk
.conduit_end_writeresponsevalid_n (LEDG[0]), // conduit_end.writeresponsevalid_n
.reset_reset_n (1'b1) // reset.reset_n
.reset_reset_n (nreset) // reset.reset_n
);