done lr4, programmed hardware

.gitignore

@@ -2,6 +2,8 @@
 *.rpt
 *.bak
 .#*
+#*.*#
+.*~
 
 /db
 /incremental_db
@@ -19,11 +21,15 @@ drivers/
 HAL/
 Part_test/
 .metadata/
+.settings/
 RemoteSystemsTempFiles/
 aldec/
 cadence/
 synopsys/
 
+db/
+incremental_db/
+*.xml
 
 /testbenches/*.bak
 /common_uart/*.bak

HDL/IP/sine256.mif

@@ -0,0 +1,242 @@
+WIDTH = 8;
+DEPTH = 256;
+
+ADDRESS_RADIX = DEC;
+DATA_RADIX = HEX;
+
+CONTENT BEGIN
+	0 : 02;
+	1 : 05;
+	2 : 08;
+	3 : 0B;
+	4 : 0E;
+	5 : 11;
+	6 : 14;
+	7 : 17;
+	8 : 1A;
+	9 : 1D;
+	10 : 20;
+	11 : 23;
+	12 : 26;
+	13 : 29;
+	14 : 2C;
+	15 : 2F;
+	16 : 32;
+	17 : 35;
+	18 : 38;
+	19 : 3A;
+	20 : 3D;
+	21 : 40;
+	22 : 43;
+	23 : 45;
+	24 : 48;
+	25 : 4A;
+	26 : 4D;
+	27 : 4F;
+	28 : 52;
+	29 : 54;
+	30 : 56;
+	31 : 59;
+	32 : 5B;
+	33 : 5D;
+	34 : 5F;
+	35 : 61;
+	36 : 63;
+	37 : 65;
+	38 : 67;
+	39 : 69;
+	40 : 6A;
+	41 : 6C;
+	42 : 6E;
+	43 : 6F;
+	44 : 71;
+	45 : 72;
+	46 : 73;
+	47 : 75;
+	48 : 76;
+	49 : 77;
+	50 : 78;
+	51 : 79;
+	52 : 7A;
+	53 : 7B;
+	54 : 7C;
+	55 : 7C;
+	56 : 7D;
+	57 : 7D;
+	[58..69] : 7E;
+	70 : 7D;
+	71 : 7D;
+	72 : 7C;
+	73 : 7C;
+	74 : 7B;
+	75 : 7A;
+	76 : 79;
+	77 : 78;
+	78 : 77;
+	79 : 76;
+	80 : 75;
+	81 : 73;
+	82 : 72;
+	83 : 71;
+	84 : 6F;
+	85 : 6E;
+	86 : 6C;
+	87 : 6A;
+	88 : 69;
+	89 : 67;
+	90 : 65;
+	91 : 63;
+	92 : 61;
+	93 : 5F;
+	94 : 5D;
+	95 : 5B;
+	96 : 59;
+	97 : 56;
+	98 : 54;
+	99 : 52;
+	100 : 4F;
+	101 : 4D;
+	102 : 4A;
+	103 : 48;
+	104 : 45;
+	105 : 43;
+	106 : 40;
+	107 : 3D;
+	108 : 3A;
+	109 : 38;
+	110 : 35;
+	111 : 32;
+	112 : 2F;
+	113 : 2C;
+	114 : 29;
+	115 : 26;
+	116 : 23;
+	117 : 20;
+	118 : 1D;
+	119 : 1A;
+	120 : 17;
+	121 : 14;
+	122 : 11;
+	123 : 0E;
+	124 : 0B;
+	125 : 08;
+	126 : 05;
+	127 : 02;
+	128 : FE;
+	129 : FB;
+	130 : F8;
+	131 : F5;
+	132 : F2;
+	133 : EF;
+	134 : EC;
+	135 : E9;
+	136 : E6;
+	137 : E3;
+	138 : E0;
+	139 : DD;
+	140 : DA;
+	141 : D7;
+	142 : D4;
+	143 : D1;
+	144 : CE;
+	145 : CB;
+	146 : C8;
+	147 : C6;
+	148 : C3;
+	149 : C0;
+	150 : BD;
+	151 : BB;
+	152 : B8;
+	153 : B6;
+	154 : B3;
+	155 : B1;
+	156 : AE;
+	157 : AC;
+	158 : AA;
+	159 : A7;
+	160 : A5;
+	161 : A3;
+	162 : A1;
+	163 : 9F;
+	164 : 9D;
+	165 : 9B;
+	166 : 99;
+	167 : 97;
+	168 : 96;
+	169 : 94;
+	170 : 92;
+	171 : 91;
+	172 : 8F;
+	173 : 8E;
+	174 : 8D;
+	175 : 8B;
+	176 : 8A;
+	177 : 89;
+	178 : 88;
+	179 : 87;
+	180 : 86;
+	181 : 85;
+	182 : 84;
+	183 : 84;
+	184 : 83;
+	185 : 83;
+	[186..197] : 82;
+	198 : 83;
+	199 : 83;
+	200 : 84;
+	201 : 84;
+	202 : 85;
+	203 : 86;
+	204 : 87;
+	205 : 88;
+	206 : 89;
+	207 : 8A;
+	208 : 8B;
+	209 : 8D;
+	210 : 8E;
+	211 : 8F;
+	212 : 91;
+	213 : 92;
+	214 : 94;
+	215 : 96;
+	216 : 97;
+	217 : 99;
+	218 : 9B;
+	219 : 9D;
+	220 : 9F;
+	221 : A1;
+	222 : A3;
+	223 : A5;
+	224 : A7;
+	225 : AA;
+	226 : AC;
+	227 : AE;
+	228 : B1;
+	229 : B3;
+	230 : B6;
+	231 : B8;
+	232 : BB;
+	233 : BD;
+	234 : C0;
+	235 : C3;
+	236 : C6;
+	237 : C8;
+	238 : CB;
+	239 : CE;
+	240 : D1;
+	241 : D4;
+	242 : D7;
+	243 : DA;
+	244 : DD;
+	245 : E0;
+	246 : E3;
+	247 : E6;
+	248 : E9;
+	249 : EC;
+	250 : EF;
+	251 : F2;
+	252 : F5;
+	253 : F8;
+	254 : FB;
+	255 : FE;
+END;

HDL/IP/sinelut.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "18.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sinelut.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sinelut_bb.v"]

HDL/IP/sinelut.v

@@ -0,0 +1,159 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: sinelut.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2018  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module sinelut (
+	address,
+	clock,
+	q);
+
+	input	[7:0]  address;
+	input	  clock;
+	output	[7:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a ({8{1'b1}}),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "sine256.mif",
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "sine256.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "sine256.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf

HDL/IP/sinelut_bb.v

@@ -0,0 +1,110 @@
+// megafunction wizard: %ROM: 1-PORT%VBB%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: sinelut.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+// ************************************************************
+
+//Copyright (C) 2018  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel FPGA IP License Agreement, or other applicable license
+//agreement, including, without limitation, that your use is for
+//the sole purpose of programming logic devices manufactured by
+//Intel and sold by Intel or its authorized distributors.  Please
+//refer to the applicable agreement for further details.
+
+module sinelut (
+	address,
+	clock,
+	q);
+
+	input	[7:0]  address;
+	input	  clock;
+	output	[7:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "sine256.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "sine256.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_bb.v TRUE
+// Retrieval info: LIB_FILE: altera_mf

HDL/IP/sinelut_inst.v

@@ -0,0 +1,5 @@
+sinelut	sinelut_inst (
+	.address ( address_sig ),
+	.clock ( clock_sig ),
+	.q ( q_sig )
+	);

HDL/phacc.sv

@@ -0,0 +1,23 @@
+module phacc
+  #(
+    parameter unsigned WIDTH = 14
+    ) (
+	   input logic [7:0] phinc,
+	   input             clk,
+	   input             reset,
+	   output [7:0]      phase
+       );
+
+    logic [WIDTH - 1 : 0] sum;
+
+    always_ff @(posedge clk, negedge reset) begin
+	    if (~reset) begin
+		    sum <= 0;
+	    end else begin
+		    sum <= sum + phinc;
+	    end
+    end
+
+    assign phase = sum[WIDTH - 1 : WIDTH - 8];
+
+endmodule

HDL/sdmod.sv

@@ -0,0 +1,23 @@
+module sdmod (
+	input signed [7:0] val,
+	input clk,
+	input reset,
+	output daco
+);
+
+logic out;
+logic signed [7:0] eps;
+logic signed [8:0] un;
+
+always_ff @(posedge clk, negedge reset) begin
+	if (~reset) begin
+		un <= 9'd0;
+	end else begin		
+		un <= val - eps;
+	end
+end
+
+assign out  = (un >= $signed(9'd0)) ? 1'd1                 : 1'd0;
+assign eps  = (un >= $signed(9'd0)) ? $signed(9'd126) - un : $signed(-9'd126) - un;
+assign daco = out;
+endmodule

HDL/sigdel.sv

@@ -0,0 +1,37 @@
+//top-level module
+module sigdel
+#(
+    PHACC_WIDTH = 27
+) (
+	//clock and reset
+	input logic clk, clr_n,
+	//control slave
+	input logic [31:0] wr_data,
+	input logic wr_n,
+	output logic fout
+);
+
+	logic [7:0] phinc_val, phase, sine;
+	
+	//control slave logic
+	always_ff @ (posedge clk or negedge clr_n) begin
+		if (!clr_n) begin
+			phinc_val[7:0] <= 8'd0;
+		end else	begin
+			if (!wr_n) begin
+				phinc_val[7:0] <= wr_data[31:0];
+			end
+		end
+	end
+
+	phacc phacc_inst (.phinc(1'b1), .clk(clk), .reset(clr_n), .phase(phase));
+	defparam phacc_inst.WIDTH = PHACC_WIDTH;
+	
+	sinelut sinelut_inst (
+       .address (phase), .clock (clk), .q(sine)
+	);
+	
+	sdmod sdmod_inst (
+	    .val(sine), .clk(clk), .reset(clr_n), .daco(fout)
+	);
+endmodule

Testbench/dec/#dec_tb.sv#

@@ -1,128 +0,0 @@
-`timescale 1 ns/1 ns
-
-module dec_tb();
-
-	// Wires and variables to connect to UUT (unit under test)
-	logic clk, clrn, train;
-	logic r, y, g;
-    logic [1:0] div;
-	logic ctl_wr, ctl_rd;
-	logic ctl_addr;
-	logic [31:0] ctl_wrdata;
-	logic [31:0] ctl_rddata;
-	logic ram_wr;
-	logic [3:0] ram_addr;
-	logic [31:0] ram_wrdata;
-
-    logic [31:0] divisor[3:0] = {
-        {8'd10, 8'd70, 8'd50, 8'd20},
-        {8'd10, 8'd30, 8'd40, 8'd30},
-        {8'd10, 8'd30, 8'd10, 8'd100},
-        {8'd10, 8'd60, 8'd80, 8'd50}
-    };
-	
-	// Instantiate UUT
-	dec my_sem(
-        .clk(clk), .clrn(clrn),
-        .ctl_wr(ctl_wr), .ctl_rd(ctl_rd), 
-        .ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
-        .ram_wr(ram_wr),
-        .ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
-		.train(train), .red(r), .yellow(y), .green(g)
-    );
-
-	// Clock definition
-	initial begin
-		clk = 0;
-		forever #10 clk = ~clk;
-	end
-	
-	// Divisor and train definition
-	initial begin
-        //initial reset
-        clrn = 0;
-		div = 0;
-		train = 0;
-        //take reset off
-        @(negedge clk) clrn = 1;
-        //configure semaphore
-        for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]);        //write divisor RAM
-        write_reg_transaction(1,div);   //write initial divisor
-        write_reg_transaction(0,1);     //enable semaphore
-        //run trains
-		repeat (4)
-		begin
-            repeat (10) @(posedge clk);
-			train=1;
-            repeat (4) @(posedge clk);
-			train=0;
-			wait ({r,y,g}==3'b001);
-            repeat (10) @(posedge clk);
-            write_reg_transaction(1,div);
-            div=div+1;
-		end
-        //wait a little
-		repeat (10) @(posedge clk); 
-        $stop;
-	end
-	
-	//Single register write transaction task
-	task write_reg_transaction;
-		//input signals
-		input [1:0] offs;
-		input [31:0] val;
-		//transaction implementation
-		begin
-			@(posedge clk);
-			//assert signals for one clock cycle
-			ctl_wr = 1;
-			ctl_addr = offs;
-			ctl_wrdata = val;
-			@(posedge clk);
-			//deassert signals
-			ctl_wr = 0;
-			ctl_addr = 'bx;
-			ctl_wrdata = 'bx;
-		end
-	endtask
-
-	//Single register read transaction task
-	task read_reg_transaction;
-		//input signals
-		input [1:0] offs;
-		output [31:0] val;
-		//transaction implementation
-		begin
-			@(posedge clk);
-			//assert signals for one clock cycle
-			ctl_rd = 1;
-			ctl_addr = offs;
-			@(posedge clk);
-            val = ctl_rddata;
-			//deassert signals
-			ctl_rd = 0;
-			ctl_addr = 'bx;
-		end
-	endtask
-
-	//RAM write transaction task
-	task write_ram_transaction;
-		//input signals
-		input [1:0] offs;
-		input [31:0] val;
-		//transaction implementation
-		begin
-			@(posedge clk);
-			//assert signals for one clock cycle
-			ram_wr = 1;
-			ram_addr = offs;
-			ram_wrdata = val;
-			@(posedge clk);
-			//deassert signals
-			ram_wr = 0;
-			ram_addr = 'bx;
-			ram_wrdata = 'bx;
-		end
-	endtask
-
-endmodule

Testbench/sigdel/db/prev_cmp_sigdel.qmsg

@@ -1,9 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673520674097 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 12 13:51:13 2023 " "Processing started: Thu Jan 12 13:51:13 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674097 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674098 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
-{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\[\";  expecting an operand sigdel.sv(14) " "Verilog HDL syntax error at sigdel.sv(14) near text: \"\[\";  expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." {  } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 14 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
-{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "sigdel sigdel.sv(1) " "Ignored design unit \"sigdel\" at sigdel.sv(1) due to previous errors" {  } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 0 0 } }  } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" {  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680483 ""}
-{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "923 " "Peak virtual memory: 923 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 12 13:51:20 2023 " "Processing ended: Thu Jan 12 13:51:20 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680505 ""}

Testbench/sigdel/db/sigdel.cbx.xml

@@ -1,5 +0,0 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
-	<PROJECT NAME="sigdel">
-	</PROJECT>
-</LOG_ROOT>

Testbench/sigdel/db/sigdel.db_info

@@ -1,3 +0,0 @@
-Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-Version_Index = 486699264
-Creation_Time = Mon Jan 16 21:47:58 2023

Testbench/sigdel/db/sigdel.hier_info

@@ -1,47 +0,0 @@
-|sigdel
-phinc[0] => Add0.IN14
-phinc[1] => Add0.IN13
-phinc[2] => Add0.IN12
-phinc[3] => Add0.IN11
-phinc[4] => Add0.IN10
-phinc[5] => Add0.IN9
-phinc[6] => Add0.IN8
-phinc[7] => Add0.IN7
-clk => acc[0].CLK
-clk => acc[1].CLK
-clk => acc[2].CLK
-clk => acc[3].CLK
-clk => acc[4].CLK
-clk => acc[5].CLK
-clk => acc[6].CLK
-clk => acc[7].CLK
-clk => acc[8].CLK
-clk => acc[9].CLK
-clk => acc[10].CLK
-clk => acc[11].CLK
-clk => acc[12].CLK
-clk => acc[13].CLK
-clr_n => acc[0].ACLR
-clr_n => acc[1].ACLR
-clr_n => acc[2].ACLR
-clr_n => acc[3].ACLR
-clr_n => acc[4].ACLR
-clr_n => acc[5].ACLR
-clr_n => acc[6].ACLR
-clr_n => acc[7].ACLR
-clr_n => acc[8].ACLR
-clr_n => acc[9].ACLR
-clr_n => acc[10].ACLR
-clr_n => acc[11].ACLR
-clr_n => acc[12].ACLR
-clr_n => acc[13].ACLR
-phase[0] <= acc[6].DB_MAX_OUTPUT_PORT_TYPE
-phase[1] <= acc[7].DB_MAX_OUTPUT_PORT_TYPE
-phase[2] <= acc[8].DB_MAX_OUTPUT_PORT_TYPE
-phase[3] <= acc[9].DB_MAX_OUTPUT_PORT_TYPE
-phase[4] <= acc[10].DB_MAX_OUTPUT_PORT_TYPE
-phase[5] <= acc[11].DB_MAX_OUTPUT_PORT_TYPE
-phase[6] <= acc[12].DB_MAX_OUTPUT_PORT_TYPE
-phase[7] <= acc[13].DB_MAX_OUTPUT_PORT_TYPE
-
-

Testbench/sigdel/db/sigdel.lpc.html

@@ -1,18 +0,0 @@
-<TABLE>
-<TR  bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-</TABLE>

Testbench/sigdel/db/sigdel.lpc.txt

@@ -1,5 +0,0 @@
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates                                                                                                                                                                                     ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

Testbench/sigdel/db/sigdel.map.logdb

@@ -1 +0,0 @@
-v1

Testbench/sigdel/db/sigdel.map.qmsg

@@ -1,12 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673883395012 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 16 18:36:34 2023 " "Processing started: Mon Jan 16 18:36:34 2023" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel " "Found entity 1: sigdel" {  } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sigdel_tb.sv 1 1 " "Found 1 design units, including 1 entities, in source file sigdel_tb.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel_tb " "Found entity 1: sigdel_tb" {  } { { "sigdel_tb.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Testbench/sigdel/sigdel_tb.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "sigdel " "Elaborating entity \"sigdel\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1673883401097 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1673883401388 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1673883401553 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1673883401553 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1673883401619 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1673883401619 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1047 " "Peak virtual memory: 1047 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 16 18:36:41 2023 " "Processing ended: Mon Jan 16 18:36:41 2023" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401622 ""}

Testbench/sigdel/db/sigdel.map_bb.logdb

@@ -1 +0,0 @@
-v1

Testbench/sigdel/db/sigdel.smart_action.txt

@@ -1 +0,0 @@
-FIT

Testbench/sigdel/db/sigdel_partition_pins.json

@@ -1,81 +0,0 @@
-{
-	"partitions" : [
-		{
-			"name" : "Top",
-			"pins" : [
-				{
-					"name" : "phase[0]",
-					"strict" : false
-				},
-				{
-					"name" : "phase[1]",
-					"strict" : false
-				},
-				{
-					"name" : "phase[2]",
-					"strict" : false
-				},
-				{
-					"name" : "phase[3]",
-					"strict" : false
-				},
-				{
-					"name" : "phase[4]",
-					"strict" : false
-				},
-				{
-					"name" : "phase[5]",
-					"strict" : false
-				},
-				{
-					"name" : "phase[6]",
-					"strict" : false
-				},
-				{
-					"name" : "phase[7]",
-					"strict" : false
-				},
-				{
-					"name" : "clk",
-					"strict" : false
-				},
-				{
-					"name" : "clr_n",
-					"strict" : false
-				},
-				{
-					"name" : "phinc[6]",
-					"strict" : false
-				},
-				{
-					"name" : "phinc[7]",
-					"strict" : false
-				},
-				{
-					"name" : "phinc[5]",
-					"strict" : false
-				},
-				{
-					"name" : "phinc[4]",
-					"strict" : false
-				},
-				{
-					"name" : "phinc[3]",
-					"strict" : false
-				},
-				{
-					"name" : "phinc[2]",
-					"strict" : false
-				},
-				{
-					"name" : "phinc[1]",
-					"strict" : false
-				},
-				{
-					"name" : "phinc[0]",
-					"strict" : false
-				}
-			]
-		}
-	]
-}

Testbench/sigdel/inc_lut_tb.sv

@@ -0,0 +1,47 @@
+`timescale 1 ns/1 ns
+
+module inc_lut_tb();
+
+	// Parameters
+	localparam CLK_PRD = 20;
+	localparam PHACC_WIDTH = 14;
+	
+	logic clk, clr_n, wr_n;
+	logic [7:0] phinc_val, phase, sine;
+		
+	// Instantiate UUT and connect used ports
+	phacc phacc(.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
+	defparam phacc.WIDTH = PHACC_WIDTH;
+	
+	sinelut	sinelut_inst (
+       .address (phase), .clock (clk), .q(sine)
+	);
+
+
+	// Clock definition
+	initial begin
+		clk = 0;
+		forever #(CLK_PRD/2) clk = ~clk;
+	end
+
+	// Reset and initial values definition
+	initial begin
+		clr_n = 0;
+		#(CLK_PRD*5) clr_n = 1;
+	end
+	
+	// Bus write transaction simulation
+	initial begin
+		// Wait until system is out of reset
+		@(posedge clr_n);
+		
+		phinc_val=(2**(PHACC_WIDTH - 8));
+		if ((phinc_val <= 255) && (phinc_val != 0)) begin
+          #(CLK_PRD * 256 * 5) $stop;
+		end else begin
+			$display("Error: value of phase increment is out of range! Stopped simulation.");
+			#1 $stop;
+		end
+	end
+endmodule
+

Testbench/sigdel/incremental_db/README

@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used.  To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-

Testbench/sigdel/incremental_db/compiled_partitions/sigdel.db_info

@@ -1,3 +0,0 @@
-Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-Version_Index = 486699264
-Creation_Time = Thu Jan 12 13:26:18 2023

Testbench/sigdel/incremental_db/compiled_partitions/sigdel.root_partition.map.hbdb.sig

@@ -1 +0,0 @@
-7aee213afbf8301ed5eefc8c827f49a3

Testbench/sigdel/lut_mod_tb.sv

@@ -0,0 +1,55 @@
+`timescale 1 ns/1 ns
+
+module lut_mod_tb();
+
+	// Parameters
+	localparam CLK_PRD = 20;
+	localparam PHACC_WIDTH = 14;
+	
+	logic clk, clr_n, wr_n, daco;
+	logic [7:0] phinc_val, phase, sine;
+		
+	// Instantiate UUT and connect used ports
+	phacc phacc (
+	    .phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase)
+	);
+	defparam phacc.WIDTH = PHACC_WIDTH;
+	
+	sinelut sinelut_inst (
+       .address(phase), .clock(clk), .q(sine)
+	);
+	
+	sdmod sdmod_inst (
+	    .val(sine), .clk(clk), .reset(clr_n), .daco(daco)
+//	    .val(8'd0), .clk(clk), .reset(clr_n), .daco(daco)
+//	    .val(8'd255), .clk(clk), .reset(clr_n), .daco(daco)
+	);
+
+
+	// Clock definition
+	initial begin
+		clk = 0;
+		forever #(CLK_PRD/2) clk = ~clk;
+	end
+
+	// Reset and initial values definition
+	initial begin
+		clr_n = 0;
+		#(CLK_PRD*5) clr_n = 1;
+	end
+	
+	// Bus write transaction simulation
+	initial begin
+		// Wait until system is out of reset
+		@(posedge clr_n);
+		
+		phinc_val=(2**(PHACC_WIDTH - 8));
+		if ((phinc_val <= 255) && (phinc_val != 0)) begin
+          #(CLK_PRD * 256 * 10) $stop;
+		end else begin
+			$display("Error: value of phase increment is out of range! Stopped simulation.");
+			#1 $stop;
+		end
+	end
+endmodule
+

Testbench/sigdel/sigdel.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 10:16:23  January 27, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "10:16:23  January 27, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "sigdel"

Testbench/sigdel/sigdel.qsf

@@ -0,0 +1,79 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
+# Date created = 10:16:23  January 27, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		sigdel_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE15F23C8
+set_global_assignment -name TOP_LEVEL_ENTITY sigdel
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:16:23  JANUARY 27, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH sigdel_tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME inc_lut_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id inc_lut_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME inc_lut_tb -section_id inc_lut_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME lut_mod_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id lut_mod_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME lut_mod_tb -section_id lut_mod_tb
+set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/phacc.sv
+set_global_assignment -name QIP_FILE ../../HDL/IP/sinelut.qip
+set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sigdel.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sdmod.sv
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_FILE inc_lut_tb.sv -section_id inc_lut_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE lut_mod_tb.sv -section_id lut_mod_tb
+set_global_assignment -name EDA_TEST_BENCH_NAME sigdel_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sigdel_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sigdel_tb -section_id sigdel_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE sigdel_tb.sv -section_id sigdel_tb
+set_location_assignment PIN_T2 -to clk
+set_location_assignment PIN_E4 -to clr_n
+set_location_assignment PIN_E3 -to fout
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Testbench/sigdel/sigdel.sv

@@ -0,0 +1,37 @@
+//top-level module
+module sigdel
+#(
+    PHACC_WIDTH = 14
+) (
+	//clock and reset
+	input logic clk, clr_n,
+	//control slave
+	input logic [31:0] wr_data,
+	input logic wr_n,
+	output logic fout
+);
+
+	logic [7:0] phinc_val;
+	
+	//control slave logic
+	always_ff @ (posedge clk or negedge clr_n) begin
+		if (!clr_n) begin
+			phinc_val[7:0] <= 8'd0;
+		end else	begin
+			if (!wr_n) begin
+				phinc_val[7:0] <= wr_data[31:0];
+			end
+		end
+	end
+
+	phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
+	defparam phacc_inst.WIDTH = PHACC_WIDTH;
+	
+	sinelut sinelut_inst (
+       .address (phase), .clock (clk), .q(sine)
+	);
+	
+	sdmod sdmod_inst (
+	    .val(sine), .clk(clk), .reset(clr_n), .daco(fout)
+	);
+endmodule

Testbench/sigdel/sigdel_tb.sv

@@ -0,0 +1,81 @@
+`timescale 1 ns/1 ns
+
+module sigdel_tb();
+
+	// Parameters
+	localparam CLK_PRD = 20;
+	localparam SAMPLES_PRD = 256;
+	localparam OVERSAMPLING = 4;
+	localparam PHACC_WIDTH = 14;
+	
+	// Wires and variables to connect to UUT (unit under test)
+	logic clk, clr_n, wr_n;
+	logic [31:0] wr_data;
+	logic [31:0] phinc_val;
+	logic fout;
+		
+	// Instantiate UUT and connect used ports
+	sigdel dut(.clk(clk), .clr_n(clr_n), .wr_n(wr_n), .wr_data(wr_data), .fout(fout));
+	defparam dut.PHACC_WIDTH = PHACC_WIDTH;
+
+	// Clock definition
+	initial begin
+		clk = 0;
+		forever #(CLK_PRD/2) clk = ~clk;
+	end
+
+	// Reset and initial values definition
+	initial begin
+		clr_n = 0;
+		wr_n = 1;
+		wr_data = 'bx;
+		#(CLK_PRD*5) clr_n = 1;
+	end
+	
+	// Bus write transaction simulation
+	initial begin
+		// Wait until system is out of reset
+		@(posedge clr_n);
+		// Check if phase increment for required accumulator width 
+		// and oversamlpling ratio will fit in 8 bits
+		phinc_val=(2**(PHACC_WIDTH-8))/OVERSAMPLING;
+		if ((phinc_val <= 255) && (phinc_val != 0))
+		begin
+			// Write phase increment several clock cycles after reset
+			#(CLK_PRD*3) write_transaction(phinc_val);
+			// Wait for one sine period (for 14-bit phase accumulator case)
+			#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
+
+			#(CLK_PRD*3) write_transaction(phinc_val*5);
+
+			#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
+			$stop;
+		end
+		else
+		begin
+			//Output simulation error
+			$display("Error: value of phase increment is out of range! Stopped simulation.");
+			//Stop simulation (small delay needed for $display to work)
+			#1 $stop;
+		end
+	end
+
+	//Single write transaction task
+	task write_transaction;
+		//input signals
+		input [31:0] val;
+		//transaction implementation
+		begin
+			@(posedge clk);
+			//assert signals for one clock cycle
+			wr_n = 0;
+			wr_data = val;
+			@(posedge clk);
+			//deassert signals
+			wr_n = 1;
+			wr_data = 'bx;
+		end
+	endtask
+
+endmodule
+

Testbench/sigdel/sine256.mif

@@ -0,0 +1,242 @@
+WIDTH = 8;
+DEPTH = 256;
+
+ADDRESS_RADIX = DEC;
+DATA_RADIX = HEX;
+
+CONTENT BEGIN
+	0 : 02;
+	1 : 05;
+	2 : 08;
+	3 : 0B;
+	4 : 0E;
+	5 : 11;
+	6 : 14;
+	7 : 17;
+	8 : 1A;
+	9 : 1D;
+	10 : 20;
+	11 : 23;
+	12 : 26;
+	13 : 29;
+	14 : 2C;
+	15 : 2F;
+	16 : 32;
+	17 : 35;
+	18 : 38;
+	19 : 3A;
+	20 : 3D;
+	21 : 40;
+	22 : 43;
+	23 : 45;
+	24 : 48;
+	25 : 4A;
+	26 : 4D;
+	27 : 4F;
+	28 : 52;
+	29 : 54;
+	30 : 56;
+	31 : 59;
+	32 : 5B;
+	33 : 5D;
+	34 : 5F;
+	35 : 61;
+	36 : 63;
+	37 : 65;
+	38 : 67;
+	39 : 69;
+	40 : 6A;
+	41 : 6C;
+	42 : 6E;
+	43 : 6F;
+	44 : 71;
+	45 : 72;
+	46 : 73;
+	47 : 75;
+	48 : 76;
+	49 : 77;
+	50 : 78;
+	51 : 79;
+	52 : 7A;
+	53 : 7B;
+	54 : 7C;
+	55 : 7C;
+	56 : 7D;
+	57 : 7D;
+	[58..69] : 7E;
+	70 : 7D;
+	71 : 7D;
+	72 : 7C;
+	73 : 7C;
+	74 : 7B;
+	75 : 7A;
+	76 : 79;
+	77 : 78;
+	78 : 77;
+	79 : 76;
+	80 : 75;
+	81 : 73;
+	82 : 72;
+	83 : 71;
+	84 : 6F;
+	85 : 6E;
+	86 : 6C;
+	87 : 6A;
+	88 : 69;
+	89 : 67;
+	90 : 65;
+	91 : 63;
+	92 : 61;
+	93 : 5F;
+	94 : 5D;
+	95 : 5B;
+	96 : 59;
+	97 : 56;
+	98 : 54;
+	99 : 52;
+	100 : 4F;
+	101 : 4D;
+	102 : 4A;
+	103 : 48;
+	104 : 45;
+	105 : 43;
+	106 : 40;
+	107 : 3D;
+	108 : 3A;
+	109 : 38;
+	110 : 35;
+	111 : 32;
+	112 : 2F;
+	113 : 2C;
+	114 : 29;
+	115 : 26;
+	116 : 23;
+	117 : 20;
+	118 : 1D;
+	119 : 1A;
+	120 : 17;
+	121 : 14;
+	122 : 11;
+	123 : 0E;
+	124 : 0B;
+	125 : 08;
+	126 : 05;
+	127 : 02;
+	128 : FE;
+	129 : FB;
+	130 : F8;
+	131 : F5;
+	132 : F2;
+	133 : EF;
+	134 : EC;
+	135 : E9;
+	136 : E6;
+	137 : E3;
+	138 : E0;
+	139 : DD;
+	140 : DA;
+	141 : D7;
+	142 : D4;
+	143 : D1;
+	144 : CE;
+	145 : CB;
+	146 : C8;
+	147 : C6;
+	148 : C3;
+	149 : C0;
+	150 : BD;
+	151 : BB;
+	152 : B8;
+	153 : B6;
+	154 : B3;
+	155 : B1;
+	156 : AE;
+	157 : AC;
+	158 : AA;
+	159 : A7;
+	160 : A5;
+	161 : A3;
+	162 : A1;
+	163 : 9F;
+	164 : 9D;
+	165 : 9B;
+	166 : 99;
+	167 : 97;
+	168 : 96;
+	169 : 94;
+	170 : 92;
+	171 : 91;
+	172 : 8F;
+	173 : 8E;
+	174 : 8D;
+	175 : 8B;
+	176 : 8A;
+	177 : 89;
+	178 : 88;
+	179 : 87;
+	180 : 86;
+	181 : 85;
+	182 : 84;
+	183 : 84;
+	184 : 83;
+	185 : 83;
+	[186..197] : 82;
+	198 : 83;
+	199 : 83;
+	200 : 84;
+	201 : 84;
+	202 : 85;
+	203 : 86;
+	204 : 87;
+	205 : 88;
+	206 : 89;
+	207 : 8A;
+	208 : 8B;
+	209 : 8D;
+	210 : 8E;
+	211 : 8F;
+	212 : 91;
+	213 : 92;
+	214 : 94;
+	215 : 96;
+	216 : 97;
+	217 : 99;
+	218 : 9B;
+	219 : 9D;
+	220 : 9F;
+	221 : A1;
+	222 : A3;
+	223 : A5;
+	224 : A7;
+	225 : AA;
+	226 : AC;
+	227 : AE;
+	228 : B1;
+	229 : B3;
+	230 : B6;
+	231 : B8;
+	232 : BB;
+	233 : BD;
+	234 : C0;
+	235 : C3;
+	236 : C6;
+	237 : C8;
+	238 : CB;
+	239 : CE;
+	240 : D1;
+	241 : D4;
+	242 : D7;
+	243 : DA;
+	244 : DD;
+	245 : E0;
+	246 : E3;
+	247 : E6;
+	248 : E9;
+	249 : EC;
+	250 : EF;
+	251 : F2;
+	252 : F5;
+	253 : F8;
+	254 : FB;
+	255 : FE;
+END;

Top/#niosII_tb.csv#

@@ -1,151 +0,0 @@
-# system info niosII_tb on 2022.10.24.18:26:01
-system_info:
-name,value
-DEVICE,EP4CE115F29C7
-DEVICE_FAMILY,Cyclone IV E
-GENERATION_ID,1666621532
-#
-#
-# Files generated for niosII_tb on 2022.10.24.18:26:01
-files:
-filepath,kind,attributes,module,is_top
-niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
-niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
-niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
-niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
-niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
-niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_001,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_002,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_004,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_008,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux_001,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_demux,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
-#
-# Map from instance-path to kind of module
-instances:
-instancePath,module
-niosII_tb.niosII_inst,niosII
-niosII_tb.niosII_inst.cpu,niosII_cpu
-niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
-niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
-niosII_tb.niosII_inst.mem,niosII_mem
-niosII_tb.niosII_inst.sem,dec
-niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
-niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
-niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
-niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.router,niosII_mm_interconnect_0_router
-niosII_tb.niosII_inst.mm_interconnect_0.router_001,niosII_mm_interconnect_0_router_001
-niosII_tb.niosII_inst.mm_interconnect_0.router_002,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_003,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_005,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_006,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_007,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_004,niosII_mm_interconnect_0_router_004
-niosII_tb.niosII_inst.mm_interconnect_0.router_008,niosII_mm_interconnect_0_router_008
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux,niosII_mm_interconnect_0_cmd_demux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux_001,niosII_mm_interconnect_0_cmd_demux_001
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_002,niosII_mm_interconnect_0_cmd_demux_001
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_001,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_003,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_004,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_005,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_006,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_002,niosII_mm_interconnect_0_cmd_mux_002
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_001,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_003,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_004,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_005,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_006,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux,niosII_mm_interconnect_0_rsp_mux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux_001,niosII_mm_interconnect_0_rsp_mux_001
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-                                                                niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
-niosII_tb.niosII_inst.rst_controller,altera_reset_controller
-niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
-niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source

Top/niosII.qsys

@@ -29,7 +29,7 @@
    {
       datum baseAddress
       {
-         value = "133120";
+         value = "34816";
          type = "String";
       }
    }
@@ -45,7 +45,7 @@
    {
       datum baseAddress
       {
-         value = "135272";
+         value = "36896";
          type = "String";
       }
    }
@@ -105,7 +105,15 @@
          type = "String";
       }
    }
-   element sem
+   element niosII
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Cyclone IV E";
+         type = "String";
+      }
+   }
+   element sigdel_0
    {
       datum _sortIndex
       {
@@ -113,19 +121,11 @@
          type = "int";
       }
    }
-   element sem.ctl_slave
+   element sigdel_0.avalon_slave
    {
       datum baseAddress
       {
-         value = "135264";
+         value = "36904";
-         type = "String";
-      }
-   }
-   element sem.ram_slave
-   {
-      datum baseAddress
-      {
-         value = "135168";
          type = "String";
       }
    }
@@ -141,16 +141,16 @@
    {
       datum baseAddress
       {
-         value = "135232";
+         value = "36864";
          type = "String";
       }
    }
 }
 ]]></parameter>
  <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="EP4CE115F29C7" />
+ <parameter name="device" value="EP4CE15F23C8" />
  <parameter name="deviceFamily" value="Cyclone IV E" />
- <parameter name="deviceSpeedGrade" value="7" />
+ <parameter name="deviceSpeedGrade" value="8" />
  <parameter name="fabricMode" value="QSYS" />
  <parameter name="generateLegacySim" value="false" />
  <parameter name="generationId" value="0" />
@@ -167,8 +167,12 @@
  <parameter name="useTestBenchNamingPattern" value="false" />
  <instanceScript></instanceScript>
  <interface name="clk" internal="clk.clk_in" type="clock" dir="end" />
+ <interface
+   name="conduit_end"
+   internal="sigdel_0.conduit_end"
+   type="conduit"
+   dir="end" />
  <interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end" />
- <interface name="sem_export" internal="sem.sem" type="conduit" dir="end" />
  <module name="clk" kind="clock_source" version="18.1" enabled="1">
   <parameter name="clockFrequency" value="50000000" />
   <parameter name="clockFrequencyKnown" value="true" />
@@ -178,8 +182,8 @@
  <module name="cpu" kind="altera_nios2_gen2" version="18.1" enabled="1">
   <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
   <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
-  <parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
+  <parameter name="AUTO_DEVICE" value="EP4CE15F23C8" />
-  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
   <parameter name="bht_ramBlockType" value="Automatic" />
   <parameter name="breakOffset" value="32" />
   <parameter name="breakSlave" value="None" />
@@ -192,10 +196,10 @@
   <parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
   <parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
   <parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
-  <parameter name="dataAddrWidth" value="18" />
+  <parameter name="dataAddrWidth" value="16" />
   <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
   <parameter name="dataMasterHighPerformanceMapParam" value="" />
-  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /><slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /><slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
+  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /></address-map>]]></parameter>
   <parameter name="data_master_high_performance_paddr_base" value="0" />
   <parameter name="data_master_high_performance_paddr_size" value="0" />
   <parameter name="data_master_paddr_base" value="0" />
@@ -233,8 +237,8 @@
   <parameter name="icache_size" value="4096" />
   <parameter name="icache_tagramBlockType" value="Automatic" />
   <parameter name="impl" value="Tiny" />
-  <parameter name="instAddrWidth" value="18" />
+  <parameter name="instAddrWidth" value="16" />
-  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
+  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
   <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
   <parameter name="instructionMasterHighPerformanceMapParam" value="" />
   <parameter name="instruction_master_high_performance_paddr_base" value="0" />
@@ -392,7 +396,7 @@
   <parameter name="initMemContent" value="true" />
   <parameter name="initializationFileName" value="onchip_mem.hex" />
   <parameter name="instanceID" value="NONE" />
-  <parameter name="memorySize" value="131072" />
+  <parameter name="memorySize" value="32768" />
   <parameter name="readDuringWriteMode" value="DONT_CARE" />
   <parameter name="resetrequest_enabled" value="true" />
   <parameter name="simAllowMRAMContentsFile" value="false" />
@@ -404,8 +408,8 @@
   <parameter name="useShallowMemBlocks" value="false" />
   <parameter name="writable" value="true" />
  </module>
- <module name="sem" kind="sem" version="1.1" enabled="1">
+ <module name="sigdel_0" kind="sigdel" version="1.0" enabled="1">
-  <parameter name="m" value="32" />
+  <parameter name="PHACC_WIDTH" value="26" />
  </module>
  <module
    name="sys_clk_timer"
@@ -429,16 +433,16 @@
    start="cpu.data_master"
    end="jtag_uart.avalon_jtag_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00021068" />
+  <parameter name="baseAddress" value="0x9020" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="18.1"
    start="cpu.data_master"
-   end="sem.ctl_slave">
+   end="sigdel_0.avalon_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00021060" />
+  <parameter name="baseAddress" value="0x9028" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -447,16 +451,7 @@
    start="cpu.data_master"
    end="cpu.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020800" />
+  <parameter name="baseAddress" value="0x8800" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="18.1"
-   start="cpu.data_master"
-   end="sem.ram_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00021000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -465,7 +460,7 @@
    start="cpu.data_master"
    end="sys_clk_timer.s1">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00021040" />
+  <parameter name="baseAddress" value="0x9000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2">
@@ -479,7 +474,7 @@
    start="cpu.instruction_master"
    end="cpu.debug_mem_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00020800" />
+  <parameter name="baseAddress" value="0x8800" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
@@ -495,7 +490,7 @@
  <connection kind="clock" version="18.1" start="clk.clk" end="jtag_uart.clk" />
  <connection kind="clock" version="18.1" start="clk.clk" end="sys_clk_timer.clk" />
  <connection kind="clock" version="18.1" start="clk.clk" end="mem.clk1" />
- <connection kind="clock" version="18.1" start="clk.clk" end="sem.clock" />
+ <connection kind="clock" version="18.1" start="clk.clk" end="sigdel_0.clock" />
  <connection
    kind="interrupt"
    version="18.1"
@@ -518,7 +513,11 @@
    start="clk.clk_reset"
    end="sys_clk_timer.reset" />
  <connection kind="reset" version="18.1" start="clk.clk_reset" end="mem.reset1" />
- <connection kind="reset" version="18.1" start="clk.clk_reset" end="sem.reset_n" />
+ <connection
+   kind="reset"
+   version="18.1"
+   start="clk.clk_reset"
+   end="sigdel_0.reset_sink" />
  <connection
    kind="reset"
    version="18.1"
@@ -543,7 +542,7 @@
    kind="reset"
    version="18.1"
    start="cpu.debug_reset_request"
-   end="sem.reset_n" />
+   end="sigdel_0.reset_sink" />
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
  <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
  <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />

Top/niosII/niosII.bsf

@@ -20,75 +20,51 @@ refer to the applicable agreement for further details.
 */
 (header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 288 232)
+	(rect 0 0 496 184)
-	(text "niosII" (rect 130 -1 150 11)(font "Arial" (font_size 10)))
+	(text "niosII" (rect 234 -1 254 11)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 216 20 228)(font "Arial" ))
+	(text "inst" (rect 8 168 20 180)(font "Arial" ))
 	(port
 		(pt 0 72)
 		(input)
 		(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
 		(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
-		(line (pt 0 72)(pt 112 72)(line_width 1))
+		(line (pt 0 72)(pt 192 72)(line_width 1))
-	)
-	(port
-		(pt 0 112)
-		(input)
-		(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
-		(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
-		(line (pt 0 112)(pt 112 112)(line_width 1))
 	)
 	(port
 		(pt 0 152)
 		(input)
-		(text "sem_export_train" (rect 0 0 70 12)(font "Arial" (font_size 8)))
+		(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
-		(text "sem_export_train" (rect 4 141 100 152)(font "Arial" (font_size 8)))
+		(text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8)))
-		(line (pt 0 152)(pt 112 152)(line_width 1))
+		(line (pt 0 152)(pt 192 152)(line_width 1))
 	)
 	(port
-		(pt 0 168)
+		(pt 0 112)
 		(output)
-		(text "sem_export_red" (rect 0 0 67 12)(font "Arial" (font_size 8)))
+		(text "conduit_end_writeresponsevalid_n" (rect 0 0 135 12)(font "Arial" (font_size 8)))
-		(text "sem_export_red" (rect 4 157 88 168)(font "Arial" (font_size 8)))
+		(text "conduit_end_writeresponsevalid_n" (rect 4 101 196 112)(font "Arial" (font_size 8)))
-		(line (pt 0 168)(pt 112 168)(line_width 1))
+		(line (pt 0 112)(pt 192 112)(line_width 1))
-	)
-	(port
-		(pt 0 184)
-		(output)
-		(text "sem_export_yellow" (rect 0 0 77 12)(font "Arial" (font_size 8)))
-		(text "sem_export_yellow" (rect 4 173 106 184)(font "Arial" (font_size 8)))
-		(line (pt 0 184)(pt 112 184)(line_width 1))
-	)
-	(port
-		(pt 0 200)
-		(output)
-		(text "sem_export_green" (rect 0 0 76 12)(font "Arial" (font_size 8)))
-		(text "sem_export_green" (rect 4 189 100 200)(font "Arial" (font_size 8)))
-		(line (pt 0 200)(pt 112 200)(line_width 1))
 	)
 	(drawing
-		(text "clk" (rect 97 43 212 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "clk" (rect 117 67 252 144)(font "Arial" (color 0 0 0)))
+		(text "clk" (rect 197 67 412 144)(font "Arial" (color 0 0 0)))
-		(text "reset" (rect 83 83 196 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "conduit_end" (rect 123 83 312 179)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "reset_n" (rect 117 107 276 224)(font "Arial" (color 0 0 0)))
+		(text "writeresponsevalid_n" (rect 197 107 514 224)(font "Arial" (color 0 0 0)))
-		(text "sem_export" (rect 44 123 148 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 163 123 356 259)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "train" (rect 117 147 264 304)(font "Arial" (color 0 0 0)))
+		(text "reset_n" (rect 197 147 436 304)(font "Arial" (color 0 0 0)))
-		(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
+		(text " niosII " (rect 470 168 988 346)(font "Arial" ))
-		(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
+		(line (pt 192 32)(pt 304 32)(line_width 1))
-		(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
+		(line (pt 304 32)(pt 304 168)(line_width 1))
-		(text " niosII " (rect 262 216 572 442)(font "Arial" ))
+		(line (pt 192 168)(pt 304 168)(line_width 1))
-		(line (pt 112 32)(pt 176 32)(line_width 1))
+		(line (pt 192 32)(pt 192 168)(line_width 1))
-		(line (pt 176 32)(pt 176 216)(line_width 1))
+		(line (pt 193 52)(pt 193 76)(line_width 1))
-		(line (pt 112 216)(pt 176 216)(line_width 1))
+		(line (pt 194 52)(pt 194 76)(line_width 1))
-		(line (pt 112 32)(pt 112 216)(line_width 1))
+		(line (pt 193 92)(pt 193 116)(line_width 1))
-		(line (pt 113 52)(pt 113 76)(line_width 1))
+		(line (pt 194 92)(pt 194 116)(line_width 1))
-		(line (pt 114 52)(pt 114 76)(line_width 1))
+		(line (pt 193 132)(pt 193 156)(line_width 1))
-		(line (pt 113 92)(pt 113 116)(line_width 1))
+		(line (pt 194 132)(pt 194 156)(line_width 1))
-		(line (pt 114 92)(pt 114 116)(line_width 1))
+		(line (pt 0 0)(pt 496 0)(line_width 1))
-		(line (pt 113 132)(pt 113 204)(line_width 1))
+		(line (pt 496 0)(pt 496 184)(line_width 1))
-		(line (pt 114 132)(pt 114 204)(line_width 1))
+		(line (pt 0 184)(pt 496 184)(line_width 1))
-		(line (pt 0 0)(pt 288 0)(line_width 1))
+		(line (pt 0 0)(pt 0 184)(line_width 1))
-		(line (pt 288 0)(pt 288 232)(line_width 1))
-		(line (pt 0 232)(pt 288 232)(line_width 1))
-		(line (pt 0 0)(pt 0 232)(line_width 1))
 	)
 )

Top/niosII/niosII.cmp

@@ -1,11 +1,8 @@
 	component niosII is
 		port (
 			clk_clk                          : in  std_logic := 'X'; -- clk
-			reset_reset_n     : in  std_logic := 'X'; -- reset_n
+			conduit_end_writeresponsevalid_n : out std_logic;        -- writeresponsevalid_n
-			sem_export_train  : in  std_logic := 'X'; -- train
+			reset_reset_n                    : in  std_logic := 'X'  -- reset_n
-			sem_export_red    : out std_logic;        -- red
-			sem_export_yellow : out std_logic;        -- yellow
-			sem_export_green  : out std_logic         -- green
 		);
 	end component niosII;
 

Top/niosII/niosII.html

@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2023.01.17.19:00:54</td>
+    <td class="l">2023.02.07.17:03:00</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -100,8 +100,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
      <a href="#module_mem"><b>mem</b>
      </a> altera_avalon_onchip_memory2 18.1
      <br/>&#160;&#160;
-     <a href="#module_sem"><b>sem</b>
+     <a href="#module_sigdel_0"><b>sigdel_0</b>
-     </a> sem 1.1
+     </a> sigdel 1.0
      <br/>&#160;&#160;
      <a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
      </a> altera_avalon_timer 18.1</span>
@@ -131,8 +131,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slaveb">debug_mem_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00020800</td>
+    <td class="addr"><span style="color:#989898">0x</span>00008800</td>
-    <td class="addr"><span style="color:#989898">0x</span>00020800</td>
+    <td class="addr"><span style="color:#989898">0x</span>00008800</td>
    </tr>
    <tr>
     <td class="slavemodule">&#160;
@@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slaveb">avalon_jtag_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021068</td>
+    <td class="addr"><span style="color:#989898">0x</span>00009020</td>
     <td class="empty"></td>
    </tr>
    <tr>
@@ -167,20 +167,15 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slavemodule">&#160;
-     <a href="#module_sem"><b>sem</b>
+     <a href="#module_sigdel_0"><b>sigdel_0</b>
      </a>
     </td>
     <td class="empty"></td>
     <td class="empty"></td>
    </tr>
    <tr>
-    <td class="slavem">ctl_slave&#160;</td>
+    <td class="slaveb">avalon_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021060</td>
+    <td class="addr"><span style="color:#989898">0x</span>00009028</td>
-    <td class="empty"></td>
-   </tr>
-   <tr>
-    <td class="slavem">ram_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021000</td>
     <td class="empty"></td>
    </tr>
    <tr>
@@ -193,7 +188,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slaveb">s1&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021040</td>
+    <td class="addr"><span style="color:#989898">0x</span>00009000</td>
     <td class="empty"></td>
    </tr>
   </table>
@@ -256,7 +251,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        <a href="#module_clk">clk</a>
       </td>
       <td class="from">clk&#160;&#160;</td>
-      <td class="main" rowspan="31">cpu</td>
+      <td class="main" rowspan="29">cpu</td>
      </tr>
      <tr>
       <td class="to">&#160;&#160;clk</td>
@@ -307,24 +302,14 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <td></td>
       <td></td>
       <td class="from">data_master&#160;&#160;</td>
-      <td class="neighbor" rowspan="6">
+      <td class="neighbor" rowspan="4">
-       <a href="#module_sem">sem</a>
+       <a href="#module_sigdel_0">sigdel_0</a>
       </td>
      </tr>
      <tr>
       <td></td>
       <td></td>
-      <td class="to">&#160;&#160;ctl_slave</td>
+      <td class="to">&#160;&#160;avalon_slave</td>
-     </tr>
-     <tr>
-      <td></td>
-      <td></td>
-      <td class="from">data_master&#160;&#160;</td>
-     </tr>
-     <tr>
-      <td></td>
-      <td></td>
-      <td class="to">&#160;&#160;ram_slave</td>
      </tr>
      <tr>
       <td></td>
@@ -334,7 +319,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
      <tr>
       <td></td>
       <td></td>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
      <tr style="height:6px">
       <td></td>
@@ -991,7 +976,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">breakAbsoluteAddr</td>
-        <td class="parametervalue">133152</td>
+        <td class="parametervalue">34848</td>
        </tr>
        <tr>
         <td class="parametername">mmu_TLBMissExcAbsAddr</td>
@@ -1047,7 +1032,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">instAddrWidth</td>
-        <td class="parametervalue">18</td>
+        <td class="parametervalue">16</td>
        </tr>
        <tr>
         <td class="parametername">faAddrWidth</td>
@@ -1055,7 +1040,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">dataAddrWidth</td>
-        <td class="parametervalue">18</td>
+        <td class="parametervalue">16</td>
        </tr>
        <tr>
         <td class="parametername">tightlyCoupledDataMaster0AddrWidth</td>
@@ -1099,7 +1084,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">instSlaveMapParam</td>
-        <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td>
+        <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td>
        </tr>
        <tr>
         <td class="parametername">faSlaveMapParam</td>
@@ -1107,7 +1092,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">dataSlaveMapParam</td>
-        <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
+        <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /&gt;&lt;/address-map&gt;</td>
        </tr>
        <tr>
         <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@@ -1183,11 +1168,11 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">AUTO_DEVICE</td>
-        <td class="parametervalue">EP4CE115F29C7</td>
+        <td class="parametervalue">EP4CE15F23C8</td>
        </tr>
        <tr>
         <td class="parametername">AUTO_DEVICE_SPEEDGRADE</td>
-        <td class="parametervalue">7</td>
+        <td class="parametervalue">8</td>
        </tr>
        <tr>
         <td class="parametername">AUTO_CLK_CLOCK_DOMAIN</td>
@@ -1220,7 +1205,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">BREAK_ADDR</td>
-        <td class="parametervalue">0x00020820</td>
+        <td class="parametervalue">0x00008820</td>
        </tr>
        <tr>
         <td class="parametername">CPU_ARCH_NIOS2_R1</td>
@@ -1244,7 +1229,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">DATA_ADDR_WIDTH</td>
-        <td class="parametervalue">18</td>
+        <td class="parametervalue">16</td>
        </tr>
        <tr>
         <td class="parametername">DCACHE_LINE_SIZE</td>
@@ -1316,7 +1301,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">INST_ADDR_WIDTH</td>
-        <td class="parametervalue">18</td>
+        <td class="parametervalue">16</td>
        </tr>
        <tr>
         <td class="parametername">OCI_VERSION</td>
@@ -1591,7 +1576,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">memorySize</td>
-        <td class="parametervalue">131072</td>
+        <td class="parametervalue">32768</td>
        </tr>
        <tr>
         <td class="parametername">readDuringWriteMode</td>
@@ -1659,11 +1644,11 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">derived_set_addr_width</td>
-        <td class="parametervalue">15</td>
+        <td class="parametervalue">13</td>
        </tr>
        <tr>
         <td class="parametername">derived_set_addr_width2</td>
-        <td class="parametervalue">15</td>
+        <td class="parametervalue">13</td>
        </tr>
        <tr>
         <td class="parametername">derived_set_data_width</td>
@@ -1752,7 +1737,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">SIZE_VALUE</td>
-        <td class="parametervalue">131072</td>
+        <td class="parametervalue">32768</td>
        </tr>
        <tr>
         <td class="parametername">WRITABLE</td>
@@ -1763,34 +1748,28 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
     </tr>
    </table>
   </div>
-  <a name="module_sem"> </a>
+  <a name="module_sigdel_0"> </a>
   <div>
    <hr/>
-   <h2>sem</h2>sem v1.1
+   <h2>sigdel_0</h2>sigdel v1.0
    <br/>
    <div class="greydiv">
     <table class="connectionboxes">
      <tr>
-      <td class="neighbor" rowspan="6">
+      <td class="neighbor" rowspan="4">
        <a href="#module_cpu">cpu</a>
       </td>
       <td class="from">data_master&#160;&#160;</td>
-      <td class="main" rowspan="11">sem</td>
+      <td class="main" rowspan="9">sigdel_0</td>
      </tr>
      <tr>
-      <td class="to">&#160;&#160;ctl_slave</td>
+      <td class="to">&#160;&#160;avalon_slave</td>
-     </tr>
-     <tr>
-      <td class="from">data_master&#160;&#160;</td>
-     </tr>
-     <tr>
-      <td class="to">&#160;&#160;ram_slave</td>
      </tr>
      <tr>
       <td class="from">debug_reset_request&#160;&#160;</td>
      </tr>
      <tr>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
      <tr style="height:6px">
       <td></td>
@@ -1808,7 +1787,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <td class="from">clk_reset&#160;&#160;</td>
      </tr>
      <tr>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
     </table>
    </div>
@@ -1820,8 +1799,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <h2>Parameters</h2>
       <table>
        <tr>
-        <td class="parametername">m</td>
+        <td class="parametername">PHACC_WIDTH</td>
-        <td class="parametervalue">32</td>
+        <td class="parametervalue">26</td>
        </tr>
        <tr>
         <td class="parametername">deviceFamily</td>
@@ -2039,7 +2018,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   <table class="blueBar">
    <tr>
     <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0.02 seconds</td>
+    <td class="r">rendering took 0.03 seconds</td>
    </tr>
   </table>
  </body>

Top/niosII/niosII_bb.v

@@ -1,16 +1,10 @@
 
 module niosII (
 	clk_clk,
-	reset_reset_n,
+	conduit_end_writeresponsevalid_n,
-	sem_export_train,
+	reset_reset_n);	
-	sem_export_red,
-	sem_export_yellow,
-	sem_export_green);	
 
 	input		clk_clk;
+	output		conduit_end_writeresponsevalid_n;
 	input		reset_reset_n;
-	input		sem_export_train;
-	output		sem_export_red;
-	output		sem_export_yellow;
-	output		sem_export_green;
 endmodule

Top/niosII/niosII_inst.v

@@ -1,9 +1,6 @@
 	niosII u0 (
 		.clk_clk                          (<connected-to-clk_clk>),                          //         clk.clk
-		.reset_reset_n     (<connected-to-reset_reset_n>),     //      reset.reset_n
+		.conduit_end_writeresponsevalid_n (<connected-to-conduit_end_writeresponsevalid_n>), // conduit_end.writeresponsevalid_n
-		.sem_export_train  (<connected-to-sem_export_train>),  // sem_export.train
+		.reset_reset_n                    (<connected-to-reset_reset_n>)                     //       reset.reset_n
-		.sem_export_red    (<connected-to-sem_export_red>),    //           .red
-		.sem_export_yellow (<connected-to-sem_export_yellow>), //           .yellow
-		.sem_export_green  (<connected-to-sem_export_green>)   //           .green
 	);
 

Top/niosII/niosII_inst.vhd

@@ -1,21 +1,15 @@
 	component niosII is
 		port (
 			clk_clk                          : in  std_logic := 'X'; -- clk
-			reset_reset_n     : in  std_logic := 'X'; -- reset_n
+			conduit_end_writeresponsevalid_n : out std_logic;        -- writeresponsevalid_n
-			sem_export_train  : in  std_logic := 'X'; -- train
+			reset_reset_n                    : in  std_logic := 'X'  -- reset_n
-			sem_export_red    : out std_logic;        -- red
-			sem_export_yellow : out std_logic;        -- yellow
-			sem_export_green  : out std_logic         -- green
 		);
 	end component niosII;
 
 	u0 : component niosII
 		port map (
 			clk_clk                          => CONNECTED_TO_clk_clk,                          --         clk.clk
-			reset_reset_n     => CONNECTED_TO_reset_reset_n,     --      reset.reset_n
+			conduit_end_writeresponsevalid_n => CONNECTED_TO_conduit_end_writeresponsevalid_n, -- conduit_end.writeresponsevalid_n
-			sem_export_train  => CONNECTED_TO_sem_export_train,  -- sem_export.train
+			reset_reset_n                    => CONNECTED_TO_reset_reset_n                     --       reset.reset_n
-			sem_export_red    => CONNECTED_TO_sem_export_red,    --           .red
-			sem_export_yellow => CONNECTED_TO_sem_export_yellow, --           .yellow
-			sem_export_green  => CONNECTED_TO_sem_export_green   --           .green
 		);
 

Top/niosII/synthesis/niosII.v

@@ -5,24 +5,21 @@
 `timescale 1 ps / 1 ps
 module niosII (
 		input  wire  clk_clk,                          //         clk.clk
-		input  wire  reset_reset_n,     //      reset.reset_n
+		output wire  conduit_end_writeresponsevalid_n, // conduit_end.writeresponsevalid_n
-		input  wire  sem_export_train,  // sem_export.train
+		input  wire  reset_reset_n                     //       reset.reset_n
-		output wire  sem_export_red,    //           .red
-		output wire  sem_export_yellow, //           .yellow
-		output wire  sem_export_green   //           .green
 	);
 
 	wire  [31:0] cpu_data_master_readdata;                                  // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
 	wire         cpu_data_master_waitrequest;                               // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
 	wire         cpu_data_master_debugaccess;                               // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
-	wire  [17:0] cpu_data_master_address;                                   // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
+	wire  [15:0] cpu_data_master_address;                                   // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
 	wire   [3:0] cpu_data_master_byteenable;                                // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
 	wire         cpu_data_master_read;                                      // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
 	wire         cpu_data_master_write;                                     // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
 	wire  [31:0] cpu_data_master_writedata;                                 // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
 	wire  [31:0] cpu_instruction_master_readdata;                           // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
 	wire         cpu_instruction_master_waitrequest;                        // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
-	wire  [17:0] cpu_instruction_master_address;                            // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
+	wire  [15:0] cpu_instruction_master_address;                            // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
 	wire         cpu_instruction_master_read;                               // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
 	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect;  // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
 	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata;    // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
@@ -31,11 +28,8 @@ module niosII (
 	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_read;        // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
 	wire         mm_interconnect_0_jtag_uart_avalon_jtag_slave_write;       // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
 	wire  [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata;   // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
-	wire  [31:0] mm_interconnect_0_sem_ctl_slave_readdata;                  // sem:ctl_rddata -> mm_interconnect_0:sem_ctl_slave_readdata
+	wire         mm_interconnect_0_sigdel_0_avalon_slave_write;             // mm_interconnect_0:sigdel_0_avalon_slave_write -> sigdel_0:wr_n
-	wire   [0:0] mm_interconnect_0_sem_ctl_slave_address;                   // mm_interconnect_0:sem_ctl_slave_address -> sem:ctl_addr
+	wire  [31:0] mm_interconnect_0_sigdel_0_avalon_slave_writedata;         // mm_interconnect_0:sigdel_0_avalon_slave_writedata -> sigdel_0:wr_data
-	wire         mm_interconnect_0_sem_ctl_slave_read;                      // mm_interconnect_0:sem_ctl_slave_read -> sem:ctl_rd
-	wire         mm_interconnect_0_sem_ctl_slave_write;                     // mm_interconnect_0:sem_ctl_slave_write -> sem:ctl_wr
-	wire  [31:0] mm_interconnect_0_sem_ctl_slave_writedata;                 // mm_interconnect_0:sem_ctl_slave_writedata -> sem:ctl_wrdata
 	wire  [31:0] mm_interconnect_0_cpu_debug_mem_slave_readdata;            // cpu:debug_mem_slave_readdata -> mm_interconnect_0:cpu_debug_mem_slave_readdata
 	wire         mm_interconnect_0_cpu_debug_mem_slave_waitrequest;         // cpu:debug_mem_slave_waitrequest -> mm_interconnect_0:cpu_debug_mem_slave_waitrequest
 	wire         mm_interconnect_0_cpu_debug_mem_slave_debugaccess;         // mm_interconnect_0:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess
@@ -44,9 +38,6 @@ module niosII (
 	wire   [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable;          // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
 	wire         mm_interconnect_0_cpu_debug_mem_slave_write;               // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
 	wire  [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata;           // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
-	wire   [3:0] mm_interconnect_0_sem_ram_slave_address;                   // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr
-	wire         mm_interconnect_0_sem_ram_slave_write;                     // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr
-	wire  [31:0] mm_interconnect_0_sem_ram_slave_writedata;                 // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata
 	wire         mm_interconnect_0_sys_clk_timer_s1_chipselect;             // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
 	wire  [15:0] mm_interconnect_0_sys_clk_timer_s1_readdata;               // sys_clk_timer:readdata -> mm_interconnect_0:sys_clk_timer_s1_readdata
 	wire   [2:0] mm_interconnect_0_sys_clk_timer_s1_address;                // mm_interconnect_0:sys_clk_timer_s1_address -> sys_clk_timer:address
@@ -54,14 +45,14 @@ module niosII (
 	wire  [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata;              // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata
 	wire         mm_interconnect_0_mem_s2_chipselect;                       // mm_interconnect_0:mem_s2_chipselect -> mem:chipselect2
 	wire  [31:0] mm_interconnect_0_mem_s2_readdata;                         // mem:readdata2 -> mm_interconnect_0:mem_s2_readdata
-	wire  [14:0] mm_interconnect_0_mem_s2_address;                          // mm_interconnect_0:mem_s2_address -> mem:address2
+	wire  [12:0] mm_interconnect_0_mem_s2_address;                          // mm_interconnect_0:mem_s2_address -> mem:address2
 	wire   [3:0] mm_interconnect_0_mem_s2_byteenable;                       // mm_interconnect_0:mem_s2_byteenable -> mem:byteenable2
 	wire         mm_interconnect_0_mem_s2_write;                            // mm_interconnect_0:mem_s2_write -> mem:write2
 	wire  [31:0] mm_interconnect_0_mem_s2_writedata;                        // mm_interconnect_0:mem_s2_writedata -> mem:writedata2
 	wire         mm_interconnect_0_mem_s2_clken;                            // mm_interconnect_0:mem_s2_clken -> mem:clken2
 	wire         mm_interconnect_0_mem_s1_chipselect;                       // mm_interconnect_0:mem_s1_chipselect -> mem:chipselect
 	wire  [31:0] mm_interconnect_0_mem_s1_readdata;                         // mem:readdata -> mm_interconnect_0:mem_s1_readdata
-	wire  [14:0] mm_interconnect_0_mem_s1_address;                          // mm_interconnect_0:mem_s1_address -> mem:address
+	wire  [12:0] mm_interconnect_0_mem_s1_address;                          // mm_interconnect_0:mem_s1_address -> mem:address
 	wire   [3:0] mm_interconnect_0_mem_s1_byteenable;                       // mm_interconnect_0:mem_s1_byteenable -> mem:byteenable
 	wire         mm_interconnect_0_mem_s1_write;                            // mm_interconnect_0:mem_s1_write -> mem:write
 	wire  [31:0] mm_interconnect_0_mem_s1_writedata;                        // mm_interconnect_0:mem_s1_writedata -> mem:writedata
@@ -69,7 +60,7 @@ module niosII (
 	wire         irq_mapper_receiver0_irq;                                  // sys_clk_timer:irq -> irq_mapper:receiver0_irq
 	wire         irq_mapper_receiver1_irq;                                  // jtag_uart:av_irq -> irq_mapper:receiver1_irq
 	wire  [31:0] cpu_irq_irq;                                               // irq_mapper:sender_irq -> cpu:irq
-	wire         rst_controller_reset_out_reset;                            // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n]
+	wire         rst_controller_reset_out_reset;                            // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sigdel_0:clr_n, sys_clk_timer:reset_n]
 	wire         rst_controller_reset_out_reset_req;                        // rst_controller:reset_req -> [cpu:reset_req, mem:reset_req, rst_translator:reset_req_in]
 	wire         cpu_debug_reset_request_reset;                             // cpu:debug_reset_request -> rst_controller:reset_in1
 
@@ -136,23 +127,14 @@ module niosII (
 		.freeze      (1'b0)                                 // (terminated)
 	);
 
-	dec #(
+	sigdel #(
-		.m (32)
+		.PHACC_WIDTH (26)
-	) sem (
+	) sigdel_0 (
 		.clk     (clk_clk),                                           //        clock.clk
-		.ctl_wr     (mm_interconnect_0_sem_ctl_slave_write),     // ctl_slave.write
+		.clr_n   (~rst_controller_reset_out_reset),                   //   reset_sink.reset_n
-		.ctl_rd     (mm_interconnect_0_sem_ctl_slave_read),      //          .read
+		.fout    (conduit_end_writeresponsevalid_n),                  //  conduit_end.writeresponsevalid_n
-		.ctl_addr   (mm_interconnect_0_sem_ctl_slave_address),   //          .address
+		.wr_n    (~mm_interconnect_0_sigdel_0_avalon_slave_write),    // avalon_slave.write_n
-		.ctl_wrdata (mm_interconnect_0_sem_ctl_slave_writedata), //          .writedata
+		.wr_data (mm_interconnect_0_sigdel_0_avalon_slave_writedata)  //             .writedata
-		.ctl_rddata (mm_interconnect_0_sem_ctl_slave_readdata),  //          .readdata
-		.clrn       (~rst_controller_reset_out_reset),           //   reset_n.reset_n
-		.ram_wr     (mm_interconnect_0_sem_ram_slave_write),     // ram_slave.write
-		.ram_addr   (mm_interconnect_0_sem_ram_slave_address),   //          .address
-		.ram_wrdata (mm_interconnect_0_sem_ram_slave_writedata), //          .writedata
-		.train      (sem_export_train),                          //       sem.train
-		.red        (sem_export_red),                            //          .red
-		.yellow     (sem_export_yellow),                         //          .yellow
-		.green      (sem_export_green)                           //          .green
 	);
 
 	niosII_sys_clk_timer sys_clk_timer (
@@ -210,14 +192,8 @@ module niosII (
 		.mem_s2_byteenable                       (mm_interconnect_0_mem_s2_byteenable),                       //                                .byteenable
 		.mem_s2_chipselect                       (mm_interconnect_0_mem_s2_chipselect),                       //                                .chipselect
 		.mem_s2_clken                            (mm_interconnect_0_mem_s2_clken),                            //                                .clken
-		.sem_ctl_slave_address                   (mm_interconnect_0_sem_ctl_slave_address),                   //                   sem_ctl_slave.address
+		.sigdel_0_avalon_slave_write             (mm_interconnect_0_sigdel_0_avalon_slave_write),             //           sigdel_0_avalon_slave.write
-		.sem_ctl_slave_write                     (mm_interconnect_0_sem_ctl_slave_write),                     //                                .write
+		.sigdel_0_avalon_slave_writedata         (mm_interconnect_0_sigdel_0_avalon_slave_writedata),         //                                .writedata
-		.sem_ctl_slave_read                      (mm_interconnect_0_sem_ctl_slave_read),                      //                                .read
-		.sem_ctl_slave_readdata                  (mm_interconnect_0_sem_ctl_slave_readdata),                  //                                .readdata
-		.sem_ctl_slave_writedata                 (mm_interconnect_0_sem_ctl_slave_writedata),                 //                                .writedata
-		.sem_ram_slave_address                   (mm_interconnect_0_sem_ram_slave_address),                   //                   sem_ram_slave.address
-		.sem_ram_slave_write                     (mm_interconnect_0_sem_ram_slave_write),                     //                                .write
-		.sem_ram_slave_writedata                 (mm_interconnect_0_sem_ram_slave_writedata),                 //                                .writedata
 		.sys_clk_timer_s1_address                (mm_interconnect_0_sys_clk_timer_s1_address),                //                sys_clk_timer_s1.address
 		.sys_clk_timer_s1_write                  (mm_interconnect_0_sys_clk_timer_s1_write),                  //                                .write
 		.sys_clk_timer_s1_readdata               (mm_interconnect_0_sys_clk_timer_s1_readdata),               //                                .readdata

Top/niosII/synthesis/submodules/niosII_cpu.v

@@ -10,7 +10,7 @@ module niosII_cpu (
 		input  wire        clk,                                 //                       clk.clk
 		input  wire        reset_n,                             //                     reset.reset_n
 		input  wire        reset_req,                           //                          .reset_req
-		output wire [17:0] d_address,                           //               data_master.address
+		output wire [15:0] d_address,                           //               data_master.address
 		output wire [3:0]  d_byteenable,                        //                          .byteenable
 		output wire        d_read,                              //                          .read
 		input  wire [31:0] d_readdata,                          //                          .readdata
@@ -18,7 +18,7 @@ module niosII_cpu (
 		output wire        d_write,                             //                          .write
 		output wire [31:0] d_writedata,                         //                          .writedata
 		output wire        debug_mem_slave_debugaccess_to_roms, //                          .debugaccess
-		output wire [17:0] i_address,                           //        instruction_master.address
+		output wire [15:0] i_address,                           //        instruction_master.address
 		output wire        i_read,                              //                          .read
 		input  wire [31:0] i_readdata,                          //                          .readdata
 		input  wire        i_waitrequest,                       //                          .waitrequest

Top/niosII/synthesis/submodules/niosII_cpu_cpu.v

@@ -617,7 +617,7 @@ module niosII_cpu_cpu_nios2_oci_xbrk (
   output           xbrk_trigout;
   input            D_valid;
   input            E_valid;
-  input   [ 15: 0] F_pc;
+  input   [ 13: 0] F_pc;
   input            clk;
   input            reset_n;
   input            trigger_state_0;
@@ -635,7 +635,7 @@ reg              E_xbrk_goto1;
 reg              E_xbrk_traceoff;
 reg              E_xbrk_traceon;
 reg              E_xbrk_trigout;
-wire    [ 17: 0] cpu_i_address;
+wire    [ 15: 0] cpu_i_address;
 wire             xbrk0_armed;
 wire             xbrk0_break_hit;
 wire             xbrk0_goto0_hit;
@@ -821,7 +821,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
                                      )
 ;
 
-  output  [ 17: 0] cpu_d_address;
+  output  [ 15: 0] cpu_d_address;
   output           cpu_d_read;
   output  [ 31: 0] cpu_d_readdata;
   output           cpu_d_wait;
@@ -837,7 +837,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
   input   [ 31: 0] E_st_data;
   input   [ 31: 0] av_ld_data_aligned_filtered;
   input            clk;
-  input   [ 17: 0] d_address;
+  input   [ 15: 0] d_address;
   input            d_read;
   input            d_waitrequest;
   input            d_write;
@@ -845,7 +845,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
   input            reset_n;
 
 
-wire    [ 17: 0] cpu_d_address;
+wire    [ 15: 0] cpu_d_address;
 wire             cpu_d_read;
 wire    [ 31: 0] cpu_d_readdata;
 wire             cpu_d_wait;
@@ -1201,7 +1201,7 @@ module niosII_cpu_cpu_nios2_oci_dtrace (
   output  [ 35: 0] atm;
   output  [ 35: 0] dtm;
   input            clk;
-  input   [ 17: 0] cpu_d_address;
+  input   [ 15: 0] cpu_d_address;
   input            cpu_d_read;
   input   [ 31: 0] cpu_d_readdata;
   input            cpu_d_wait;
@@ -2339,7 +2339,7 @@ defparam niosII_cpu_cpu_ociram_sp_ram.lpm_file = "niosII_cpu_cpu_ociram_default_
 `endif
 //synthesis translate_on
   assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 :
-    (MonAReg[4 : 2] == 3'd1)? 32'h00001212 :
+    (MonAReg[4 : 2] == 3'd1)? 32'h00001010 :
     (MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
     (MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
     (MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
@@ -2403,12 +2403,12 @@ module niosII_cpu_cpu_nios2_oci (
   input            D_valid;
   input   [ 31: 0] E_st_data;
   input            E_valid;
-  input   [ 15: 0] F_pc;
+  input   [ 13: 0] F_pc;
   input   [  8: 0] address_nxt;
   input   [ 31: 0] av_ld_data_aligned_filtered;
   input   [  3: 0] byteenable_nxt;
   input            clk;
-  input   [ 17: 0] d_address;
+  input   [ 15: 0] d_address;
   input            d_read;
   input            d_waitrequest;
   input            d_write;
@@ -2427,7 +2427,7 @@ reg     [  8: 0] address;
 wire    [ 35: 0] atm;
 wire    [ 31: 0] break_readreg;
 reg     [  3: 0] byteenable;
-wire    [ 17: 0] cpu_d_address;
+wire    [ 15: 0] cpu_d_address;
 wire             cpu_d_read;
 wire    [ 31: 0] cpu_d_readdata;
 wire             cpu_d_wait;
@@ -2864,7 +2864,7 @@ module niosII_cpu_cpu (
                       )
 ;
 
-  output  [ 17: 0] d_address;
+  output  [ 15: 0] d_address;
   output  [  3: 0] d_byteenable;
   output           d_read;
   output           d_write;
@@ -2874,7 +2874,7 @@ module niosII_cpu_cpu (
   output           debug_mem_slave_waitrequest;
   output           debug_reset_request;
   output           dummy_ci_port;
-  output  [ 17: 0] i_address;
+  output  [ 15: 0] i_address;
   output           i_read;
   input            clk;
   input   [ 31: 0] d_readdata;
@@ -2959,7 +2959,7 @@ wire    [  4: 0] D_iw_imm5;
 wire    [  1: 0] D_iw_memsz;
 wire    [  5: 0] D_iw_op;
 wire    [  5: 0] D_iw_opx;
-wire    [ 15: 0] D_jmp_direct_target_waddr;
+wire    [ 13: 0] D_jmp_direct_target_waddr;
 wire    [  1: 0] D_logic_op;
 wire    [  1: 0] D_logic_op_raw;
 wire             D_mem16;
@@ -3110,7 +3110,7 @@ wire             E_ld_stall;
 wire    [ 31: 0] E_logic_result;
 wire             E_logic_result_is_0;
 wire             E_lt;
-wire    [ 17: 0] E_mem_baddr;
+wire    [ 15: 0] E_mem_baddr;
 wire    [  3: 0] E_mem_byte_en;
 reg              E_new_inst;
 wire             E_rf_ecc_recoverable_valid;
@@ -3301,15 +3301,15 @@ wire             F_op_wrprs;
 wire             F_op_xor;
 wire             F_op_xorhi;
 wire             F_op_xori;
-reg     [ 15: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
+reg     [ 13: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
 wire             F_pc_en;
-wire    [ 15: 0] F_pc_no_crst_nxt;
+wire    [ 13: 0] F_pc_no_crst_nxt;
-wire    [ 15: 0] F_pc_nxt;
+wire    [ 13: 0] F_pc_nxt;
-wire    [ 15: 0] F_pc_plus_one;
+wire    [ 13: 0] F_pc_plus_one;
 wire    [  1: 0] F_pc_sel_nxt;
-wire    [ 17: 0] F_pcb;
+wire    [ 15: 0] F_pcb;
-wire    [ 17: 0] F_pcb_nxt;
+wire    [ 15: 0] F_pcb_nxt;
-wire    [ 17: 0] F_pcb_plus_four;
+wire    [ 15: 0] F_pcb_plus_four;
 wire             F_valid;
 wire    [ 71: 0] F_vinst;
 reg     [  1: 0] R_compare_op;
@@ -3443,7 +3443,7 @@ reg     [ 31: 0] W_ienable_reg;
 wire    [ 31: 0] W_ienable_reg_nxt;
 reg     [ 31: 0] W_ipending_reg;
 wire    [ 31: 0] W_ipending_reg_nxt;
-wire    [ 17: 0] W_mem_baddr;
+wire    [ 15: 0] W_mem_baddr;
 reg              W_rf_ecc_recoverable_valid;
 reg              W_rf_ecc_unrecoverable_valid;
 wire             W_rf_ecc_valid_any;
@@ -3483,7 +3483,7 @@ wire             av_ld_rshift8;
 reg              av_ld_waiting_for_data;
 wire             av_ld_waiting_for_data_nxt;
 wire             av_sign_bit;
-wire    [ 17: 0] d_address;
+wire    [ 15: 0] d_address;
 reg     [  3: 0] d_byteenable;
 reg              d_read;
 wire             d_read_nxt;
@@ -3501,7 +3501,7 @@ reg              hbreak_enabled;
 reg              hbreak_pending;
 wire             hbreak_pending_nxt;
 wire             hbreak_req;
-wire    [ 17: 0] i_address;
+wire    [ 15: 0] i_address;
 reg              i_read;
 wire             i_read_nxt;
 wire    [ 31: 0] iactive;
@@ -3863,8 +3863,8 @@ reg              wait_for_one_post_bret_inst;
     2'b11;
 
   assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 :
-    (F_pc_sel_nxt == 2'b01)? 33288 :
+    (F_pc_sel_nxt == 2'b01)? 8712 :
-    (F_pc_sel_nxt == 2'b10)? E_arith_result[17 : 2] :
+    (F_pc_sel_nxt == 2'b10)? E_arith_result[15 : 2] :
     F_pc_plus_one;
 
   assign F_pc_nxt = F_pc_no_crst_nxt;
@@ -4166,7 +4166,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
     E_arith_src1 - E_arith_src2 :
     E_arith_src1 + E_arith_src2;
 
-  assign E_mem_baddr = E_arith_result[17 : 0];
+  assign E_mem_baddr = E_arith_result[15 : 0];
   assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
     (R_logic_op == 2'b01)? (E_src1 & E_src2) :
     (R_logic_op == 2'b10)? (E_src1 | E_src2) :
@@ -4489,7 +4489,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
 
   assign W_wr_data = W_wr_data_non_zero;
   assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result);
-  assign W_mem_baddr = W_alu_result[17 : 0];
+  assign W_mem_baddr = W_alu_result[15 : 0];
   assign W_status_reg = W_status_reg_pie;
   assign E_wrctl_status = R_ctrl_wrctl_inst & 
     (D_iw_control_regnum == 5'd0);

Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v

@@ -59,7 +59,7 @@ module niosII_cpu_cpu_test_bench (
   input   [  5: 0] D_iw_opx;
   input            D_valid;
   input            E_valid;
-  input   [ 17: 0] F_pcb;
+  input   [ 15: 0] F_pcb;
   input            F_valid;
   input            R_ctrl_ld;
   input            R_ctrl_ld_non_io;
@@ -70,11 +70,11 @@ module niosII_cpu_cpu_test_bench (
   input   [ 31: 0] W_wr_data;
   input   [ 31: 0] av_ld_data_aligned_unfiltered;
   input            clk;
-  input   [ 17: 0] d_address;
+  input   [ 15: 0] d_address;
   input   [  3: 0] d_byteenable;
   input            d_read;
   input            d_write;
-  input   [ 17: 0] i_address;
+  input   [ 15: 0] i_address;
   input            i_read;
   input   [ 31: 0] i_readdata;
   input            i_waitrequest;

Top/niosII/synthesis/submodules/niosII_mem.v

@@ -48,8 +48,8 @@ module niosII_mem (
 
   output  [ 31: 0] readdata;
   output  [ 31: 0] readdata2;
-  input   [ 14: 0] address;
+  input   [ 12: 0] address;
-  input   [ 14: 0] address2;
+  input   [ 12: 0] address2;
   input   [  3: 0] byteenable;
   input   [  3: 0] byteenable2;
   input            chipselect;
@@ -102,9 +102,9 @@ wire             wren2;
            the_altsyncram.indata_reg_b = "CLOCK0",
            the_altsyncram.init_file = INIT_FILE,
            the_altsyncram.lpm_type = "altsyncram",
-           the_altsyncram.maximum_depth = 32768,
+           the_altsyncram.maximum_depth = 8192,
-           the_altsyncram.numwords_a = 32768,
+           the_altsyncram.numwords_a = 8192,
-           the_altsyncram.numwords_b = 32768,
+           the_altsyncram.numwords_b = 8192,
            the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
            the_altsyncram.outdata_reg_a = "UNREGISTERED",
            the_altsyncram.outdata_reg_b = "UNREGISTERED",
@@ -114,8 +114,8 @@ wire             wren2;
            the_altsyncram.width_b = 32,
            the_altsyncram.width_byteena_a = 4,
            the_altsyncram.width_byteena_b = 4,
-           the_altsyncram.widthad_a = 15,
+           the_altsyncram.widthad_a = 13,
-           the_altsyncram.widthad_b = 15,
+           the_altsyncram.widthad_b = 13,
            the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0";
 
   //s1, which is an e_avalon_slave

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv

@@ -28,9 +28,9 @@
 // ------------------------------------------
 // Generation parameters:
 //   output_name:         niosII_mm_interconnect_0_cmd_demux
-//   ST_DATA_W:           94
+//   ST_DATA_W:           92
-//   ST_CHANNEL_W:        7
+//   ST_CHANNEL_W:        6
-//   NUM_OUTPUTS:         6
+//   NUM_OUTPUTS:         5
 //   VALID_WIDTH:         1
 // ------------------------------------------
 
@@ -46,8 +46,8 @@ module niosII_mm_interconnect_0_cmd_demux
     // Sink
     // -------------------
     input  [1-1      : 0]   sink_valid,
-    input  [94-1    : 0]   sink_data, // ST_DATA_W=94
+    input  [92-1    : 0]   sink_data, // ST_DATA_W=92
-    input  [7-1 : 0]   sink_channel, // ST_CHANNEL_W=7
+    input  [6-1 : 0]   sink_channel, // ST_CHANNEL_W=6
     input                         sink_startofpacket,
     input                         sink_endofpacket,
     output                        sink_ready,
@@ -56,47 +56,40 @@ module niosII_mm_interconnect_0_cmd_demux
     // Sources 
     // -------------------
     output reg                      src0_valid,
-    output reg [94-1    : 0] src0_data, // ST_DATA_W=94
+    output reg [92-1    : 0] src0_data, // ST_DATA_W=92
-    output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
+    output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
     output reg                      src0_startofpacket,
     output reg                      src0_endofpacket,
     input                           src0_ready,
 
     output reg                      src1_valid,
-    output reg [94-1    : 0] src1_data, // ST_DATA_W=94
+    output reg [92-1    : 0] src1_data, // ST_DATA_W=92
-    output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
+    output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
     output reg                      src1_startofpacket,
     output reg                      src1_endofpacket,
     input                           src1_ready,
 
     output reg                      src2_valid,
-    output reg [94-1    : 0] src2_data, // ST_DATA_W=94
+    output reg [92-1    : 0] src2_data, // ST_DATA_W=92
-    output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
+    output reg [6-1 : 0] src2_channel, // ST_CHANNEL_W=6
     output reg                      src2_startofpacket,
     output reg                      src2_endofpacket,
     input                           src2_ready,
 
     output reg                      src3_valid,
-    output reg [94-1    : 0] src3_data, // ST_DATA_W=94
+    output reg [92-1    : 0] src3_data, // ST_DATA_W=92
-    output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7
+    output reg [6-1 : 0] src3_channel, // ST_CHANNEL_W=6
     output reg                      src3_startofpacket,
     output reg                      src3_endofpacket,
     input                           src3_ready,
 
     output reg                      src4_valid,
-    output reg [94-1    : 0] src4_data, // ST_DATA_W=94
+    output reg [92-1    : 0] src4_data, // ST_DATA_W=92
-    output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7
+    output reg [6-1 : 0] src4_channel, // ST_CHANNEL_W=6
     output reg                      src4_startofpacket,
     output reg                      src4_endofpacket,
     input                           src4_ready,
 
-    output reg                      src5_valid,
-    output reg [94-1    : 0] src5_data, // ST_DATA_W=94
-    output reg [7-1 : 0] src5_channel, // ST_CHANNEL_W=7
-    output reg                      src5_startofpacket,
-    output reg                      src5_endofpacket,
-    input                           src5_ready,
-
 
     // -------------------
     // Clock & Reset
@@ -108,7 +101,7 @@ module niosII_mm_interconnect_0_cmd_demux
 
 );
 
-    localparam NUM_OUTPUTS = 6;
+    localparam NUM_OUTPUTS = 5;
     wire [NUM_OUTPUTS - 1 : 0] ready_vector;
 
     // -------------------
@@ -150,13 +143,6 @@ module niosII_mm_interconnect_0_cmd_demux
 
         src4_valid         = sink_channel[4] && sink_valid;
 
-        src5_data          = sink_data;
-        src5_startofpacket = sink_startofpacket;
-        src5_endofpacket   = sink_endofpacket;
-        src5_channel       = sink_channel >> NUM_OUTPUTS;
-
-        src5_valid         = sink_channel[5] && sink_valid;
-
     end
 
     // -------------------
@@ -167,7 +153,6 @@ module niosII_mm_interconnect_0_cmd_demux
     assign ready_vector[2] = src2_ready;
     assign ready_vector[3] = src3_ready;
     assign ready_vector[4] = src4_ready;
-    assign ready_vector[5] = src5_ready;
 
     assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
 

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv

@@ -28,8 +28,8 @@
 // ------------------------------------------
 // Generation parameters:
 //   output_name:         niosII_mm_interconnect_0_cmd_demux_001
-//   ST_DATA_W:           94
+//   ST_DATA_W:           92
-//   ST_CHANNEL_W:        7
+//   ST_CHANNEL_W:        6
 //   NUM_OUTPUTS:         2
 //   VALID_WIDTH:         1
 // ------------------------------------------
@@ -46,8 +46,8 @@ module niosII_mm_interconnect_0_cmd_demux_001
     // Sink
     // -------------------
     input  [1-1      : 0]   sink_valid,
-    input  [94-1    : 0]   sink_data, // ST_DATA_W=94
+    input  [92-1    : 0]   sink_data, // ST_DATA_W=92
-    input  [7-1 : 0]   sink_channel, // ST_CHANNEL_W=7
+    input  [6-1 : 0]   sink_channel, // ST_CHANNEL_W=6
     input                         sink_startofpacket,
     input                         sink_endofpacket,
     output                        sink_ready,
@@ -56,15 +56,15 @@ module niosII_mm_interconnect_0_cmd_demux_001
     // Sources 
     // -------------------
     output reg                      src0_valid,
-    output reg [94-1    : 0] src0_data, // ST_DATA_W=94
+    output reg [92-1    : 0] src0_data, // ST_DATA_W=92
-    output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
+    output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
     output reg                      src0_startofpacket,
     output reg                      src0_endofpacket,
     input                           src0_ready,
 
     output reg                      src1_valid,
-    output reg [94-1    : 0] src1_data, // ST_DATA_W=94
+    output reg [92-1    : 0] src1_data, // ST_DATA_W=92
-    output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
+    output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
     output reg                      src1_startofpacket,
     output reg                      src1_endofpacket,
     input                           src1_ready,
@@ -109,7 +109,7 @@ module niosII_mm_interconnect_0_cmd_demux_001
     assign ready_vector[0] = src0_ready;
     assign ready_vector[1] = src1_ready;
 
-    assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+    assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
 
 endmodule
 

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv

@@ -43,9 +43,9 @@
 //   ARBITRATION_SHARES:  1
 //   ARBITRATION_SCHEME   "round-robin"
 //   PIPELINE_ARB:        1
-//   PKT_TRANS_LOCK:      58 (arbitration locking enabled)
+//   PKT_TRANS_LOCK:      56 (arbitration locking enabled)
-//   ST_DATA_W:           94
+//   ST_DATA_W:           92
-//   ST_CHANNEL_W:        7
+//   ST_CHANNEL_W:        6
 // ------------------------------------------
 
 module niosII_mm_interconnect_0_cmd_mux
@@ -54,8 +54,8 @@ module niosII_mm_interconnect_0_cmd_mux
     // Sinks
     // ----------------------
     input                       sink0_valid,
-    input [94-1   : 0]  sink0_data,
+    input [92-1   : 0]  sink0_data,
-    input [7-1: 0]  sink0_channel,
+    input [6-1: 0]  sink0_channel,
     input                       sink0_startofpacket,
     input                       sink0_endofpacket,
     output                      sink0_ready,
@@ -65,8 +65,8 @@ module niosII_mm_interconnect_0_cmd_mux
     // Source
     // ----------------------
     output                      src_valid,
-    output [94-1    : 0] src_data,
+    output [92-1    : 0] src_data,
-    output [7-1 : 0] src_channel,
+    output [6-1 : 0] src_channel,
     output                      src_startofpacket,
     output                      src_endofpacket,
     input                       src_ready,
@@ -77,13 +77,13 @@ module niosII_mm_interconnect_0_cmd_mux
     input clk,
     input reset
 );
-    localparam PAYLOAD_W        = 94 + 7 + 2;
+    localparam PAYLOAD_W        = 92 + 6 + 2;
     localparam NUM_INPUTS       = 1;
     localparam SHARE_COUNTER_W  = 1;
     localparam PIPELINE_ARB     = 1;
-    localparam ST_DATA_W        = 94;
+    localparam ST_DATA_W        = 92;
-    localparam ST_CHANNEL_W     = 7;
+    localparam ST_CHANNEL_W     = 6;
-    localparam PKT_TRANS_LOCK   = 58;
+    localparam PKT_TRANS_LOCK   = 56;
 
     assign	src_valid			=  sink0_valid;
     assign	src_data			=  sink0_data;

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv

@@ -43,9 +43,9 @@
 //   ARBITRATION_SHARES:  1 1
 //   ARBITRATION_SCHEME   "round-robin"
 //   PIPELINE_ARB:        1
-//   PKT_TRANS_LOCK:      58 (arbitration locking enabled)
+//   PKT_TRANS_LOCK:      56 (arbitration locking enabled)
-//   ST_DATA_W:           94
+//   ST_DATA_W:           92
-//   ST_CHANNEL_W:        7
+//   ST_CHANNEL_W:        6
 // ------------------------------------------
 
 module niosII_mm_interconnect_0_cmd_mux_002
@@ -54,15 +54,15 @@ module niosII_mm_interconnect_0_cmd_mux_002
     // Sinks
     // ----------------------
     input                       sink0_valid,
-    input [94-1   : 0]  sink0_data,
+    input [92-1   : 0]  sink0_data,
-    input [7-1: 0]  sink0_channel,
+    input [6-1: 0]  sink0_channel,
     input                       sink0_startofpacket,
     input                       sink0_endofpacket,
     output                      sink0_ready,
 
     input                       sink1_valid,
-    input [94-1   : 0]  sink1_data,
+    input [92-1   : 0]  sink1_data,
-    input [7-1: 0]  sink1_channel,
+    input [6-1: 0]  sink1_channel,
     input                       sink1_startofpacket,
     input                       sink1_endofpacket,
     output                      sink1_ready,
@@ -72,8 +72,8 @@ module niosII_mm_interconnect_0_cmd_mux_002
     // Source
     // ----------------------
     output                      src_valid,
-    output [94-1    : 0] src_data,
+    output [92-1    : 0] src_data,
-    output [7-1 : 0] src_channel,
+    output [6-1 : 0] src_channel,
     output                      src_startofpacket,
     output                      src_endofpacket,
     input                       src_ready,
@@ -84,13 +84,13 @@ module niosII_mm_interconnect_0_cmd_mux_002
     input clk,
     input reset
 );
-    localparam PAYLOAD_W        = 94 + 7 + 2;
+    localparam PAYLOAD_W        = 92 + 6 + 2;
     localparam NUM_INPUTS       = 2;
     localparam SHARE_COUNTER_W  = 1;
     localparam PIPELINE_ARB     = 1;
-    localparam ST_DATA_W        = 94;
+    localparam ST_DATA_W        = 92;
-    localparam ST_CHANNEL_W     = 7;
+    localparam ST_CHANNEL_W     = 6;
-    localparam PKT_TRANS_LOCK   = 58;
+    localparam PKT_TRANS_LOCK   = 56;
 
     // ------------------------------------------
     // Signals
@@ -122,8 +122,8 @@ module niosII_mm_interconnect_0_cmd_mux_002
     // ------------------------------------------
     reg [NUM_INPUTS - 1 : 0] lock;
     always @* begin
-      lock[0] = sink0_data[58];
+      lock[0] = sink0_data[56];
-      lock[1] = sink1_data[58];
+      lock[1] = sink1_data[56];
     end
     reg [NUM_INPUTS - 1 : 0] locked = '0;
     always @(posedge clk or posedge reset) begin

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv

@@ -44,26 +44,26 @@
 
 module niosII_mm_interconnect_0_router_default_decode
   #(
-     parameter DEFAULT_CHANNEL = 5,
+     parameter DEFAULT_CHANNEL = 4,
                DEFAULT_WR_CHANNEL = -1,
                DEFAULT_RD_CHANNEL = -1,
                DEFAULT_DESTID = 3 
    )
-  (output [80 - 78 : 0] default_destination_id,
+  (output [78 - 76 : 0] default_destination_id,
-   output [7-1 : 0] default_wr_channel,
+   output [6-1 : 0] default_wr_channel,
-   output [7-1 : 0] default_rd_channel,
+   output [6-1 : 0] default_rd_channel,
-   output [7-1 : 0] default_src_channel
+   output [6-1 : 0] default_src_channel
   );
 
   assign default_destination_id = 
-    DEFAULT_DESTID[80 - 78 : 0];
+    DEFAULT_DESTID[78 - 76 : 0];
 
   generate
     if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
       assign default_src_channel = '0;
     end
     else begin : default_channel_assignment
-      assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
+      assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
     end
   endgenerate
 
@@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_default_decode
       assign default_rd_channel = '0;
     end
     else begin : default_rw_channel_assignment
-      assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
+      assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
-      assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
+      assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
     end
   endgenerate
 
@@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router
     // Command Sink (Input)
     // -------------------
     input                       sink_valid,
-    input  [94-1 : 0]    sink_data,
+    input  [92-1 : 0]    sink_data,
     input                       sink_startofpacket,
     input                       sink_endofpacket,
     output                      sink_ready,
@@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router
     // Command Source (Output)
     // -------------------
     output                          src_valid,
-    output reg [94-1    : 0] src_data,
+    output reg [92-1    : 0] src_data,
-    output reg [7-1 : 0] src_channel,
+    output reg [6-1 : 0] src_channel,
     output                          src_startofpacket,
     output                          src_endofpacket,
     input                           src_ready
@@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router
     // -------------------------------------------------------
     // Local parameters and variables
     // -------------------------------------------------------
-    localparam PKT_ADDR_H = 53;
+    localparam PKT_ADDR_H = 51;
     localparam PKT_ADDR_L = 36;
-    localparam PKT_DEST_ID_H = 80;
+    localparam PKT_DEST_ID_H = 78;
-    localparam PKT_DEST_ID_L = 78;
+    localparam PKT_DEST_ID_L = 76;
-    localparam PKT_PROTECTION_H = 84;
+    localparam PKT_PROTECTION_H = 82;
-    localparam PKT_PROTECTION_L = 82;
+    localparam PKT_PROTECTION_L = 80;
-    localparam ST_DATA_W = 94;
+    localparam ST_DATA_W = 92;
-    localparam ST_CHANNEL_W = 7;
+    localparam ST_CHANNEL_W = 6;
     localparam DECODER_TYPE = 0;
 
-    localparam PKT_TRANS_WRITE = 56;
+    localparam PKT_TRANS_WRITE = 54;
-    localparam PKT_TRANS_READ  = 57;
+    localparam PKT_TRANS_READ  = 55;
 
     localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
     localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@@ -134,18 +134,17 @@ module niosII_mm_interconnect_0_router
     // Figure out the number of bits to mask off for each slave span
     // during address decoding
     // -------------------------------------------------------
-    localparam PAD0 = log2ceil(64'h20000 - 64'h0); 
+    localparam PAD0 = log2ceil(64'h8000 - 64'h0); 
-    localparam PAD1 = log2ceil(64'h21000 - 64'h20800); 
+    localparam PAD1 = log2ceil(64'h9000 - 64'h8800); 
-    localparam PAD2 = log2ceil(64'h21040 - 64'h21000); 
+    localparam PAD2 = log2ceil(64'h9020 - 64'h9000); 
-    localparam PAD3 = log2ceil(64'h21060 - 64'h21040); 
+    localparam PAD3 = log2ceil(64'h9028 - 64'h9020); 
-    localparam PAD4 = log2ceil(64'h21068 - 64'h21060); 
+    localparam PAD4 = log2ceil(64'h902c - 64'h9028); 
-    localparam PAD5 = log2ceil(64'h21070 - 64'h21068); 
     // -------------------------------------------------------
     // Work out which address bits are significant based on the
     // address range of the slaves. If the required width is too
     // large or too small, we use the address field width instead.
     // -------------------------------------------------------
-    localparam ADDR_RANGE = 64'h21070;
+    localparam ADDR_RANGE = 64'h902c;
     localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
     localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
                                   (RANGE_ADDR_WIDTH == 0) ?
@@ -169,7 +168,7 @@ module niosII_mm_interconnect_0_router
     assign src_startofpacket = sink_startofpacket;
     assign src_endofpacket   = sink_endofpacket;
     wire [PKT_DEST_ID_W-1:0] default_destid;
-    wire [7-1 : 0] default_src_channel;
+    wire [6-1 : 0] default_src_channel;
 
 
 
@@ -198,42 +197,36 @@ module niosII_mm_interconnect_0_router
         // Sets the channel and destination ID based on the address
         // --------------------------------------------------
 
-    // ( 0x0 .. 0x20000 )
+    // ( 0x0 .. 0x8000 )
-    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0   ) begin
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 16'h0   ) begin
-            src_channel = 7'b100000;
+            src_channel = 6'b10000;
             src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
     end
 
-    // ( 0x20800 .. 0x21000 )
+    // ( 0x8800 .. 0x9000 )
-    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800   ) begin
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 16'h8800   ) begin
-            src_channel = 7'b000100;
+            src_channel = 6'b00100;
             src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
     end
 
-    // ( 0x21000 .. 0x21040 )
+    // ( 0x9000 .. 0x9020 )
-    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000  && write_transaction  ) begin
+    if ( {address[RG:PAD2],{PAD2{1'b0}}} == 16'h9000   ) begin
-            src_channel = 7'b001000;
+            src_channel = 6'b01000;
             src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
     end
 
-    // ( 0x21040 .. 0x21060 )
+    // ( 0x9020 .. 0x9028 )
-    if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21040   ) begin
+    if ( {address[RG:PAD3],{PAD3{1'b0}}} == 16'h9020   ) begin
-            src_channel = 7'b010000;
+            src_channel = 6'b00001;
-            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
-    end
-
-    // ( 0x21060 .. 0x21068 )
-    if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21060   ) begin
-            src_channel = 7'b000010;
-            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
-    end
-
-    // ( 0x21068 .. 0x21070 )
-    if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21068   ) begin
-            src_channel = 7'b000001;
             src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
     end
 
+    // ( 0x9028 .. 0x902c )
+    if ( {address[RG:PAD4],{PAD4{1'b0}}} == 16'h9028  && write_transaction  ) begin
+            src_channel = 6'b00010;
+            src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
+    end
+
 end
 
 

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv

@@ -49,21 +49,21 @@ module niosII_mm_interconnect_0_router_001_default_decode
                DEFAULT_RD_CHANNEL = -1,
                DEFAULT_DESTID = 2 
    )
-  (output [80 - 78 : 0] default_destination_id,
+  (output [78 - 76 : 0] default_destination_id,
-   output [7-1 : 0] default_wr_channel,
+   output [6-1 : 0] default_wr_channel,
-   output [7-1 : 0] default_rd_channel,
+   output [6-1 : 0] default_rd_channel,
-   output [7-1 : 0] default_src_channel
+   output [6-1 : 0] default_src_channel
   );
 
   assign default_destination_id = 
-    DEFAULT_DESTID[80 - 78 : 0];
+    DEFAULT_DESTID[78 - 76 : 0];
 
   generate
     if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
       assign default_src_channel = '0;
     end
     else begin : default_channel_assignment
-      assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
+      assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
     end
   endgenerate
 
@@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_001_default_decode
       assign default_rd_channel = '0;
     end
     else begin : default_rw_channel_assignment
-      assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
+      assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
-      assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
+      assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
     end
   endgenerate
 
@@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_001
     // Command Sink (Input)
     // -------------------
     input                       sink_valid,
-    input  [94-1 : 0]    sink_data,
+    input  [92-1 : 0]    sink_data,
     input                       sink_startofpacket,
     input                       sink_endofpacket,
     output                      sink_ready,
@@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router_001
     // Command Source (Output)
     // -------------------
     output                          src_valid,
-    output reg [94-1    : 0] src_data,
+    output reg [92-1    : 0] src_data,
-    output reg [7-1 : 0] src_channel,
+    output reg [6-1 : 0] src_channel,
     output                          src_startofpacket,
     output                          src_endofpacket,
     input                           src_ready
@@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_001
     // -------------------------------------------------------
     // Local parameters and variables
     // -------------------------------------------------------
-    localparam PKT_ADDR_H = 53;
+    localparam PKT_ADDR_H = 51;
     localparam PKT_ADDR_L = 36;
-    localparam PKT_DEST_ID_H = 80;
+    localparam PKT_DEST_ID_H = 78;
-    localparam PKT_DEST_ID_L = 78;
+    localparam PKT_DEST_ID_L = 76;
-    localparam PKT_PROTECTION_H = 84;
+    localparam PKT_PROTECTION_H = 82;
-    localparam PKT_PROTECTION_L = 82;
+    localparam PKT_PROTECTION_L = 80;
-    localparam ST_DATA_W = 94;
+    localparam ST_DATA_W = 92;
-    localparam ST_CHANNEL_W = 7;
+    localparam ST_CHANNEL_W = 6;
     localparam DECODER_TYPE = 0;
 
-    localparam PKT_TRANS_WRITE = 56;
+    localparam PKT_TRANS_WRITE = 54;
-    localparam PKT_TRANS_READ  = 57;
+    localparam PKT_TRANS_READ  = 55;
 
     localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
     localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@@ -134,14 +134,14 @@ module niosII_mm_interconnect_0_router_001
     // Figure out the number of bits to mask off for each slave span
     // during address decoding
     // -------------------------------------------------------
-    localparam PAD0 = log2ceil(64'h20000 - 64'h0); 
+    localparam PAD0 = log2ceil(64'h8000 - 64'h0); 
-    localparam PAD1 = log2ceil(64'h21000 - 64'h20800); 
+    localparam PAD1 = log2ceil(64'h9000 - 64'h8800); 
     // -------------------------------------------------------
     // Work out which address bits are significant based on the
     // address range of the slaves. If the required width is too
     // large or too small, we use the address field width instead.
     // -------------------------------------------------------
-    localparam ADDR_RANGE = 64'h21000;
+    localparam ADDR_RANGE = 64'h9000;
     localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
     localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
                                   (RANGE_ADDR_WIDTH == 0) ?
@@ -165,7 +165,7 @@ module niosII_mm_interconnect_0_router_001
     assign src_startofpacket = sink_startofpacket;
     assign src_endofpacket   = sink_endofpacket;
     wire [PKT_DEST_ID_W-1:0] default_destid;
-    wire [7-1 : 0] default_src_channel;
+    wire [6-1 : 0] default_src_channel;
 
 
 
@@ -189,15 +189,15 @@ module niosII_mm_interconnect_0_router_001
         // Sets the channel and destination ID based on the address
         // --------------------------------------------------
 
-    // ( 0x0 .. 0x20000 )
+    // ( 0x0 .. 0x8000 )
-    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0   ) begin
+    if ( {address[RG:PAD0],{PAD0{1'b0}}} == 16'h0   ) begin
-            src_channel = 7'b10;
+            src_channel = 6'b10;
             src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
     end
 
-    // ( 0x20800 .. 0x21000 )
+    // ( 0x8800 .. 0x9000 )
-    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800   ) begin
+    if ( {address[RG:PAD1],{PAD1{1'b0}}} == 16'h8800   ) begin
-            src_channel = 7'b01;
+            src_channel = 6'b01;
             src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
     end
 

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv

@@ -49,21 +49,21 @@ module niosII_mm_interconnect_0_router_002_default_decode
                DEFAULT_RD_CHANNEL = -1,
                DEFAULT_DESTID = 0 
    )
-  (output [80 - 78 : 0] default_destination_id,
+  (output [78 - 76 : 0] default_destination_id,
-   output [7-1 : 0] default_wr_channel,
+   output [6-1 : 0] default_wr_channel,
-   output [7-1 : 0] default_rd_channel,
+   output [6-1 : 0] default_rd_channel,
-   output [7-1 : 0] default_src_channel
+   output [6-1 : 0] default_src_channel
   );
 
   assign default_destination_id = 
-    DEFAULT_DESTID[80 - 78 : 0];
+    DEFAULT_DESTID[78 - 76 : 0];
 
   generate
     if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
       assign default_src_channel = '0;
     end
     else begin : default_channel_assignment
-      assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
+      assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
     end
   endgenerate
 
@@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_002_default_decode
       assign default_rd_channel = '0;
     end
     else begin : default_rw_channel_assignment
-      assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
+      assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
-      assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
+      assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
     end
   endgenerate
 
@@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_002
     // Command Sink (Input)
     // -------------------
     input                       sink_valid,
-    input  [94-1 : 0]    sink_data,
+    input  [92-1 : 0]    sink_data,
     input                       sink_startofpacket,
     input                       sink_endofpacket,
     output                      sink_ready,
@@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router_002
     // Command Source (Output)
     // -------------------
     output                          src_valid,
-    output reg [94-1    : 0] src_data,
+    output reg [92-1    : 0] src_data,
-    output reg [7-1 : 0] src_channel,
+    output reg [6-1 : 0] src_channel,
     output                          src_startofpacket,
     output                          src_endofpacket,
     input                           src_ready
@@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_002
     // -------------------------------------------------------
     // Local parameters and variables
     // -------------------------------------------------------
-    localparam PKT_ADDR_H = 53;
+    localparam PKT_ADDR_H = 51;
     localparam PKT_ADDR_L = 36;
-    localparam PKT_DEST_ID_H = 80;
+    localparam PKT_DEST_ID_H = 78;
-    localparam PKT_DEST_ID_L = 78;
+    localparam PKT_DEST_ID_L = 76;
-    localparam PKT_PROTECTION_H = 84;
+    localparam PKT_PROTECTION_H = 82;
-    localparam PKT_PROTECTION_L = 82;
+    localparam PKT_PROTECTION_L = 80;
-    localparam ST_DATA_W = 94;
+    localparam ST_DATA_W = 92;
-    localparam ST_CHANNEL_W = 7;
+    localparam ST_CHANNEL_W = 6;
     localparam DECODER_TYPE = 1;
 
-    localparam PKT_TRANS_WRITE = 56;
+    localparam PKT_TRANS_WRITE = 54;
-    localparam PKT_TRANS_READ  = 57;
+    localparam PKT_TRANS_READ  = 55;
 
     localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
     localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@@ -158,7 +158,7 @@ module niosII_mm_interconnect_0_router_002
     assign src_valid         = sink_valid;
     assign src_startofpacket = sink_startofpacket;
     assign src_endofpacket   = sink_endofpacket;
-    wire [7-1 : 0] default_src_channel;
+    wire [6-1 : 0] default_src_channel;
 
 
 
@@ -185,7 +185,7 @@ module niosII_mm_interconnect_0_router_002
 
 
         if (destid == 0 ) begin
-            src_channel = 7'b1;
+            src_channel = 6'b1;
         end
 
 

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv

@@ -49,21 +49,21 @@ module niosII_mm_interconnect_0_router_004_default_decode
                DEFAULT_RD_CHANNEL = -1,
                DEFAULT_DESTID = 0 
    )
-  (output [80 - 78 : 0] default_destination_id,
+  (output [78 - 76 : 0] default_destination_id,
-   output [7-1 : 0] default_wr_channel,
+   output [6-1 : 0] default_wr_channel,
-   output [7-1 : 0] default_rd_channel,
+   output [6-1 : 0] default_rd_channel,
-   output [7-1 : 0] default_src_channel
+   output [6-1 : 0] default_src_channel
   );
 
   assign default_destination_id = 
-    DEFAULT_DESTID[80 - 78 : 0];
+    DEFAULT_DESTID[78 - 76 : 0];
 
   generate
     if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
       assign default_src_channel = '0;
     end
     else begin : default_channel_assignment
-      assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
+      assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
     end
   endgenerate
 
@@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_004_default_decode
       assign default_rd_channel = '0;
     end
     else begin : default_rw_channel_assignment
-      assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
+      assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
-      assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
+      assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
     end
   endgenerate
 
@@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_004
     // Command Sink (Input)
     // -------------------
     input                       sink_valid,
-    input  [94-1 : 0]    sink_data,
+    input  [92-1 : 0]    sink_data,
     input                       sink_startofpacket,
     input                       sink_endofpacket,
     output                      sink_ready,
@@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router_004
     // Command Source (Output)
     // -------------------
     output                          src_valid,
-    output reg [94-1    : 0] src_data,
+    output reg [92-1    : 0] src_data,
-    output reg [7-1 : 0] src_channel,
+    output reg [6-1 : 0] src_channel,
     output                          src_startofpacket,
     output                          src_endofpacket,
     input                           src_ready
@@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_004
     // -------------------------------------------------------
     // Local parameters and variables
     // -------------------------------------------------------
-    localparam PKT_ADDR_H = 53;
+    localparam PKT_ADDR_H = 51;
     localparam PKT_ADDR_L = 36;
-    localparam PKT_DEST_ID_H = 80;
+    localparam PKT_DEST_ID_H = 78;
-    localparam PKT_DEST_ID_L = 78;
+    localparam PKT_DEST_ID_L = 76;
-    localparam PKT_PROTECTION_H = 84;
+    localparam PKT_PROTECTION_H = 82;
-    localparam PKT_PROTECTION_L = 82;
+    localparam PKT_PROTECTION_L = 80;
-    localparam ST_DATA_W = 94;
+    localparam ST_DATA_W = 92;
-    localparam ST_CHANNEL_W = 7;
+    localparam ST_CHANNEL_W = 6;
     localparam DECODER_TYPE = 1;
 
-    localparam PKT_TRANS_WRITE = 56;
+    localparam PKT_TRANS_WRITE = 54;
-    localparam PKT_TRANS_READ  = 57;
+    localparam PKT_TRANS_READ  = 55;
 
     localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
     localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@@ -158,7 +158,7 @@ module niosII_mm_interconnect_0_router_004
     assign src_valid         = sink_valid;
     assign src_startofpacket = sink_startofpacket;
     assign src_endofpacket   = sink_endofpacket;
-    wire [7-1 : 0] default_src_channel;
+    wire [6-1 : 0] default_src_channel;
 
 
 
@@ -190,11 +190,11 @@ module niosII_mm_interconnect_0_router_004
 
 
         if (destid == 0 ) begin
-            src_channel = 7'b01;
+            src_channel = 6'b01;
         end
 
         if (destid == 1  && read_transaction) begin
-            src_channel = 7'b10;
+            src_channel = 6'b10;
         end
 
 

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv

@@ -28,8 +28,8 @@
 // ------------------------------------------
 // Generation parameters:
 //   output_name:         niosII_mm_interconnect_0_rsp_demux
-//   ST_DATA_W:           94
+//   ST_DATA_W:           92
-//   ST_CHANNEL_W:        7
+//   ST_CHANNEL_W:        6
 //   NUM_OUTPUTS:         1
 //   VALID_WIDTH:         1
 // ------------------------------------------
@@ -46,8 +46,8 @@ module niosII_mm_interconnect_0_rsp_demux
     // Sink
     // -------------------
     input  [1-1      : 0]   sink_valid,
-    input  [94-1    : 0]   sink_data, // ST_DATA_W=94
+    input  [92-1    : 0]   sink_data, // ST_DATA_W=92
-    input  [7-1 : 0]   sink_channel, // ST_CHANNEL_W=7
+    input  [6-1 : 0]   sink_channel, // ST_CHANNEL_W=6
     input                         sink_startofpacket,
     input                         sink_endofpacket,
     output                        sink_ready,
@@ -56,8 +56,8 @@ module niosII_mm_interconnect_0_rsp_demux
     // Sources 
     // -------------------
     output reg                      src0_valid,
-    output reg [94-1    : 0] src0_data, // ST_DATA_W=94
+    output reg [92-1    : 0] src0_data, // ST_DATA_W=92
-    output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
+    output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
     output reg                      src0_startofpacket,
     output reg                      src0_endofpacket,
     input                           src0_ready,
@@ -94,7 +94,7 @@ module niosII_mm_interconnect_0_rsp_demux
     // -------------------
     assign ready_vector[0] = src0_ready;
 
-    assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
+    assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
 
 endmodule
 

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv

@@ -39,13 +39,13 @@
 // ------------------------------------------
 // Generation parameters:
 //   output_name:         niosII_mm_interconnect_0_rsp_mux
-//   NUM_INPUTS:          6
+//   NUM_INPUTS:          5
-//   ARBITRATION_SHARES:  1 1 1 1 1 1
+//   ARBITRATION_SHARES:  1 1 1 1 1
 //   ARBITRATION_SCHEME   "no-arb"
 //   PIPELINE_ARB:        0
-//   PKT_TRANS_LOCK:      58 (arbitration locking enabled)
+//   PKT_TRANS_LOCK:      56 (arbitration locking enabled)
-//   ST_DATA_W:           94
+//   ST_DATA_W:           92
-//   ST_CHANNEL_W:        7
+//   ST_CHANNEL_W:        6
 // ------------------------------------------
 
 module niosII_mm_interconnect_0_rsp_mux
@@ -54,54 +54,47 @@ module niosII_mm_interconnect_0_rsp_mux
     // Sinks
     // ----------------------
     input                       sink0_valid,
-    input [94-1   : 0]  sink0_data,
+    input [92-1   : 0]  sink0_data,
-    input [7-1: 0]  sink0_channel,
+    input [6-1: 0]  sink0_channel,
     input                       sink0_startofpacket,
     input                       sink0_endofpacket,
     output                      sink0_ready,
 
     input                       sink1_valid,
-    input [94-1   : 0]  sink1_data,
+    input [92-1   : 0]  sink1_data,
-    input [7-1: 0]  sink1_channel,
+    input [6-1: 0]  sink1_channel,
     input                       sink1_startofpacket,
     input                       sink1_endofpacket,
     output                      sink1_ready,
 
     input                       sink2_valid,
-    input [94-1   : 0]  sink2_data,
+    input [92-1   : 0]  sink2_data,
-    input [7-1: 0]  sink2_channel,
+    input [6-1: 0]  sink2_channel,
     input                       sink2_startofpacket,
     input                       sink2_endofpacket,
     output                      sink2_ready,
 
     input                       sink3_valid,
-    input [94-1   : 0]  sink3_data,
+    input [92-1   : 0]  sink3_data,
-    input [7-1: 0]  sink3_channel,
+    input [6-1: 0]  sink3_channel,
     input                       sink3_startofpacket,
     input                       sink3_endofpacket,
     output                      sink3_ready,
 
     input                       sink4_valid,
-    input [94-1   : 0]  sink4_data,
+    input [92-1   : 0]  sink4_data,
-    input [7-1: 0]  sink4_channel,
+    input [6-1: 0]  sink4_channel,
     input                       sink4_startofpacket,
     input                       sink4_endofpacket,
     output                      sink4_ready,
 
-    input                       sink5_valid,
-    input [94-1   : 0]  sink5_data,
-    input [7-1: 0]  sink5_channel,
-    input                       sink5_startofpacket,
-    input                       sink5_endofpacket,
-    output                      sink5_ready,
-
 
     // ----------------------
     // Source
     // ----------------------
     output                      src_valid,
-    output [94-1    : 0] src_data,
+    output [92-1    : 0] src_data,
-    output [7-1 : 0] src_channel,
+    output [6-1 : 0] src_channel,
     output                      src_startofpacket,
     output                      src_endofpacket,
     input                       src_ready,
@@ -112,13 +105,13 @@ module niosII_mm_interconnect_0_rsp_mux
     input clk,
     input reset
 );
-    localparam PAYLOAD_W        = 94 + 7 + 2;
+    localparam PAYLOAD_W        = 92 + 6 + 2;
-    localparam NUM_INPUTS       = 6;
+    localparam NUM_INPUTS       = 5;
     localparam SHARE_COUNTER_W  = 1;
     localparam PIPELINE_ARB     = 0;
-    localparam ST_DATA_W        = 94;
+    localparam ST_DATA_W        = 92;
-    localparam ST_CHANNEL_W     = 7;
+    localparam ST_CHANNEL_W     = 6;
-    localparam PKT_TRANS_LOCK   = 58;
+    localparam PKT_TRANS_LOCK   = 56;
 
     // ------------------------------------------
     // Signals
@@ -138,14 +131,12 @@ module niosII_mm_interconnect_0_rsp_mux
     wire [PAYLOAD_W - 1 : 0] sink2_payload;
     wire [PAYLOAD_W - 1 : 0] sink3_payload;
     wire [PAYLOAD_W - 1 : 0] sink4_payload;
-    wire [PAYLOAD_W - 1 : 0] sink5_payload;
 
     assign valid[0] = sink0_valid;
     assign valid[1] = sink1_valid;
     assign valid[2] = sink2_valid;
     assign valid[3] = sink3_valid;
     assign valid[4] = sink4_valid;
-    assign valid[5] = sink5_valid;
 
 
     // ------------------------------------------
@@ -155,12 +146,11 @@ module niosII_mm_interconnect_0_rsp_mux
     // ------------------------------------------
     reg [NUM_INPUTS - 1 : 0] lock;
     always @* begin
-      lock[0] = sink0_data[58];
+      lock[0] = sink0_data[56];
-      lock[1] = sink1_data[58];
+      lock[1] = sink1_data[56];
-      lock[2] = sink2_data[58];
+      lock[2] = sink2_data[56];
-      lock[3] = sink3_data[58];
+      lock[3] = sink3_data[56];
-      lock[4] = sink4_data[58];
+      lock[4] = sink4_data[56];
-      lock[5] = sink5_data[58];
     end
 
     assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
@@ -196,13 +186,11 @@ module niosII_mm_interconnect_0_rsp_mux
     // 2      |      1       |  0
     // 3      |      1       |  0
     // 4      |      1       |  0
-    // 5      |      1       |  0
      wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
      wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
      wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
      wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
      wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
-     wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
 
     // ------------------------------------------
     // Choose the share value corresponding to the grant.
@@ -214,8 +202,7 @@ module niosII_mm_interconnect_0_rsp_mux
     share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
     share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
     share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
-    share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
+    share_4 & { SHARE_COUNTER_W {next_grant[4]} };
-    share_5 & { SHARE_COUNTER_W {next_grant[5]} };
     end
 
     // ------------------------------------------
@@ -287,14 +274,11 @@ module niosII_mm_interconnect_0_rsp_mux
 
     wire final_packet_4 = 1'b1;
 
-    wire final_packet_5 = 1'b1;
-
 
     // ------------------------------------------
     // Concatenate all final_packet signals (wire or reg) into a handy vector.
     // ------------------------------------------
     wire [NUM_INPUTS - 1 : 0] final_packet = {
-    final_packet_5,
     final_packet_4,
     final_packet_3,
     final_packet_2,
@@ -388,7 +372,6 @@ module niosII_mm_interconnect_0_rsp_mux
     assign sink2_ready = src_ready && grant[2];
     assign sink3_ready = src_ready && grant[3];
     assign sink4_ready = src_ready && grant[4];
-    assign sink5_ready = src_ready && grant[5];
 
     assign src_valid = |(grant & valid);
 
@@ -398,8 +381,7 @@ module niosII_mm_interconnect_0_rsp_mux
       sink1_payload & {PAYLOAD_W {grant[1]} } |
       sink2_payload & {PAYLOAD_W {grant[2]} } |
       sink3_payload & {PAYLOAD_W {grant[3]} } |
-      sink4_payload & {PAYLOAD_W {grant[4]} } |
+      sink4_payload & {PAYLOAD_W {grant[4]} };
-      sink5_payload & {PAYLOAD_W {grant[5]} };
     end
 
     // ------------------------------------------
@@ -416,8 +398,6 @@ module niosII_mm_interconnect_0_rsp_mux
     sink3_startofpacket,sink3_endofpacket};
     assign sink4_payload = {sink4_channel,sink4_data,
     sink4_startofpacket,sink4_endofpacket};
-    assign sink5_payload = {sink5_channel,sink5_data,
-    sink5_startofpacket,sink5_endofpacket};
 
     assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
 endmodule

Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv

@@ -43,9 +43,9 @@
 //   ARBITRATION_SHARES:  1 1
 //   ARBITRATION_SCHEME   "no-arb"
 //   PIPELINE_ARB:        0
-//   PKT_TRANS_LOCK:      58 (arbitration locking enabled)
+//   PKT_TRANS_LOCK:      56 (arbitration locking enabled)
-//   ST_DATA_W:           94
+//   ST_DATA_W:           92
-//   ST_CHANNEL_W:        7
+//   ST_CHANNEL_W:        6
 // ------------------------------------------
 
 module niosII_mm_interconnect_0_rsp_mux_001
@@ -54,15 +54,15 @@ module niosII_mm_interconnect_0_rsp_mux_001
     // Sinks
     // ----------------------
     input                       sink0_valid,
-    input [94-1   : 0]  sink0_data,
+    input [92-1   : 0]  sink0_data,
-    input [7-1: 0]  sink0_channel,
+    input [6-1: 0]  sink0_channel,
     input                       sink0_startofpacket,
     input                       sink0_endofpacket,
     output                      sink0_ready,
 
     input                       sink1_valid,
-    input [94-1   : 0]  sink1_data,
+    input [92-1   : 0]  sink1_data,
-    input [7-1: 0]  sink1_channel,
+    input [6-1: 0]  sink1_channel,
     input                       sink1_startofpacket,
     input                       sink1_endofpacket,
     output                      sink1_ready,
@@ -72,8 +72,8 @@ module niosII_mm_interconnect_0_rsp_mux_001
     // Source
     // ----------------------
     output                      src_valid,
-    output [94-1    : 0] src_data,
+    output [92-1    : 0] src_data,
-    output [7-1 : 0] src_channel,
+    output [6-1 : 0] src_channel,
     output                      src_startofpacket,
     output                      src_endofpacket,
     input                       src_ready,
@@ -84,13 +84,13 @@ module niosII_mm_interconnect_0_rsp_mux_001
     input clk,
     input reset
 );
-    localparam PAYLOAD_W        = 94 + 7 + 2;
+    localparam PAYLOAD_W        = 92 + 6 + 2;
     localparam NUM_INPUTS       = 2;
     localparam SHARE_COUNTER_W  = 1;
     localparam PIPELINE_ARB     = 0;
-    localparam ST_DATA_W        = 94;
+    localparam ST_DATA_W        = 92;
-    localparam ST_CHANNEL_W     = 7;
+    localparam ST_CHANNEL_W     = 6;
-    localparam PKT_TRANS_LOCK   = 58;
+    localparam PKT_TRANS_LOCK   = 56;
 
     // ------------------------------------------
     // Signals
@@ -119,8 +119,8 @@ module niosII_mm_interconnect_0_rsp_mux_001
     // ------------------------------------------
     reg [NUM_INPUTS - 1 : 0] lock;
     always @* begin
-      lock[0] = sink0_data[58];
+      lock[0] = sink0_data[56];
-      lock[1] = sink1_data[58];
+      lock[1] = sink1_data[56];
     end
 
     assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));

Top/niosII/testbench/niosII.html

@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2023.01.17.19:01:29</td>
+    <td class="l">2023.01.27.19:00:16</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -100,8 +100,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
      <a href="#module_mem"><b>mem</b>
      </a> altera_avalon_onchip_memory2 18.1
      <br/>&#160;&#160;
-     <a href="#module_sem"><b>sem</b>
+     <a href="#module_sigdel_0"><b>sigdel_0</b>
-     </a> sem 1.1
+     </a> sigdel 1.0
      <br/>&#160;&#160;
      <a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
      </a> altera_avalon_timer 18.1</span>
@@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slaveb">avalon_jtag_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021068</td>
+    <td class="addr"><span style="color:#989898">0x</span>00021020</td>
     <td class="empty"></td>
    </tr>
    <tr>
@@ -167,20 +167,15 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slavemodule">&#160;
-     <a href="#module_sem"><b>sem</b>
+     <a href="#module_sigdel_0"><b>sigdel_0</b>
      </a>
     </td>
     <td class="empty"></td>
     <td class="empty"></td>
    </tr>
    <tr>
-    <td class="slavem">ctl_slave&#160;</td>
+    <td class="slaveb">avalon_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021060</td>
+    <td class="addr"><span style="color:#989898">0x</span>00021028</td>
-    <td class="empty"></td>
-   </tr>
-   <tr>
-    <td class="slavem">ram_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021000</td>
     <td class="empty"></td>
    </tr>
    <tr>
@@ -193,7 +188,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slaveb">s1&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021040</td>
+    <td class="addr"><span style="color:#989898">0x</span>00021000</td>
     <td class="empty"></td>
    </tr>
   </table>
@@ -256,7 +251,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        <a href="#module_clk">clk</a>
       </td>
       <td class="from">clk&#160;&#160;</td>
-      <td class="main" rowspan="31">cpu</td>
+      <td class="main" rowspan="29">cpu</td>
      </tr>
      <tr>
       <td class="to">&#160;&#160;clk</td>
@@ -307,24 +302,14 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <td></td>
       <td></td>
       <td class="from">data_master&#160;&#160;</td>
-      <td class="neighbor" rowspan="6">
+      <td class="neighbor" rowspan="4">
-       <a href="#module_sem">sem</a>
+       <a href="#module_sigdel_0">sigdel_0</a>
       </td>
      </tr>
      <tr>
       <td></td>
       <td></td>
-      <td class="to">&#160;&#160;ctl_slave</td>
+      <td class="to">&#160;&#160;avalon_slave</td>
-     </tr>
-     <tr>
-      <td></td>
-      <td></td>
-      <td class="from">data_master&#160;&#160;</td>
-     </tr>
-     <tr>
-      <td></td>
-      <td></td>
-      <td class="to">&#160;&#160;ram_slave</td>
      </tr>
      <tr>
       <td></td>
@@ -334,7 +319,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
      <tr>
       <td></td>
       <td></td>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
      <tr style="height:6px">
       <td></td>
@@ -1107,7 +1092,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">dataSlaveMapParam</td>
-        <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
+        <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21020' end='0x21028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='sigdel_0.avalon_slave' start='0x21028' end='0x2102C' type='sigdel.avalon_slave' /&gt;&lt;/address-map&gt;</td>
        </tr>
        <tr>
         <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@@ -1763,34 +1748,28 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
     </tr>
    </table>
   </div>
-  <a name="module_sem"> </a>
+  <a name="module_sigdel_0"> </a>
   <div>
    <hr/>
-   <h2>sem</h2>sem v1.1
+   <h2>sigdel_0</h2>sigdel v1.0
    <br/>
    <div class="greydiv">
     <table class="connectionboxes">
      <tr>
-      <td class="neighbor" rowspan="6">
+      <td class="neighbor" rowspan="4">
        <a href="#module_cpu">cpu</a>
       </td>
       <td class="from">data_master&#160;&#160;</td>
-      <td class="main" rowspan="11">sem</td>
+      <td class="main" rowspan="9">sigdel_0</td>
      </tr>
      <tr>
-      <td class="to">&#160;&#160;ctl_slave</td>
+      <td class="to">&#160;&#160;avalon_slave</td>
-     </tr>
-     <tr>
-      <td class="from">data_master&#160;&#160;</td>
-     </tr>
-     <tr>
-      <td class="to">&#160;&#160;ram_slave</td>
      </tr>
      <tr>
       <td class="from">debug_reset_request&#160;&#160;</td>
      </tr>
      <tr>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
      <tr style="height:6px">
       <td></td>
@@ -1808,7 +1787,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <td class="from">clk_reset&#160;&#160;</td>
      </tr>
      <tr>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
     </table>
    </div>
@@ -1820,8 +1799,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <h2>Parameters</h2>
       <table>
        <tr>
-        <td class="parametername">m</td>
+        <td class="parametername">PHACC_WIDTH</td>
-        <td class="parametervalue">32</td>
+        <td class="parametervalue">14</td>
        </tr>
        <tr>
         <td class="parametername">deviceFamily</td>
@@ -2039,7 +2018,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   <table class="blueBar">
    <tr>
     <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0.01 seconds</td>
+    <td class="r">rendering took 0.03 seconds</td>
    </tr>
   </table>
  </body>

Top/niosII/testbench/niosII_tb.html

@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   </table>
   <table class="blueBar">
    <tr>
-    <td class="l">2023.01.17.19:01:31</td>
+    <td class="l">2023.01.27.19:00:18</td>
     <td class="r">Datasheet</td>
    </tr>
   </table>
@@ -100,8 +100,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
      <a href="#module_niosII_inst_mem"><b>niosII_inst_mem</b>
      </a> altera_avalon_onchip_memory2 18.1
      <br/>&#160;&#160;
-     <a href="#module_niosII_inst_sem"><b>niosII_inst_sem</b>
+     <a href="#module_niosII_inst_sigdel_0"><b>niosII_inst_sigdel_0</b>
-     </a> sem 1.1
+     </a> sigdel 1.0
      <br/>&#160;&#160;
      <a href="#module_niosII_inst_sys_clk_timer"><b>niosII_inst_sys_clk_timer</b>
      </a> altera_avalon_timer 18.1</span>
@@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slaveb">avalon_jtag_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021068</td>
+    <td class="addr"><span style="color:#989898">0x</span>00021020</td>
     <td class="empty"></td>
    </tr>
    <tr>
@@ -167,20 +167,15 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slavemodule">&#160;
-     <a href="#module_niosII_inst_sem"><b>niosII_inst_sem</b>
+     <a href="#module_niosII_inst_sigdel_0"><b>niosII_inst_sigdel_0</b>
      </a>
     </td>
     <td class="empty"></td>
     <td class="empty"></td>
    </tr>
    <tr>
-    <td class="slavem">ctl_slave&#160;</td>
+    <td class="slaveb">avalon_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021060</td>
+    <td class="addr"><span style="color:#989898">0x</span>00021028</td>
-    <td class="empty"></td>
-   </tr>
-   <tr>
-    <td class="slavem">ram_slave&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021000</td>
     <td class="empty"></td>
    </tr>
    <tr>
@@ -193,7 +188,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
    </tr>
    <tr>
     <td class="slaveb">s1&#160;</td>
-    <td class="addr"><span style="color:#989898">0x</span>00021040</td>
+    <td class="addr"><span style="color:#989898">0x</span>00021000</td>
     <td class="empty"></td>
    </tr>
   </table>
@@ -211,7 +206,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <table>
        <tr>
         <td class="parametername">AUTO_GENERATION_ID</td>
-        <td class="parametervalue">1673967691</td>
+        <td class="parametervalue">1674831618</td>
        </tr>
        <tr>
         <td class="parametername">AUTO_UNIQUE_ID</td>
@@ -398,7 +393,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <td></td>
       <td class="from">clk&#160;&#160;</td>
       <td class="neighbor" rowspan="4">
-       <a href="#module_niosII_inst_sem">niosII_inst_sem</a>
+       <a href="#module_niosII_inst_sigdel_0">niosII_inst_sigdel_0</a>
       </td>
      </tr>
      <tr>
@@ -414,7 +409,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
      <tr>
       <td></td>
       <td></td>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
     </table>
    </div>
@@ -472,7 +467,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        <a href="#module_niosII_inst_clk">niosII_inst_clk</a>
       </td>
       <td class="from">clk&#160;&#160;</td>
-      <td class="main" rowspan="31">niosII_inst_cpu</td>
+      <td class="main" rowspan="29">niosII_inst_cpu</td>
      </tr>
      <tr>
       <td class="to">&#160;&#160;clk</td>
@@ -523,24 +518,14 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <td></td>
       <td></td>
       <td class="from">data_master&#160;&#160;</td>
-      <td class="neighbor" rowspan="6">
+      <td class="neighbor" rowspan="4">
-       <a href="#module_niosII_inst_sem">niosII_inst_sem</a>
+       <a href="#module_niosII_inst_sigdel_0">niosII_inst_sigdel_0</a>
       </td>
      </tr>
      <tr>
       <td></td>
       <td></td>
-      <td class="to">&#160;&#160;ctl_slave</td>
+      <td class="to">&#160;&#160;avalon_slave</td>
-     </tr>
-     <tr>
-      <td></td>
-      <td></td>
-      <td class="from">data_master&#160;&#160;</td>
-     </tr>
-     <tr>
-      <td></td>
-      <td></td>
-      <td class="to">&#160;&#160;ram_slave</td>
      </tr>
      <tr>
       <td></td>
@@ -550,7 +535,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
      <tr>
       <td></td>
       <td></td>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
      <tr style="height:6px">
       <td></td>
@@ -1323,7 +1308,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
        </tr>
        <tr>
         <td class="parametername">dataSlaveMapParam</td>
-        <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sem.ram_slave' start='0x21000' end='0x21040' type='sem.ram_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21040' end='0x21060' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ctl_slave' start='0x21060' end='0x21068' type='sem.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21068' end='0x21070' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
+        <td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21020' end='0x21028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='sigdel_0.avalon_slave' start='0x21028' end='0x2102C' type='sigdel.avalon_slave' /&gt;&lt;/address-map&gt;</td>
        </tr>
        <tr>
         <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@@ -1979,34 +1964,28 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
     </tr>
    </table>
   </div>
-  <a name="module_niosII_inst_sem"> </a>
+  <a name="module_niosII_inst_sigdel_0"> </a>
   <div>
    <hr/>
-   <h2>niosII_inst_sem</h2>sem v1.1
+   <h2>niosII_inst_sigdel_0</h2>sigdel v1.0
    <br/>
    <div class="greydiv">
     <table class="connectionboxes">
      <tr>
-      <td class="neighbor" rowspan="6">
+      <td class="neighbor" rowspan="4">
        <a href="#module_niosII_inst_cpu">niosII_inst_cpu</a>
       </td>
       <td class="from">data_master&#160;&#160;</td>
-      <td class="main" rowspan="11">niosII_inst_sem</td>
+      <td class="main" rowspan="9">niosII_inst_sigdel_0</td>
      </tr>
      <tr>
-      <td class="to">&#160;&#160;ctl_slave</td>
+      <td class="to">&#160;&#160;avalon_slave</td>
-     </tr>
-     <tr>
-      <td class="from">data_master&#160;&#160;</td>
-     </tr>
-     <tr>
-      <td class="to">&#160;&#160;ram_slave</td>
      </tr>
      <tr>
       <td class="from">debug_reset_request&#160;&#160;</td>
      </tr>
      <tr>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
      <tr style="height:6px">
       <td></td>
@@ -2024,7 +2003,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <td class="from">clk_reset&#160;&#160;</td>
      </tr>
      <tr>
-      <td class="to">&#160;&#160;reset_n</td>
+      <td class="to">&#160;&#160;reset_sink</td>
      </tr>
     </table>
    </div>
@@ -2036,8 +2015,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
       <h2>Parameters</h2>
       <table>
        <tr>
-        <td class="parametername">m</td>
+        <td class="parametername">PHACC_WIDTH</td>
-        <td class="parametervalue">32</td>
+        <td class="parametervalue">14</td>
        </tr>
        <tr>
         <td class="parametername">deviceFamily</td>
@@ -2360,7 +2339,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
   <table class="blueBar">
    <tr>
     <td class="l">generation took 0.00 seconds</td>
-    <td class="r">rendering took 0.02 seconds</td>
+    <td class="r">rendering took 0.03 seconds</td>
    </tr>
   </table>
  </body>

Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v

@@ -8,16 +8,11 @@ module niosII_tb (
 
 	wire    niosii_inst_clk_bfm_clk_clk;       // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
 	wire    niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
-    reg     train;
-    wire    red, yellow, green;
 
 	niosII niosii_inst (
 		.clk_clk                          (niosii_inst_clk_bfm_clk_clk),       //         clk.clk
-                        .reset_reset_n     (niosii_inst_reset_bfm_reset_reset), //      reset.reset_n
+		.conduit_end_writeresponsevalid_n (),                                  // conduit_end.writeresponsevalid_n
-                        .sem_export_train  (train),                             // sem_export.train
+		.reset_reset_n                    (niosii_inst_reset_bfm_reset_reset)  //       reset.reset_n
-                        .sem_export_red    (red),                               //           .red
-                        .sem_export_yellow (yellow),                            //           .yellow
-                        .sem_export_green  (green)                              //           .green
 	);
 
 	altera_avalon_clock_source #(
@@ -34,22 +29,5 @@ module niosII_tb (
 		.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
 		.clk   (niosii_inst_clk_bfm_clk_clk)        //   clk.clk
 	);
-    initial begin
-        train = 0;
-        wait (niosii_inst_reset_bfm_reset_reset);
-        forever begin
-            wait ({red,yellow,green}==3'b001);
-            repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk);
-            repeat(8) begin
-                train = 1;
-                repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
-                train = 0;
-                wait ({red,yellow,green}==3'b001);
-                repeat (200) @(posedge niosii_inst_clk_bfm_clk_clk);
-            end
-        end
-    end
-
-
 
 endmodule

Top/niosII_tb.csv

@@ -1,12 +1,12 @@
-# system info niosII_tb on 2023.01.17.19:01:35
+# system info niosII_tb on 2023.01.27.19:00:20
 system_info:
 name,value
 DEVICE,EP4CE115F29C7
 DEVICE_FAMILY,Cyclone IV E
-GENERATION_ID,1673967691
+GENERATION_ID,1674831618
 #
 #
-# Files generated for niosII_tb on 2023.01.17.19:01:35
+# Files generated for niosII_tb on 2023.01.27.19:00:20
 files:
 filepath,kind,attributes,module,is_top
 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
@@ -19,54 +19,6 @@ niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cp
 niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
 niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
 niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
-niosII/testbench/niosII_tb/simulation/submodules/dec.sv,SYSTEM_VERILOG,,dec,false
-niosII/testbench/niosII_tb/simulation/submodules/periodram.v,VERILOG,,dec,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v,VERILOG,,niosII_sys_clk_timer,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v,VERILOG,,niosII_mm_interconnect_0,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VERILOG,,niosII_irq_mapper,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_001,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_002,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_004,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_router_008,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_demux_001,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_cmd_mux_002,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_demux,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
-niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_rsp_mux_001,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter,false
-niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0,false
 #
 # Map from instance-path to kind of module
 instances:
@@ -76,75 +28,9 @@ niosII_tb.niosII_inst.cpu,niosII_cpu
 niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
 niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
 niosII_tb.niosII_inst.mem,niosII_mem
-niosII_tb.niosII_inst.sem,dec
+niosII_tb.niosII_inst.sigdel_0,niosII_sigdel_0
 niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
 niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_translator,altera_merlin_master_translator
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_translator,altera_merlin_master_translator
-niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_translator,altera_merlin_slave_translator
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_data_master_agent,altera_merlin_master_agent
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_instruction_master_agent,altera_merlin_master_agent
-niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent,altera_merlin_slave_agent
-niosII_tb.niosII_inst.mm_interconnect_0.jtag_uart_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ctl_slave_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.cpu_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.sem_ram_slave_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.sys_clk_timer_s1_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s2_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.mem_s1_agent_rsp_fifo,altera_avalon_sc_fifo
-niosII_tb.niosII_inst.mm_interconnect_0.router,niosII_mm_interconnect_0_router
-niosII_tb.niosII_inst.mm_interconnect_0.router_001,niosII_mm_interconnect_0_router_001
-niosII_tb.niosII_inst.mm_interconnect_0.router_002,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_003,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_005,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_006,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_007,niosII_mm_interconnect_0_router_002
-niosII_tb.niosII_inst.mm_interconnect_0.router_004,niosII_mm_interconnect_0_router_004
-niosII_tb.niosII_inst.mm_interconnect_0.router_008,niosII_mm_interconnect_0_router_008
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux,niosII_mm_interconnect_0_cmd_demux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_demux_001,niosII_mm_interconnect_0_cmd_demux_001
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_002,niosII_mm_interconnect_0_cmd_demux_001
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_001,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_003,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_004,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_005,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_006,niosII_mm_interconnect_0_cmd_mux
-niosII_tb.niosII_inst.mm_interconnect_0.cmd_mux_002,niosII_mm_interconnect_0_cmd_mux_002
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_001,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_003,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_004,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_005,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_demux_006,niosII_mm_interconnect_0_rsp_demux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux,niosII_mm_interconnect_0_rsp_mux
-niosII_tb.niosII_inst.mm_interconnect_0.rsp_mux_001,niosII_mm_interconnect_0_rsp_mux_001
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_001.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_002.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_003.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_004.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_005.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006,niosII_mm_interconnect_0_avalon_st_adapter
-niosII_tb.niosII_inst.mm_interconnect_0.avalon_st_adapter_006.error_adapter_0,niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0
 niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
 niosII_tb.niosII_inst.rst_controller,altera_reset_controller
 niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source

Top/niosII_tb.spd

@@ -5,198 +5,6 @@
    type="SYSTEM_VERILOG"
    library="altera_common_sv_packages"
    systemVerilogPackageName="avalon_vip_verbosity_pkg" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv"
-   type="SYSTEM_VERILOG"
-   library="error_adapter_0" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v"
-   type="VERILOG"
-   library="avalon_st_adapter" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv"
-   type="SYSTEM_VERILOG"
-   library="rsp_mux_001" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
-   type="SYSTEM_VERILOG"
-   library="rsp_mux_001" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv"
-   type="SYSTEM_VERILOG"
-   library="rsp_mux" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
-   type="SYSTEM_VERILOG"
-   library="rsp_mux" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv"
-   type="SYSTEM_VERILOG"
-   library="rsp_demux" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv"
-   type="SYSTEM_VERILOG"
-   library="cmd_mux_002" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
-   type="SYSTEM_VERILOG"
-   library="cmd_mux_002" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv"
-   type="SYSTEM_VERILOG"
-   library="cmd_mux" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv"
-   type="SYSTEM_VERILOG"
-   library="cmd_mux" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv"
-   type="SYSTEM_VERILOG"
-   library="cmd_demux_001" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv"
-   type="SYSTEM_VERILOG"
-   library="cmd_demux" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv"
-   type="SYSTEM_VERILOG"
-   library="router_008" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv"
-   type="SYSTEM_VERILOG"
-   library="router_004" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv"
-   type="SYSTEM_VERILOG"
-   library="router_002" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv"
-   type="SYSTEM_VERILOG"
-   library="router_001" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv"
-   type="SYSTEM_VERILOG"
-   library="router" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v"
-   type="VERILOG"
-   library="jtag_uart_avalon_jtag_slave_agent_rsp_fifo" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv"
-   type="SYSTEM_VERILOG"
-   library="jtag_uart_avalon_jtag_slave_agent" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv"
-   type="SYSTEM_VERILOG"
-   library="jtag_uart_avalon_jtag_slave_agent" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv"
-   type="SYSTEM_VERILOG"
-   library="cpu_data_master_agent" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv"
-   type="SYSTEM_VERILOG"
-   library="jtag_uart_avalon_jtag_slave_translator" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv"
-   type="SYSTEM_VERILOG"
-   library="cpu_data_master_translator" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
-   type="VERILOG"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat"
-   type="DAT"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat"
-   type="DAT"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
-   type="MIF"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat"
-   type="DAT"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
-   type="OTHER"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex"
-   type="HEX"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
-   type="VERILOG"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"
-   type="VERILOG"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif"
-   type="MIF"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
-   type="VERILOG"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
-   type="SDC"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"
-   type="VERILOG"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex"
-   type="HEX"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif"
-   type="MIF"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex"
-   type="HEX"
-   library="cpu" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v"
-   type="VERILOG"
-   library="rst_controller" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v"
-   type="VERILOG"
-   library="rst_controller" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc"
-   type="SDC"
-   library="rst_controller" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv"
-   type="SYSTEM_VERILOG"
-   library="irq_mapper" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v"
-   type="VERILOG"
-   library="mm_interconnect_0" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v"
-   type="VERILOG"
-   library="sys_clk_timer" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/dec.sv"
-   type="SYSTEM_VERILOG"
-   library="sem" />
- <file
-   path="niosII/testbench/niosII_tb/simulation/submodules/periodram.v"
-   type="VERILOG"
-   library="sem" />
  <file
    path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex"
    type="HEX"

Top/semafor.qsf

@@ -37,26 +37,20 @@
 
 
 set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE115F29C7
+set_global_assignment -name DEVICE EP4CE15F23C8
 set_global_assignment -name TOP_LEVEL_ENTITY top
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:55  OCTOBER 18, 2022"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
 set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
 set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_location_assignment PIN_Y2 -to clk
-set_location_assignment PIN_M23 -to train
-set_location_assignment PIN_G19 -to yellow
-set_location_assignment PIN_F19 -to red
-set_location_assignment PIN_G21 -to green
 
 set_global_assignment -name SYSTEMVERILOG_FILE top.sv
 set_global_assignment -name QIP_FILE niosII/synthesis/niosII.qip
@@ -64,4 +58,9 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_location_assignment PIN_T2 -to CLOCK_50
+set_location_assignment PIN_E3 -to LEDG[0]
+set_location_assignment PIN_C21 -to FOUTA
+set_location_assignment PIN_E4 -to nreset
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Top/sigdel_hw.tcl

@@ -0,0 +1,143 @@
+# TCL File Generated by Component Editor 18.1
+# Tue Feb 07 16:48:35 MSK 2023
+# DO NOT MODIFY
+
+
+# 
+# sigdel "Sigma-Delta Modulator" v1.0
+#  2023.02.07.16:48:35
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module sigdel
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME sigdel
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "User Logic"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME "Sigma-Delta Modulator"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL sigdel
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file phacc.sv SYSTEM_VERILOG PATH ../HDL/phacc.sv
+add_fileset_file sdmod.sv SYSTEM_VERILOG PATH ../HDL/sdmod.sv
+add_fileset_file sigdel.sv SYSTEM_VERILOG PATH ../HDL/sigdel.sv TOP_LEVEL_FILE
+add_fileset_file sinelut.v VERILOG PATH ../HDL/IP/sinelut.v
+add_fileset_file sine256.mif MIF PATH ../HDL/IP/sine256.mif
+
+
+# 
+# parameters
+# 
+add_parameter PHACC_WIDTH INTEGER 14
+set_parameter_property PHACC_WIDTH DEFAULT_VALUE 14
+set_parameter_property PHACC_WIDTH DISPLAY_NAME PHACC_WIDTH
+set_parameter_property PHACC_WIDTH TYPE INTEGER
+set_parameter_property PHACC_WIDTH UNITS None
+set_parameter_property PHACC_WIDTH ALLOWED_RANGES -2147483648:2147483647
+set_parameter_property PHACC_WIDTH HDL_PARAMETER true
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink clr_n reset_n Input 1
+
+
+# 
+# connection point conduit_end
+# 
+add_interface conduit_end conduit end
+set_interface_property conduit_end associatedClock ""
+set_interface_property conduit_end associatedReset ""
+set_interface_property conduit_end ENABLED true
+set_interface_property conduit_end EXPORT_OF ""
+set_interface_property conduit_end PORT_NAME_MAP ""
+set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end fout writeresponsevalid_n Output 1
+
+
+# 
+# connection point avalon_slave
+# 
+add_interface avalon_slave avalon end
+set_interface_property avalon_slave addressUnits WORDS
+set_interface_property avalon_slave associatedClock clock
+set_interface_property avalon_slave associatedReset reset_sink
+set_interface_property avalon_slave bitsPerSymbol 8
+set_interface_property avalon_slave burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave burstcountUnits WORDS
+set_interface_property avalon_slave explicitAddressSpan 0
+set_interface_property avalon_slave holdTime 0
+set_interface_property avalon_slave linewrapBursts false
+set_interface_property avalon_slave maximumPendingReadTransactions 0
+set_interface_property avalon_slave maximumPendingWriteTransactions 0
+set_interface_property avalon_slave readLatency 0
+set_interface_property avalon_slave readWaitTime 1
+set_interface_property avalon_slave setupTime 0
+set_interface_property avalon_slave timingUnits Cycles
+set_interface_property avalon_slave writeWaitTime 0
+set_interface_property avalon_slave ENABLED true
+set_interface_property avalon_slave EXPORT_OF ""
+set_interface_property avalon_slave PORT_NAME_MAP ""
+set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave wr_n write_n Input 1
+add_interface_port avalon_slave wr_data writedata Input 32
+set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
+

Top/sigdel_hw.tcl~

@@ -0,0 +1,143 @@
+# TCL File Generated by Component Editor 18.1
+# Fri Jan 27 18:48:38 MSK 2023
+# DO NOT MODIFY
+
+
+# 
+# sigdel "Sigma-Delta Modulator" v1.0
+#  2023.01.27.18:48:38
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module sigdel
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME sigdel
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP "User Logic"
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME "Sigma-Delta Modulator"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL sigdel
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file phacc.sv SYSTEM_VERILOG PATH ../HDL/phacc.sv
+add_fileset_file sdmod.sv SYSTEM_VERILOG PATH ../HDL/sdmod.sv
+add_fileset_file sigdel.sv SYSTEM_VERILOG PATH ../HDL/sigdel.sv TOP_LEVEL_FILE
+add_fileset_file sinelut.v VERILOG PATH ../HDL/IP/sinelut.v
+add_fileset_file sine256.mif MIF PATH ../HDL/IP/sine256.mif
+
+
+# 
+# parameters
+# 
+add_parameter PHACC_WIDTH INTEGER 14
+set_parameter_property PHACC_WIDTH DEFAULT_VALUE 14
+set_parameter_property PHACC_WIDTH DISPLAY_NAME PHACC_WIDTH
+set_parameter_property PHACC_WIDTH TYPE INTEGER
+set_parameter_property PHACC_WIDTH UNITS None
+set_parameter_property PHACC_WIDTH ALLOWED_RANGES -2147483648:2147483647
+set_parameter_property PHACC_WIDTH HDL_PARAMETER true
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink clr_n reset_n Input 1
+
+
+# 
+# connection point conduit_end
+# 
+add_interface conduit_end conduit end
+set_interface_property conduit_end associatedClock ""
+set_interface_property conduit_end associatedReset ""
+set_interface_property conduit_end ENABLED true
+set_interface_property conduit_end EXPORT_OF ""
+set_interface_property conduit_end PORT_NAME_MAP ""
+set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
+set_interface_property conduit_end SVD_ADDRESS_GROUP ""
+
+add_interface_port conduit_end fout writeresponsevalid_n Output 1
+
+
+# 
+# connection point avalon_slave
+# 
+add_interface avalon_slave avalon end
+set_interface_property avalon_slave addressUnits WORDS
+set_interface_property avalon_slave associatedClock clock
+set_interface_property avalon_slave associatedReset reset_sink
+set_interface_property avalon_slave bitsPerSymbol 8
+set_interface_property avalon_slave burstOnBurstBoundariesOnly false
+set_interface_property avalon_slave burstcountUnits WORDS
+set_interface_property avalon_slave explicitAddressSpan 0
+set_interface_property avalon_slave holdTime 0
+set_interface_property avalon_slave linewrapBursts false
+set_interface_property avalon_slave maximumPendingReadTransactions 0
+set_interface_property avalon_slave maximumPendingWriteTransactions 0
+set_interface_property avalon_slave readLatency 0
+set_interface_property avalon_slave readWaitTime 1
+set_interface_property avalon_slave setupTime 0
+set_interface_property avalon_slave timingUnits Cycles
+set_interface_property avalon_slave writeWaitTime 0
+set_interface_property avalon_slave ENABLED true
+set_interface_property avalon_slave EXPORT_OF ""
+set_interface_property avalon_slave PORT_NAME_MAP ""
+set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
+set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
+
+add_interface_port avalon_slave wr_n write_n Input 1
+add_interface_port avalon_slave wr_data writedata Input 32
+set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
+

Top/software/ci_project/.project

@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>ci_project</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.altera.sbtgui.project.makefileBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>com.altera.sbtgui.project.makefileBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUINature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
+	</natures>
+</projectDescription>