Merge branch 'simulation' into lab3 preferring lab3 in conflicts

# Conflicts:
#	Top/niosII.sopcinfo
#	Top/niosII/niosII.html
#	Top/niosII/niosII.xml
#	Top/niosII/synthesis/niosII.debuginfo
#	Top/niosII/synthesis/niosII.qip
#	Top/semafor.qws
This commit is contained in:
Ivan I. Ovchinnikov 2023-01-20 12:59:24 +03:00
commit 83b0f857d3
80 changed files with 14541 additions and 14366 deletions

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@ -83,6 +83,7 @@ module dec
colors <= 3'b001; colors <= 3'b001;
state <= GREEN; state <= GREEN;
end end
if (train) begin if (train) begin
colors <= 3'b100; colors <= 3'b100;
state <= RED; state <= RED;

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@ -0,0 +1,9 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673520674097 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 12 13:51:13 2023 " "Processing started: Thu Jan 12 13:51:13 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673520674097 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674097 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520674098 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673520674253 ""}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"\[\"; expecting an operand sigdel.sv(14) " "Verilog HDL syntax error at sigdel.sv(14) near text: \"\[\"; expecting an operand. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 14 0 0 } } } 0 10170 "Verilog HDL syntax error at %2!s! near text: %1!s!. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number." 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
{ "Error" "EVRFX_VERI_DESIGN_UNIT_IGNORED" "sigdel sigdel.sv(1) " "Ignored design unit \"sigdel\" at sigdel.sv(1) due to previous errors" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 0 0 } } } 0 10112 "Ignored design unit \"%1!s!\" at %2!s! due to previous errors" 0 0 "Analysis & Synthesis" 0 -1 1673520680482 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 0 0 " "Found 0 design units, including 0 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680483 ""}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "923 " "Peak virtual memory: 923 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_END_BANNER_TIME" "Thu Jan 12 13:51:20 2023 " "Processing ended: Thu Jan 12 13:51:20 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:17 " "Total CPU time (on all processors): 00:00:17" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673520680505 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673520680505 ""}

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@ -0,0 +1,5 @@
<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="sigdel">
</PROJECT>
</LOG_ROOT>

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@ -0,0 +1,3 @@
Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Version_Index = 486699264
Creation_Time = Mon Jan 16 21:47:58 2023

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@ -0,0 +1,47 @@
|sigdel
phinc[0] => Add0.IN14
phinc[1] => Add0.IN13
phinc[2] => Add0.IN12
phinc[3] => Add0.IN11
phinc[4] => Add0.IN10
phinc[5] => Add0.IN9
phinc[6] => Add0.IN8
phinc[7] => Add0.IN7
clk => acc[0].CLK
clk => acc[1].CLK
clk => acc[2].CLK
clk => acc[3].CLK
clk => acc[4].CLK
clk => acc[5].CLK
clk => acc[6].CLK
clk => acc[7].CLK
clk => acc[8].CLK
clk => acc[9].CLK
clk => acc[10].CLK
clk => acc[11].CLK
clk => acc[12].CLK
clk => acc[13].CLK
clr_n => acc[0].ACLR
clr_n => acc[1].ACLR
clr_n => acc[2].ACLR
clr_n => acc[3].ACLR
clr_n => acc[4].ACLR
clr_n => acc[5].ACLR
clr_n => acc[6].ACLR
clr_n => acc[7].ACLR
clr_n => acc[8].ACLR
clr_n => acc[9].ACLR
clr_n => acc[10].ACLR
clr_n => acc[11].ACLR
clr_n => acc[12].ACLR
clr_n => acc[13].ACLR
phase[0] <= acc[6].DB_MAX_OUTPUT_PORT_TYPE
phase[1] <= acc[7].DB_MAX_OUTPUT_PORT_TYPE
phase[2] <= acc[8].DB_MAX_OUTPUT_PORT_TYPE
phase[3] <= acc[9].DB_MAX_OUTPUT_PORT_TYPE
phase[4] <= acc[10].DB_MAX_OUTPUT_PORT_TYPE
phase[5] <= acc[11].DB_MAX_OUTPUT_PORT_TYPE
phase[6] <= acc[12].DB_MAX_OUTPUT_PORT_TYPE
phase[7] <= acc[13].DB_MAX_OUTPUT_PORT_TYPE

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@ -0,0 +1,18 @@
<TABLE>
<TR bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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@ -0,0 +1 @@
v1

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@ -0,0 +1,12 @@
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1673883395012 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 16 18:36:34 2023 " "Processing started: Mon Jan 16 18:36:34 2023" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1673883395013 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel " "Command: quartus_map --read_settings_files=on --write_settings_files=off sigdel -c sigdel" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883395013 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1673883395187 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv 1 1 " "Found 1 design units, including 1 entities, in source file /home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel " "Found entity 1: sigdel" { } { { "../../HDL/sigdel.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/HDL/sigdel.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sigdel_tb.sv 1 1 " "Found 1 design units, including 1 entities, in source file sigdel_tb.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sigdel_tb " "Found entity 1: sigdel_tb" { } { { "sigdel_tb.sv" "" { Text "/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Testbench/sigdel/sigdel_tb.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1673883401066 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401066 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "sigdel " "Elaborating entity \"sigdel\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1673883401097 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1673883401388 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1673883401553 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1673883401553 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "32 " "Implemented 32 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Implemented 10 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Implemented 8 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1673883401619 ""} { "Info" "ICUT_CUT_TM_LCELLS" "14 " "Implemented 14 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1673883401619 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1673883401619 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1047 " "Peak virtual memory: 1047 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 16 18:36:41 2023 " "Processing ended: Mon Jan 16 18:36:41 2023" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Elapsed time: 00:00:07" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1673883401622 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1673883401622 ""}

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v1

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@ -0,0 +1 @@
FIT

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@ -0,0 +1,81 @@
{
"partitions" : [
{
"name" : "Top",
"pins" : [
{
"name" : "phase[0]",
"strict" : false
},
{
"name" : "phase[1]",
"strict" : false
},
{
"name" : "phase[2]",
"strict" : false
},
{
"name" : "phase[3]",
"strict" : false
},
{
"name" : "phase[4]",
"strict" : false
},
{
"name" : "phase[5]",
"strict" : false
},
{
"name" : "phase[6]",
"strict" : false
},
{
"name" : "phase[7]",
"strict" : false
},
{
"name" : "clk",
"strict" : false
},
{
"name" : "clr_n",
"strict" : false
},
{
"name" : "phinc[6]",
"strict" : false
},
{
"name" : "phinc[7]",
"strict" : false
},
{
"name" : "phinc[5]",
"strict" : false
},
{
"name" : "phinc[4]",
"strict" : false
},
{
"name" : "phinc[3]",
"strict" : false
},
{
"name" : "phinc[2]",
"strict" : false
},
{
"name" : "phinc[1]",
"strict" : false
},
{
"name" : "phinc[0]",
"strict" : false
}
]
}
]
}

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@ -0,0 +1,11 @@
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.

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@ -0,0 +1,3 @@
Quartus_Version = Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
Version_Index = 486699264
Creation_Time = Thu Jan 12 13:26:18 2023

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7aee213afbf8301ed5eefc8c827f49a3

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@ -1155,14 +1155,13 @@ set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mem.v"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_mem.v"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_jtag_uart.v"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_jtag_uart.v"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu.v"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu.v"]
set_global_assignment -library "niosII" -name SDC_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.sdc"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.v"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_sysclk.v"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_sysclk.v"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_tck.v"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_wrapper.v"]
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_ociram_default_contents.mif"] set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_ociram_default_contents.mif"]
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_a.mif"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_tck.v"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.v"]
set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_b.mif"] set_global_assignment -library "niosII" -name SOURCE_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_rf_ram_b.mif"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_debug_slave_wrapper.v"]
set_global_assignment -library "niosII" -name SDC_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu.sdc"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_test_bench.v"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/niosII_cpu_cpu_test_bench.v"]
set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/countones.v"] set_global_assignment -library "niosII" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/countones.v"]

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@ -1,4 +1,4 @@
<?xml version="1.0"?> <?xml version="1.0" encoding="UTF-8"?>
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd"> <device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
<name>niosII</name> <name>niosII</name>
<peripherals> <peripherals>

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@ -83,6 +83,7 @@ module dec
colors <= 3'b001; colors <= 3'b001;
state <= GREEN; state <= GREEN;
end end
if (train) begin if (train) begin
colors <= 3'b100; colors <= 3'b100;
state <= RED; state <= RED;

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@ -1,4 +1,4 @@
# Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your # Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
# use of Altera Corporation's design tools, logic functions and other # use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any # software and tools, and its AMPP partner logic functions, and any
# output files any of the foregoing (including device programming or # output files any of the foregoing (including device programming or

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@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your //Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other //use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any //software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or //output files any of the foregoing (including device programming or

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@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your //Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other //use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any //software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or //output files any of the foregoing (including device programming or

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@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your //Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other //use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any //software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or //output files any of the foregoing (including device programming or

View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your //Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other //use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any //software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or //output files any of the foregoing (including device programming or

View File

@ -7,261 +7,261 @@ DATA_RADIX=HEX;
CONTENT BEGIN CONTENT BEGIN
00 : 88997af9; 00 : 5870e850;
01 : abaae595; 01 : c7a32b0d;
02 : 32fd14d1; 02 : 6f82d8fd;
03 : b66193c4; 03 : 40bb3819;
04 : c6a6aa09; 04 : 03c0b473;
05 : 0b43de5b; 05 : 8f16cf30;
06 : d1d93028; 06 : d708360b;
07 : bcd08e2a; 07 : 880f36dc;
08 : 1c8bae85; 08 : d1a275f0;
09 : b11dad63; 09 : 5944e053;
0a : 864ddf62; 0a : c1313a53;
0b : 68301486; 0b : 4cb0c559;
0c : 51a3d8d0; 0c : 528cd209;
0d : 7af7d39e; 0d : 1ed6d1c2;
0e : 4761b503; 0e : 3fe378c9;
0f : 2a976e14; 0f : aa1b9ac8;
10 : 98141041; 10 : 31d374f0;
11 : 4c1f6471; 11 : be61ec44;
12 : 41dc0a35; 12 : 2c7a1043;
13 : 7d484ae3; 13 : 2641125e;
14 : 2a1329f3; 14 : 0c46e1e9;
15 : 44ecf499; 15 : 9860f4c3;
16 : dccdd125; 16 : d9980c45;
17 : 240142e9; 17 : 85005ae5;
18 : 3b7e4b05; 18 : b156d9cb;
19 : bb92e762; 19 : 8a5321c3;
1a : 4594a3c5; 1a : b603ed2b;
1b : ea0d940f; 1b : 2a1eb3a0;
1c : 66525d7c; 1c : f4b7b88b;
1d : 0f552242; 1d : a1ce694f;
1e : 452bd52d; 1e : 469d3811;
1f : d1f4ed11; 1f : 2185240b;
20 : 5d590422; 20 : a745eb3e;
21 : c8016b5f; 21 : 3d2ce9c9;
22 : 9ab94f07; 22 : e4f87c64;
23 : 16bac9b4; 23 : 4e473b66;
24 : fe569ae3; 24 : f25af5e6;
25 : c6e1e6e7; 25 : 5bf0ba5c;
26 : 2ff19932; 26 : d9f793ee;
27 : feb058ad; 27 : a5410324;
28 : 1dcce651; 28 : 298d0d25;
29 : e18b9bfb; 29 : e60402c3;
2a : e2f4fc64; 2a : 97132679;
2b : 05d34847; 2b : bcd9897b;
2c : 077a8143; 2c : 82a038f5;
2d : 2ce4207f; 2d : 201cbf45;
2e : 3f3e5113; 2e : fe6ce958;
2f : c24d2803; 2f : c368dfdf;
30 : e289b503; 30 : 6a3f8ef7;
31 : d16bcd4e; 31 : 83368a01;
32 : 57a841cf; 32 : 65976a6a;
33 : 1194f754; 33 : 821cfabf;
34 : 5c925a31; 34 : 20bdc8df;
35 : 40fd6946; 35 : 60d97952;
36 : e397e5d7; 36 : 73819628;
37 : eada7553; 37 : 674070d1;
38 : eba8ec01; 38 : fc155d79;
39 : f5b39d0b; 39 : d3a408b1;
3a : 88af39a3; 3a : bfdf2c88;
3b : 5b7f243e; 3b : 22a2fce0;
3c : 4f2bb4ba; 3c : 01e7c505;
3d : 9451a234; 3d : e3e78ba0;
3e : 10fd984d; 3e : a049e343;
3f : ad4ef4f7; 3f : c0f1b055;
40 : 7fe97f8b; 40 : 877e1ef1;
41 : 08ea614d; 41 : ca871fa5;
42 : 9f2c5cf4; 42 : 25ab3e85;
43 : 3f90b7a2; 43 : f9f4b822;
44 : 8c2bc774; 44 : 90aad39a;
45 : 45dd63a5; 45 : 08f5e44c;
46 : 3204329c; 46 : 39d12cce;
47 : 9909be0d; 47 : 80f2ed6f;
48 : be65c97b; 48 : 6a29b7d6;
49 : 78f3d4a4; 49 : 8b913cf5;
4a : 3ee8b71c; 4a : 63815e88;
4b : 9e9a0de4; 4b : 3b598e73;
4c : 56db426b; 4c : 73bfa5d4;
4d : e6869d81; 4d : 77c09ce3;
4e : 20ab0652; 4e : 839a407b;
4f : 05d247ed; 4f : 6433730b;
50 : 1edccf12; 50 : 44284f24;
51 : 1e483b5a; 51 : f5d5762e;
52 : 8e48ef1e; 52 : b65d636d;
53 : f19aefbf; 53 : d1c786b8;
54 : 98335d23; 54 : f3c8d2f5;
55 : 954ac923; 55 : 356dc558;
56 : 4679ced6; 56 : 591772eb;
57 : ae18d9b8; 57 : 79e0fdb4;
58 : be57db48; 58 : e8932f59;
59 : 2af933e3; 59 : 259d108a;
5a : 3f04e244; 5a : bb57a7f8;
5b : 5d11c958; 5b : 4825e3bc;
5c : 65bda8cb; 5c : 52cf4522;
5d : c53fe664; 5d : 79e4316b;
5e : 797ceac8; 5e : 8c0d6004;
5f : aaa406e5; 5f : a754e118;
60 : f785e24e; 60 : 4e281ca2;
61 : 95510077; 61 : fbbc819a;
62 : 5b6f55a3; 62 : 4aee7640;
63 : 2a3c749a; 63 : 7d333e63;
64 : a92e6ae6; 64 : b15aaa9c;
65 : b2117fb0; 65 : 4f43ec26;
66 : 262a254e; 66 : 1ec71c75;
67 : b8c4da74; 67 : 8836d7ff;
68 : f69070ee; 68 : 03bf3159;
69 : 9e7f80b8; 69 : 64fe92e3;
6a : 834528b4; 6a : 967a0361;
6b : 4aaf6d98; 6b : 52d392c1;
6c : 96023372; 6c : ed91cb89;
6d : d11663ed; 6d : 576cc97b;
6e : 33a3c007; 6e : 6b3ffb6a;
6f : 0e7f06ee; 6f : 35d248a1;
70 : 34385787; 70 : f9045e40;
71 : 2edfd7b0; 71 : 67ec2a14;
72 : 00d60e4b; 72 : c6a8d3b4;
73 : 49535c30; 73 : 215bfb86;
74 : e83f5c14; 74 : c69c1f66;
75 : 5e0c4c59; 75 : 4244d56d;
76 : 1d7b944a; 76 : 1b3928f3;
77 : 6ae69731; 77 : 731a2236;
78 : bf8414e4; 78 : 38d78b27;
79 : 7451c212; 79 : 059c9248;
7a : 74ede6d2; 7a : 5f87a44a;
7b : 080eafa5; 7b : aba5ed2e;
7c : f21052d8; 7c : c0524059;
7d : cc0819fb; 7d : 980abb72;
7e : 8993e5b6; 7e : 7437c9f5;
7f : e20f2df6; 7f : 7eceac74;
80 : 0f267a65; 80 : e459de2d;
81 : 7a8e8407; 81 : 70371382;
82 : e7be656d; 82 : 9e5c9169;
83 : 01ba4ca3; 83 : e019ec71;
84 : 7f998e44; 84 : 8a8a254a;
85 : 29d83420; 85 : 5d6b1e75;
86 : 149f9a73; 86 : b69a1826;
87 : 643ae51e; 87 : 1895f4fa;
88 : 125714d3; 88 : f357cacf;
89 : 6e49dc21; 89 : d52486ab;
8a : 0b227946; 8a : 1e598442;
8b : 360a837d; 8b : d8d4c72d;
8c : b2187074; 8c : f8973f5f;
8d : 17b0bdbd; 8d : 7df07844;
8e : 938fc73d; 8e : 603c0386;
8f : e73f501e; 8f : 5fa48cd0;
90 : 70b5b87e; 90 : 7dad0b4e;
91 : 2a2aed8a; 91 : d8063146;
92 : f96cc881; 92 : dd06b1d5;
93 : 021b49e1; 93 : a42cea93;
94 : 8691600d; 94 : 937d88ca;
95 : b45e1d12; 95 : 0c6e9a23;
96 : 64d9644e; 96 : b81bdfa3;
97 : 486cbaf9; 97 : 28077cf0;
98 : 386acf20; 98 : 9aab97aa;
99 : 0d1384d4; 99 : b6597e34;
9a : 62455f77; 9a : 436fcd2b;
9b : 866fde20; 9b : be8fe3e1;
9c : 006fecec; 9c : dae80c2f;
9d : 94e84514; 9d : e95b81e6;
9e : 7babc333; 9e : 767f7b1b;
9f : afaa8445; 9f : 23d2190d;
a0 : b1175e3a; a0 : dbd13b92;
a1 : e08de629; a1 : ba04bced;
a2 : 7f12a52d; a2 : c59ab4a9;
a3 : 0e322909; a3 : d18cd97a;
a4 : 18784dc6; a4 : fdc9eef9;
a5 : b23bcc20; a5 : e5d3431b;
a6 : 266c9e34; a6 : 36145dba;
a7 : c857eaf3; a7 : 381901fd;
a8 : 2ae3b164; a8 : 2b84a31d;
a9 : 038acf2a; a9 : 56d3b835;
aa : c1abc60d; aa : 82d83a4f;
ab : 8af787bd; ab : 521d2b9a;
ac : 043723a9; ac : 0224591a;
ad : c37c952d; ad : 80d7ea50;
ae : 693a361f; ae : 49815eac;
af : da4b8e99; af : 9c8177e2;
b0 : fb8fdb10; b0 : d83c171d;
b1 : 4d6365f2; b1 : 82d4e894;
b2 : 712358e9; b2 : 2da7a2cf;
b3 : 85dae0fa; b3 : ae082f05;
b4 : 7e82a418; b4 : ea847ea7;
b5 : d3493768; b5 : c53a36ee;
b6 : 739c65ec; b6 : 9044fe8d;
b7 : 73b66b19; b7 : dadb18f9;
b8 : 22142816; b8 : 3631522b;
b9 : ff498322; b9 : 2bae3746;
ba : 3266495e; ba : 02d78d99;
bb : e26e8214; bb : 8e0e2771;
bc : c8c47131; bc : 2ed189db;
bd : 660793d8; bd : 63aa82eb;
be : 689f8d69; be : 754229af;
bf : faae340b; bf : a11062b5;
c0 : 37518ba7; c0 : e28618e1;
c1 : f2865fe5; c1 : fcaf3400;
c2 : 1bb44f3d; c2 : c8a7faac;
c3 : 3bce44c5; c3 : be56d9b0;
c4 : aff2d188; c4 : 7c3f3063;
c5 : 985442da; c5 : 4d331f3f;
c6 : 85bb58bd; c6 : 8cceb16d;
c7 : 0c53135d; c7 : 2d352b5d;
c8 : 495f80bc; c8 : 0db6cd22;
c9 : 853c95dc; c9 : 745ff58e;
ca : dde937f1; ca : e450c6d2;
cb : 418f9452; cb : 5567ae51;
cc : 7669641c; cc : ec2ac609;
cd : 0e752434; cd : fcced128;
ce : b0fe17a7; ce : 193f8e92;
cf : d1be9b88; cf : 5719a6cc;
d0 : cfbfeb76; d0 : 065cddb6;
d1 : 80b48a11; d1 : 04f4e1f9;
d2 : 9327c69e; d2 : a95d8a1e;
d3 : beca5a88; d3 : d516bf8e;
d4 : e71d428f; d4 : e30d671e;
d5 : b318d275; d5 : ebeeb2fe;
d6 : 56fea35e; d6 : b48fdd0f;
d7 : 140cd6bd; d7 : f4b75c46;
d8 : b8c937ce; d8 : 4d9c9650;
d9 : 540eea36; d9 : f2df58d8;
da : ee58fc7f; da : 67ace373;
db : 5615c389; db : 7ccace3c;
dc : 46692ad0; dc : f4f3f5d5;
dd : 5c713e51; dd : 2be9f598;
de : 6ba95f60; de : f7889908;
df : 0e166732; df : f67c2f07;
e0 : ac0e49f5; e0 : 880a8491;
e1 : c9a5ea76; e1 : 9c3967d0;
e2 : 05b04d86; e2 : d89b44d2;
e3 : b29ac712; e3 : 7c21987c;
e4 : 4e344493; e4 : 495e0377;
e5 : d45ede48; e5 : 1c88706d;
e6 : 3da7e426; e6 : bf0b4325;
e7 : 4d6a8937; e7 : 79fcc944;
e8 : 99b59bd4; e8 : fd8c1d81;
e9 : 1f8a5751; e9 : f4f168ae;
ea : 8b07e64e; ea : cf67e751;
eb : b4dcd496; eb : 75907b16;
ec : 42f84fe6; ec : d859c7c1;
ed : f1d5952f; ed : 05ef2e02;
ee : a2e5a42d; ee : 1f5802c9;
ef : 15b1af16; ef : 8cb4928b;
f0 : 168012bc; f0 : 19e65b5f;
f1 : 2e276612; f1 : 9c3b7bab;
f2 : 89913eaa; f2 : 22bc8d7d;
f3 : c607a1a2; f3 : 03aa0e5f;
f4 : fd8b544d; f4 : 7d35f4ff;
f5 : aec31a53; f5 : e5208a6e;
f6 : 25f958ad; f6 : 44fdd477;
f7 : 365903ec; f7 : 74a81f1c;
f8 : 14761865; f8 : 6936d4f1;
f9 : 568cc23b; f9 : 375fc2a2;
fa : b0386305; fa : 22a07f26;
fb : fb9ebd8a; fb : 701c1a4d;
fc : a25911d4; fc : af4d2557;
fd : 806e3fbb; fd : bac85a82;
fe : 9df35264; fe : 29cff602;
ff : d62b3814; ff : 3e17ccab;
END; END;

View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your //Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other //use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any //software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or //output files any of the foregoing (including device programming or

View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your //Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other //use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any //software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or //output files any of the foregoing (including device programming or

View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your //Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other //use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any //software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or //output files any of the foregoing (including device programming or

View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your //Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other //use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any //software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or //output files any of the foregoing (including device programming or

View File

@ -1,5 +1,5 @@
# (C) 2001-2022 Altera Corporation. All rights reserved. # (C) 2001-2023 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and # Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and # other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming # any output files any of the foregoing (including device programming
@ -94,7 +94,7 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ACDS 18.1 625 linux 2023.01.17.19:01:36
# ---------------------------------------- # ----------------------------------------
# Initialize variables # Initialize variables
@ -113,7 +113,7 @@ if ![info exists QSYS_SIMDIR] {
} }
if ![info exists QUARTUS_INSTALL_DIR] { if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/software/intelfpga_lite/18.1/quartus/" set QUARTUS_INSTALL_DIR "/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
} }
if ![info exists USER_DEFINED_COMPILE_OPTIONS] { if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
@ -142,14 +142,14 @@ if ![ string match "*-64 vsim*" [ vsim -version ] ] {
alias file_copy { alias file_copy {
echo "\[exec\] file_copy" echo "\[exec\] file_copy"
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./ file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
} }
@ -280,9 +280,9 @@ alias com {
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -L altera_common_sv_packages -work cpu_data_master_agent eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -L altera_common_sv_packages -work cpu_data_master_agent
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_translator eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_translator
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -L altera_common_sv_packages -work cpu_data_master_translator eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -L altera_common_sv_packages -work cpu_data_master_translator
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller

View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2022.12.24.02:15:37</td> <td class="l">2023.01.17.19:01:29</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -2038,8 +2038,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div> </div>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0,01 seconds</td> <td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0,07 seconds</td> <td class="r">rendering took 0.01 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table> </table>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">2022.12.24.02:15:47</td> <td class="l">2023.01.17.19:01:31</td>
<td class="r">Datasheet</td> <td class="r">Datasheet</td>
</tr> </tr>
</table> </table>
@ -211,7 +211,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<table> <table>
<tr> <tr>
<td class="parametername">AUTO_GENERATION_ID</td> <td class="parametername">AUTO_GENERATION_ID</td>
<td class="parametervalue">1671833747</td> <td class="parametervalue">1673967691</td>
</tr> </tr>
<tr> <tr>
<td class="parametername">AUTO_UNIQUE_ID</td> <td class="parametername">AUTO_UNIQUE_ID</td>
@ -2359,8 +2359,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div> </div>
<table class="blueBar"> <table class="blueBar">
<tr> <tr>
<td class="l">generation took 0,01 seconds</td> <td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0,06 seconds</td> <td class="r">rendering took 0.02 seconds</td>
</tr> </tr>
</table> </table>
</body> </body>

View File

@ -1,3 +1,7 @@
// niosII_tb.v
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps `timescale 1 ps / 1 ps
module niosII_tb ( module niosII_tb (
); );
@ -7,8 +11,7 @@ module niosII_tb (
reg train; reg train;
wire red, yellow, green; wire red, yellow, green;
niosII niosii_inst niosII niosii_inst (
(
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk .clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
.reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n .reset_reset_n (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
.sem_export_train (train), // sem_export.train .sem_export_train (train), // sem_export.train
@ -17,48 +20,36 @@ module niosII_tb (
.sem_export_green (green) // .green .sem_export_green (green) // .green
); );
altera_avalon_clock_source altera_avalon_clock_source #(
#(
.CLOCK_RATE (50000000), .CLOCK_RATE (50000000),
.CLOCK_UNIT (1) .CLOCK_UNIT (1)
) ) niosii_inst_clk_bfm (
niosii_inst_clk_bfm
(
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk .clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
); );
altera_avalon_reset_source altera_avalon_reset_source #(
#(
.ASSERT_HIGH_RESET (0), .ASSERT_HIGH_RESET (0),
.INITIAL_RESET_CYCLES (50) .INITIAL_RESET_CYCLES (50)
) ) niosii_inst_reset_bfm (
niosii_inst_reset_bfm
(
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n .reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk .clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
); );
initial begin initial begin
train = 0; train = 0;
wait (niosii_inst_reset_bfm_reset_reset); wait (niosii_inst_reset_bfm_reset_reset);
forever begin forever begin
wait ({red,yellow,green}==3'b001);
repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk); repeat (29000) @(posedge niosii_inst_clk_bfm_clk_clk);
repeat(8) begin
train = 1; train = 1;
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk); repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 0; train = 0;
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk); wait ({red,yellow,green}==3'b001);
train = 1; repeat (200) @(posedge niosii_inst_clk_bfm_clk_clk);
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk); end
train = 0;
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 1;
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 0;
repeat (900) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 1;
repeat (10) @(posedge niosii_inst_clk_bfm_clk_clk);
train = 0;
end end
end end
endmodule endmodule

View File

@ -1,5 +1,5 @@
# (C) 2001-2022 Altera Corporation. All rights reserved. # (C) 2001-2023 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and # Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and # other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming # any output files any of the foregoing (including device programming
@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ACDS 18.1 625 linux 2023.01.17.19:01:36
# ---------------------------------------- # ----------------------------------------
# vcs - auto-generated simulation script # vcs - auto-generated simulation script
@ -94,12 +94,12 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ACDS 18.1 625 linux 2023.01.17.19:01:36
# ---------------------------------------- # ----------------------------------------
# initialize variables # initialize variables
TOP_LEVEL_NAME="niosII_tb" TOP_LEVEL_NAME="niosII_tb"
QSYS_SIMDIR="./../../" QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="C:/software/intelfpga_lite/18.1/quartus/" QUARTUS_INSTALL_DIR="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
SKIP_FILE_COPY=0 SKIP_FILE_COPY=0
SKIP_SIM=0 SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS="" USER_DEFINED_ELAB_OPTIONS=""
@ -131,14 +131,14 @@ fi
# copy RAM/ROM files to simulation directory # copy RAM/ROM files to simulation directory
if [ $SKIP_FILE_COPY -eq 0 ]; then if [ $SKIP_FILE_COPY -eq 0 ]; then
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
fi fi
@ -171,9 +171,9 @@ vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPT
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv \ $QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv \ $QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv \ $QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v \ $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v \ $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v \ $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v \ $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v \ $QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v \

View File

@ -1,5 +1,5 @@
# (C) 2001-2022 Altera Corporation. All rights reserved. # (C) 2001-2023 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and # Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and # other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming # any output files any of the foregoing (including device programming
@ -12,7 +12,7 @@
# or its authorized distributors. Please refer to the applicable # or its authorized distributors. Please refer to the applicable
# agreement for further details. # agreement for further details.
# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ACDS 18.1 625 linux 2023.01.17.19:01:36
# ---------------------------------------- # ----------------------------------------
# vcsmx - auto-generated simulation script # vcsmx - auto-generated simulation script
@ -107,12 +107,12 @@
# within the Quartus project, and generate a unified # within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design. # script which supports all the Altera IP within the design.
# ---------------------------------------- # ----------------------------------------
# ACDS 18.1 625 win32 2022.12.24.02:16:20 # ACDS 18.1 625 linux 2023.01.17.19:01:36
# ---------------------------------------- # ----------------------------------------
# initialize variables # initialize variables
TOP_LEVEL_NAME="niosII_tb" TOP_LEVEL_NAME="niosII_tb"
QSYS_SIMDIR="./../../" QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="C:/software/intelfpga_lite/18.1/quartus/" QUARTUS_INSTALL_DIR="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
SKIP_FILE_COPY=0 SKIP_FILE_COPY=0
SKIP_DEV_COM=0 SKIP_DEV_COM=0
SKIP_COM=0 SKIP_COM=0
@ -189,14 +189,14 @@ mkdir -p ./libraries/cycloneive_ver/
# copy RAM/ROM files to simulation directory # copy RAM/ROM files to simulation directory
if [ $SKIP_FILE_COPY -eq 0 ]; then if [ $SKIP_FILE_COPY -eq 0 ]; then
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./ cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
fi fi
@ -239,9 +239,9 @@ if [ $SKIP_COM -eq 0 ]; then
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -work cpu_data_master_agent vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -work cpu_data_master_agent
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -work jtag_uart_avalon_jtag_slave_translator vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -work jtag_uart_avalon_jtag_slave_translator
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -work cpu_data_master_translator vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -work cpu_data_master_translator
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller

View File

@ -1,12 +1,12 @@
# system info niosII_tb on 2022.12.24.02:16:19 # system info niosII_tb on 2023.01.17.19:01:35
system_info: system_info:
name,value name,value
DEVICE,EP4CE115F29C7 DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1671833747 GENERATION_ID,1673967691
# #
# #
# Files generated for niosII_tb on 2022.12.24.02:16:19 # Files generated for niosII_tb on 2023.01.17.19:01:35
files: files:
filepath,kind,attributes,module,is_top filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
@ -27,22 +27,22 @@ niosII/testbench/niosII_tb/simulation/submodules/niosII_irq_mapper.sv,SYSTEM_VER
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false

1 # system info niosII_tb on 2022.12.24.02:16:19 # system info niosII_tb on 2023.01.17.19:01:35
2 system_info: system_info:
3 name,value name,value
4 DEVICE,EP4CE115F29C7 DEVICE,EP4CE115F29C7
5 DEVICE_FAMILY,Cyclone IV E DEVICE_FAMILY,Cyclone IV E
6 GENERATION_ID,1671833747 GENERATION_ID,1673967691
7 # #
8 # #
9 # Files generated for niosII_tb on 2022.12.24.02:16:19 # Files generated for niosII_tb on 2023.01.17.19:01:35
10 files: files:
11 filepath,kind,attributes,module,is_top filepath,kind,attributes,module,is_top
12 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
27 niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
28 niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false niosII/testbench/niosII_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
29 niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
30 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
31 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat,DAT,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
32 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat,DAT,,niosII_cpu_cpu,false
33 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif,MIF,,niosII_cpu_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
34 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat,DAT,,niosII_cpu_cpu,false
35 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do,OTHER,,niosII_cpu_cpu,false
36 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex,HEX,,niosII_cpu_cpu,false
37 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v,VERILOG,,niosII_cpu_cpu,false
38 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v,VERILOG,,niosII_cpu_cpu,false
39 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif,MIF,,niosII_cpu_cpu,false
40 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v,VERILOG,,niosII_cpu_cpu,false
41 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc,SDC,,niosII_cpu_cpu,false
42 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v,VERILOG,,niosII_cpu_cpu,false
43 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex,HEX,,niosII_cpu_cpu,false
44 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif,MIF,,niosII_cpu_cpu,false
45 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex,HEX,,niosII_cpu_cpu,false
46 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
47 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
48 niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false

View File

@ -101,70 +101,70 @@
path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" path="niosII/testbench/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv"
type="SYSTEM_VERILOG" type="SYSTEM_VERILOG"
library="cpu_data_master_translator" /> library="cpu_data_master_translator" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
type="SDC"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"
type="VERILOG"
library="cpu" />
<file <file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v"
type="VERILOG" type="VERILOG"
library="cpu" /> library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
type="OTHER"
library="cpu" />
<file <file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat" path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat"
type="DAT" type="DAT"
library="cpu" /> library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex"
type="HEX"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
type="MIF"
library="cpu" />
<file <file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat" path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat"
type="DAT" type="DAT"
library="cpu" /> library="cpu" />
<file <file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex" path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif"
type="HEX"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif"
type="MIF" type="MIF"
library="cpu" /> library="cpu" />
<file <file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat" path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat"
type="DAT" type="DAT"
library="cpu" /> library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_nios2_waves.do"
type="OTHER"
library="cpu" />
<file <file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex" path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex"
type="HEX" type="HEX"
library="cpu" /> library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.v"
type="VERILOG"
library="cpu" />
<file <file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif" path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif"
type="MIF" type="MIF"
library="cpu" /> library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu.sdc"
type="SDC"
library="cpu" />
<file <file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v"
type="VERILOG" type="VERILOG"
library="cpu" /> library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex"
type="HEX"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif"
type="MIF"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex"
type="HEX"
library="cpu" />
<file <file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v" path="niosII/testbench/niosII_tb/simulation/submodules/altera_reset_controller.v"
type="VERILOG" type="VERILOG"

View File

@ -2,13 +2,12 @@
<project> <project>
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II"> <configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1701080960758821589" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true"> <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-136685873252219664" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/> <language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/> <language-scope id="org.eclipse.cdt.core.g++"/>
</provider> </provider>
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuildCommandParser" id="altera.tool.Nios2GCCBuildCommandParser" keep-relative-paths="false" name="Nios II GCC Build Output Parser" parameter="(nios2-elf-gcc)|(nios2-elf-g\+\+)" prefer-non-shared="true"/>
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/> <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
</extension> </extension>
</configuration> </configuration>

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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View File

@ -7,163 +7,163 @@
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00003258 T alt_dcache_flush 0000323c T alt_dcache_flush
00003280 t alt_dev_null_write 00003264 t alt_dev_null_write
000032ac t alt_get_errno 00003290 t alt_get_errno
000032e8 T fstat 000032cc T fstat
000033a0 t alt_get_errno 00003384 t alt_get_errno
000033dc T isatty 000033c0 T isatty
00003488 t alt_get_errno 0000346c t alt_get_errno
000034c4 T lseek 000034a8 T lseek
000035a0 T alt_main 00003584 T alt_main
0000361c T __malloc_lock 00003600 T __malloc_lock
00003640 T __malloc_unlock 00003624 T __malloc_unlock
00003664 t alt_get_errno 00003648 t alt_get_errno
000036a0 T read 00003684 T read
000037a4 T alt_release_fd 00003788 T alt_release_fd
00003828 T sbrk 0000380c T sbrk
000038d8 t alt_get_errno 000038bc t alt_get_errno
00003914 T write 000038f8 T write
00003a14 t alt_dev_reg 000039f8 t alt_dev_reg
00003a48 T alt_irq_init 00003a2c T alt_irq_init
00003a80 T alt_sys_init 00003a64 T alt_sys_init
00003ae0 T altera_avalon_jtag_uart_read_fd 00003ac4 T altera_avalon_jtag_uart_read_fd
00003b40 T altera_avalon_jtag_uart_write_fd 00003b24 T altera_avalon_jtag_uart_write_fd
00003ba0 T altera_avalon_jtag_uart_close_fd 00003b84 T altera_avalon_jtag_uart_close_fd
00003bf0 T altera_avalon_jtag_uart_ioctl_fd 00003bd4 T altera_avalon_jtag_uart_ioctl_fd
00003c44 T altera_avalon_jtag_uart_init 00003c28 T altera_avalon_jtag_uart_init
00003d04 t altera_avalon_jtag_uart_irq 00003ce8 t altera_avalon_jtag_uart_irq
00003f10 t altera_avalon_jtag_uart_timeout 00003ef4 t altera_avalon_jtag_uart_timeout
00003fb0 T altera_avalon_jtag_uart_close 00003f94 T altera_avalon_jtag_uart_close
00004018 T altera_avalon_jtag_uart_ioctl 00003ffc T altera_avalon_jtag_uart_ioctl
00004108 T altera_avalon_jtag_uart_read 000040ec T altera_avalon_jtag_uart_read
00004324 T altera_avalon_jtag_uart_write 00004308 T altera_avalon_jtag_uart_write
00004548 t alt_avalon_timer_sc_irq 0000452c t alt_avalon_timer_sc_irq
000045c0 T alt_avalon_timer_sc_init 000045a4 T alt_avalon_timer_sc_init
0000463c T alt_alarm_start 00004620 T alt_alarm_start
00004768 t alt_get_errno 0000474c t alt_get_errno
000047a4 T alt_dev_llist_insert 00004788 T alt_dev_llist_insert
00004848 T _do_ctors 0000482c T _do_ctors
000048a8 T _do_dtors 0000488c T _do_dtors
00004908 T alt_ic_isr_register 000048ec T alt_ic_isr_register
00004958 T alt_ic_irq_enable 0000493c T alt_ic_irq_enable
000049e0 T alt_ic_irq_disable 000049c4 T alt_ic_irq_disable
00004a6c T alt_ic_irq_enabled 00004a50 T alt_ic_irq_enabled
00004ab8 T alt_iic_isr_register 00004a9c T alt_iic_isr_register
00004ba8 t alt_open_fd 00004b8c t alt_open_fd
00004c8c T alt_io_redirect 00004c70 T alt_io_redirect
00004d08 t alt_get_errno 00004cec t alt_get_errno
00004d44 t alt_file_locked 00004d28 t alt_file_locked
00004e30 T open 00004e14 T open
00004f8c T alt_alarm_stop 00004f70 T alt_alarm_stop
00005028 T alt_tick 0000500c T alt_tick
00005130 T altera_nios2_gen2_irq_init 00005114 T altera_nios2_gen2_irq_init
00005154 T alt_find_dev 00005138 T alt_find_dev
000051e4 T alt_find_file 000051c8 T alt_find_file
000052ec T alt_get_fd 000052d0 T alt_get_fd
000053b0 T alt_exception_cause_generated_bad_addr 00005394 T alt_exception_cause_generated_bad_addr
0000544c T atexit 00005430 T atexit
00005460 T exit 00005444 T exit
00005498 T memcmp 0000547c T memcmp
00005514 T __register_exitproc 000054f8 T __register_exitproc
0000562c T __call_exitprocs 00005610 T __call_exitprocs
000057ac T _exit 00005790 T _exit
000057e0 A __CTOR_END__ 000057c4 A __CTOR_END__
000057e0 A __CTOR_LIST__ 000057c4 A __CTOR_LIST__
000057e0 A __DTOR_END__ 000057c4 A __DTOR_END__
000057e0 A __DTOR_LIST__ 000057c4 A __DTOR_LIST__
000057e0 R divisors 000057c4 R divisors
0000585c g impure_data 00005840 g impure_data
00005c80 G __malloc_av_ 00005c64 G __malloc_av_
00006088 G alt_dev_null 0000606c G alt_dev_null
000060b0 G alt_fd_list 00006094 G alt_fd_list
00006230 g jtag_uart 00006214 g jtag_uart
00007290 G _global_impure_ptr 00007274 G _global_impure_ptr
00007294 G _impure_ptr 00007278 G _impure_ptr
00007298 G __malloc_sbrk_base 0000727c G __malloc_sbrk_base
0000729c G __malloc_trim_threshold 00007280 G __malloc_trim_threshold
000072a0 G alt_fs_list 00007284 G alt_fs_list
000072a8 G alt_dev_list 0000728c G alt_dev_list
000072b0 G alt_max_fd 00007294 G alt_max_fd
000072b4 G alt_errno 00007298 G alt_errno
000072b8 g heap_end 0000729c g heap_end
000072bc G alt_priority_mask 000072a0 G alt_priority_mask
000072c0 G alt_alarm_list 000072a4 G alt_alarm_list
000072c8 A __bss_start 000072ac A __bss_start
000072c8 B __malloc_max_total_mem 000072ac B __malloc_max_total_mem
000072c8 A _edata 000072ac A _edata
000072cc B __malloc_max_sbrked_mem 000072b0 B __malloc_max_sbrked_mem
000072d0 B __malloc_top_pad 000072b4 B __malloc_top_pad
000072d4 B errno 000072b8 B errno
000072d8 B alt_argc 000072bc B alt_argc
000072dc B alt_argv 000072c0 B alt_argv
000072e0 B alt_envp 000072c4 B alt_envp
000072e4 B alt_irq_active 000072c8 B alt_irq_active
000072e8 B _alt_tick_rate 000072cc B _alt_tick_rate
000072ec B _alt_nticks 000072d0 B _alt_nticks
000072f0 B alt_instruction_exception_handler 000072d4 B alt_instruction_exception_handler
000072f4 B __malloc_current_mallinfo 000072d8 B __malloc_current_mallinfo
0000731c B alt_irq 00007300 B alt_irq
0000741c A __alt_heap_start 00007400 A __alt_heap_start
0000741c A __alt_stack_base 00007400 A __alt_stack_base
0000741c A __bss_end 00007400 A __bss_end
0000741c A _end 00007400 A _end
0000741c A end 00007400 A end
0000f290 A _gp 0000f274 A _gp
00020000 A __alt_data_end 00020000 A __alt_data_end
00020000 A __alt_heap_limit 00020000 A __alt_heap_limit
00020000 A __alt_stack_pointer 00020000 A __alt_stack_pointer

File diff suppressed because it is too large Load Diff

View File

@ -20,18 +20,18 @@ add wave -noupdate /niosII_tb/niosii_inst/sem/ctl_addr
add wave -noupdate /niosII_tb/niosii_inst/sem/ctl_wrdata add wave -noupdate /niosII_tb/niosii_inst/sem/ctl_wrdata
add wave -noupdate /niosII_tb/niosii_inst/sem/ctl_rddata add wave -noupdate /niosII_tb/niosii_inst/sem/ctl_rddata
add wave -noupdate /niosII_tb/niosii_inst/sem/ram_wr add wave -noupdate /niosII_tb/niosii_inst/sem/ram_wr
add wave -noupdate /niosII_tb/niosii_inst/sem/ram_addr add wave -noupdate -radix unsigned /niosII_tb/niosii_inst/sem/ram_addr
add wave -noupdate /niosII_tb/niosii_inst/sem/ram_wrdata add wave -noupdate -radix hexadecimal /niosII_tb/niosii_inst/sem/ram_wrdata
add wave -noupdate /niosII_tb/niosii_inst/sem/train add wave -noupdate /niosII_tb/niosii_inst/sem/train
add wave -noupdate /niosII_tb/niosii_inst/sem/red add wave -noupdate /niosII_tb/niosii_inst/sem/red
add wave -noupdate /niosII_tb/niosii_inst/sem/yellow add wave -noupdate /niosII_tb/niosii_inst/sem/yellow
add wave -noupdate /niosII_tb/niosii_inst/sem/green add wave -noupdate /niosII_tb/niosii_inst/sem/green
add wave -noupdate /niosII_tb/niosii_inst/sem/run add wave -noupdate /niosII_tb/niosii_inst/sem/run
add wave -noupdate /niosII_tb/niosii_inst/sem/divider add wave -noupdate /niosII_tb/niosii_inst/sem/divider
add wave -noupdate /niosII_tb/niosii_inst/sem/divisor add wave -noupdate -radix hexadecimal /niosII_tb/niosii_inst/sem/divisor
add wave -noupdate /niosII_tb/niosii_inst/sem/contr add wave -noupdate /niosII_tb/niosii_inst/sem/contr
add wave -noupdate /niosII_tb/niosii_inst/sem/colors add wave -noupdate /niosII_tb/niosii_inst/sem/colors
add wave -noupdate /niosII_tb/niosii_inst/sem/cntdiv add wave -noupdate -radix hexadecimal /niosII_tb/niosii_inst/sem/cntdiv
add wave -noupdate /niosII_tb/niosii_inst/sem/enacnt add wave -noupdate /niosII_tb/niosii_inst/sem/enacnt
add wave -noupdate -divider jtag add wave -noupdate -divider jtag
add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_irq add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_irq
@ -43,7 +43,7 @@ add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_read_n
add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_write_n add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_write_n
add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_writedata add wave -noupdate /niosII_tb/niosii_inst/jtag_uart/av_writedata
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {22 ps} 0} WaveRestoreCursors {{Cursor 1} {799999523 ps} 0}
quietly wave cursor active 1 quietly wave cursor active 1
configure wave -namecolwidth 275 configure wave -namecolwidth 275
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
@ -59,6 +59,6 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {0 ps} {662 ps}
run 800us run 800us
wave zoom full

View File

@ -21,16 +21,15 @@ int main()
//program divisors //program divisors
p = (alt_u32*) SEM_RAM_SLAVE_BASE; p = (alt_u32*) SEM_RAM_SLAVE_BASE;
for (i = 0; i < TIME_SETS; i++) { for (i = 0; i < TIME_SETS; i++) {
tmp = 0;
for (j = TIME_STATES; j > 0; j--) { for (j = TIME_STATES; j > 0; j--) {
tmp = (tmp << 32) | divisors[i][j - 1]; *p = divisors[i][j - 1];
alt_dcache_flush();
++p;
} }
*p = tmp;
p++;
} }
//since we use pointers (cached data access) to write divisor RAM, //since we use pointers (cached data access) to write divisor RAM,
//and not direct i/o access with IOWR, we need to flush cache //and not direct i/o access with IOWR, we need to flush cache
alt_dcache_flush(); // alt_dcache_flush();
//select timeset and run semafor //select timeset and run semafor
IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x00); IOWR_ALTERA_AVALON_SEM_DIVSET(SEM_CTL_SLAVE_BASE,0x00);

View File

@ -2,7 +2,7 @@
<project> <project>
<configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II"> <configuration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.283370529" name="Nios II">
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider"> <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
<provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="1701080960758821589" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true"> <provider class="com.altera.sbtgui.project.importer.Nios2GCCBuiltinSpecsDetector" console="false" env-hash="-136685873252219664" id="altera.tool.Nios2GCCBuiltinSpecsDetector" keep-relative-paths="false" name="Nios II GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/> <language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/> <language-scope id="org.eclipse.cdt.core.g++"/>
</provider> </provider>

View File

@ -2,11 +2,11 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema"> <sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType> <BspType>hal</BspType>
<BspVersion>default</BspVersion> <BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>24.12.2022 2:19:40</BspGeneratedTimeStamp> <BspGeneratedTimeStamp>Jan 17, 2023 7:10:10 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1671833980256</BspGeneratedUnixTimeStamp> <BspGeneratedUnixTimeStamp>1673968210656</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</BspGeneratedLocation> <BspGeneratedLocation>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile> <BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>..\..\niosII.sopcinfo</SopcDesignFile> <SopcDesignFile>../../niosII.sopcinfo</SopcDesignFile>
<JdiFile>default</JdiFile> <JdiFile>default</JdiFile>
<Cpu>cpu</Cpu> <Cpu>cpu</Cpu>
<SchemaVersion>1.9</SchemaVersion> <SchemaVersion>1.9</SchemaVersion>

View File

@ -7,7 +7,7 @@
<td width="20%" bgcolor="#77BBFF">BSP Type:</td><td>hal</td> <td width="20%" bgcolor="#77BBFF">BSP Type:</td><td>hal</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">SOPC Design File:</td><td>..\..\niosII.sopcinfo</td> <td width="20%" bgcolor="#77BBFF">SOPC Design File:</td><td>../../niosII.sopcinfo</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">Quartus JDI File:</td><td>default</td> <td width="20%" bgcolor="#77BBFF">Quartus JDI File:</td><td>default</td>
@ -22,13 +22,13 @@
<td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td> <td width="20%" bgcolor="#77BBFF">BSP Version:</td><td>default</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>24.12.2022 2:19:40</td> <td width="20%" bgcolor="#77BBFF">BSP Generated On:</td><td>Jan 17, 2023 7:10:10 PM</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1671833980256</td> <td width="20%" bgcolor="#77BBFF">BSP Generated Timestamp:</td><td>1673968210656</td>
</tr> </tr>
<tr mode="wrap"> <tr mode="wrap">
<td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>C:\Software\FPGA\iu3-31m\Lab2\Top\software\semafor_bsp</td> <td width="20%" bgcolor="#77BBFF">BSP Generated Location:</td><td>/home/ovchinnikov_ii@RISDE.ru/Documents/Lab2/Top/software/semafor_bsp</td>
</tr> </tr>
</table> </table>
<br> <br>