fpga-lab-2/Top/niosII/synthesis/submodules
Ivan I. Ovchinnikov dad79c26fb wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
..
altera_avalon_sc_fifo.v wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
altera_merlin_arbitrator.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
altera_merlin_burst_uncompressor.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
altera_merlin_master_agent.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
altera_merlin_master_translator.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
altera_merlin_slave_agent.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
altera_merlin_slave_translator.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
altera_reset_controller.sdc wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
altera_reset_controller.v wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
altera_reset_synchronizer.v wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
dec.sv Merge remote-tracking branch 'my/simulation' into simulation preferring their 2023-01-24 15:05:03 +03:00
niosII_cpu.v pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_cpu_cpu.sdc reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_debug_slave_sysclk.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_debug_slave_tck.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_debug_slave_wrapper.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_ociram_default_contents.mif reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_cpu_cpu_rf_ram_a.mif wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_cpu_cpu_rf_ram_b.mif wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_cpu_cpu_test_bench.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_irq_mapper.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_jtag_uart.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_mem.hex wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mem.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
niosII_mm_interconnect_0.v wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_avalon_st_adapter.v wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv pt2 done, qsys added, compiled successfully 2022-10-19 13:25:43 +03:00
niosII_mm_interconnect_0_cmd_demux.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_cmd_demux_001.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_cmd_mux.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_cmd_mux_002.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_router.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_router_001.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_router_002.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_router_004.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_router_008.sv done in hardware 2023-01-24 12:46:22 +03:00
niosII_mm_interconnect_0_rsp_demux.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_rsp_mux.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_mm_interconnect_0_rsp_mux_001.sv wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
niosII_sys_clk_timer.v reported lr2 + individual 2023-01-18 16:45:45 +03:00
periodram.v done in hardware 2023-01-24 12:46:22 +03:00