ivan-igorevich
/
fpga-lab-2
0
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

merge into: ivan-igorevich:master
Branches Tags
ivan-igorevich:master
ivan-igorevich:simulation
ivan-igorevich:lab3
...
pull from: ivan-igorevich:simulation
Branches Tags
ivan-igorevich:simulation
ivan-igorevich:lab3
ivan-igorevich:master

19 Commits
master ... simulation

Author SHA1 Message Date
Ivan I. Ovchinnikov e53eb0ff97 done lr4, programmed hardware 2023-02-07 16:10:37 +03:00
Ivan I. Ovchinnikov b551fd0a26 work board parameters 2023-02-07 13:31:34 +03:00
Ivan I. Ovchinnikov dad79c26fb wip lab4, nios connected, ready to program 2023-01-27 18:04:01 +03:00
Ivan I. Ovchinnikov 22f16bc090 wip lab4, tested module 2023-01-27 17:06:29 +03:00
Ivan I. Ovchinnikov 3b13bb1166 wip lab4, phase inc+sine 2023-01-27 11:15:11 +03:00
Ivan I. Ovchinnikov 77e2cf25d3 Merge remote-tracking branch 'my/simulation' into simulation preferring their 
# Conflicts:
#	Top/niosII.sopcinfo
#	Top/semafor.qws
#	Top/software/semafor/.settings/language.settings.xml
#	Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf
#	Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map
#	Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.objdump
#	Top/software/semafor/mem_init/hdl_sim/niosII_mem.dat
#	Top/software/semafor/mem_init/hdl_sim/niosII_mem.sym
#	Top/software/semafor/mem_init/niosII_mem.hex
#	Top/software/semafor/obj/default/runtime/sim/mentor/wave.do
#	Top/software/semafor/sem.c
#	Top/software/semafor_bsp/.settings/language.settings.xml
#	Top/software/semafor_bsp/libhal_bsp.a
#	Top/software/semafor_bsp/settings.bsp
#	Top/software/semafor_bsp/summary.html
 2023-01-24 15:05:03 +03:00
Ivan I. Ovchinnikov d2e26e53f7 done in hardware 2023-01-24 12:46:22 +03:00
Ivan I. Ovchinnikov fe241bc479 trailing files 2023-01-18 16:51:49 +03:00
Ivan I. Ovchinnikov f961f923b1 reported lr2 + individual 2023-01-18 16:45:45 +03:00
Ivan I. Ovchinnikov b86b8e55dc simulated individual, looks ok 2022-12-24 02:08:20 +03:00
Ivan I. Ovchinnikov 881e124d27 ram32ok 2022-12-22 22:27:05 +03:00
Ivan I. Ovchinnikov 6291090406 added ram hex(no luck) 2022-12-22 17:32:08 +03:00
Ivan I. Ovchinnikov f6e75a12d5 periodram x32 unchecked 2022-12-22 15:20:49 +03:00
Ivan I. Ovchinnikov 1589af18e7 sem ram widening correct, generate testbench in PD was needed 2022-12-19 22:48:11 +03:00
Ivan I. Ovchinnikov def7e9c9c4 pt3 done 2022-12-08 16:08:03 +03:00
Ivan I. Ovchinnikov edd4b417d3 gitignore update 2022-12-08 16:05:35 +03:00
Ivan I. Ovchinnikov f6d43e003a pt3.12 modelled 2022-10-24 22:35:24 +03:00
Ivan I. Ovchinnikov a5eddcc776 pt3.1-7 software project creation, branching for hardware and simulation settings 2022-10-19 15:03:52 +03:00
Ivan I. Ovchinnikov 01f41dbf51 pt2 sopcinfo compile changed 2022-10-19 13:31:51 +03:00
132 changed files with 58943 additions and 30170 deletions
Show Stats Expand all files Collapse all files

61
.gitignore vendored
View File

@ -1,19 +1,42 @@
*.pdf
*.rpt
*.bak
.#*
/db
/incremental_db
/output_files
/simulation
/.qsys*
# /atom_netlists
/testbenches/*.bak
/common_uart/*.bak
/build/*
!/build/*.pdf
!/build/tikz*.sty
*.pdf
*.rpt
*.bak
.#*
#*.*#
.*~
/db
/incremental_db
/output_files
/simulation
/.qsys*
# /atom_netlists
greybox_tmp/
.qsys_edit/
synthesis/
*output_files/
simulation/
obj/
drivers/
HAL/
Part_test/
.metadata/
.settings/
RemoteSystemsTempFiles/
aldec/
cadence/
synopsys/
db/
incremental_db/
*.xml
/testbenches/*.bak
/common_uart/*.bak
/build/*
!/build/*.pdf
!/build/tikz*.sty
!/Top/software/semafor/obj/default/runtime/sim/mentor/wave.do

10
HDL/IP/periodram.qip
View File

@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "14.0"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"]
set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "periodram.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "periodram_inst.v"]

436
HDL/IP/periodram.v
View File

@ -1,214 +1,222 @@
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: periodram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.2 Build 209 09/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module periodram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [3:0] rdaddress;
input [1:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 2,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: periodram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module periodram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "periodram.rif"
`else
altsyncram_component.init_file = "periodram.hex"
`endif
,
altsyncram_component.init_file_layout = "PORT_B",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

16
HDL/IP/periodram_inst.v
View File

@ -1,8 +1,8 @@
periodram periodram_inst (
.clock ( clock_sig ),
.data ( data_sig ),
.rdaddress ( rdaddress_sig ),
.wraddress ( wraddress_sig ),
.wren ( wren_sig ),
.q ( q_sig )
);
periodram periodram_inst (
.clock ( clock_sig ),
.data ( data_sig ),
.rdaddress ( rdaddress_sig ),
.wraddress ( wraddress_sig ),
.wren ( wren_sig ),
.q ( q_sig )
);

242
HDL/IP/sine256.mif Normal file
View File

@ -0,0 +1,242 @@
WIDTH = 8;
DEPTH = 256;
ADDRESS_RADIX = DEC;
DATA_RADIX = HEX;
CONTENT BEGIN
0 : 02;
1 : 05;
2 : 08;
3 : 0B;
4 : 0E;
5 : 11;
6 : 14;
7 : 17;
8 : 1A;
9 : 1D;
10 : 20;
11 : 23;
12 : 26;
13 : 29;
14 : 2C;
15 : 2F;
16 : 32;
17 : 35;
18 : 38;
19 : 3A;
20 : 3D;
21 : 40;
22 : 43;
23 : 45;
24 : 48;
25 : 4A;
26 : 4D;
27 : 4F;
28 : 52;
29 : 54;
30 : 56;
31 : 59;
32 : 5B;
33 : 5D;
34 : 5F;
35 : 61;
36 : 63;
37 : 65;
38 : 67;
39 : 69;
40 : 6A;
41 : 6C;
42 : 6E;
43 : 6F;
44 : 71;
45 : 72;
46 : 73;
47 : 75;
48 : 76;
49 : 77;
50 : 78;
51 : 79;
52 : 7A;
53 : 7B;
54 : 7C;
55 : 7C;
56 : 7D;
57 : 7D;
[58..69] : 7E;
70 : 7D;
71 : 7D;
72 : 7C;
73 : 7C;
74 : 7B;
75 : 7A;
76 : 79;
77 : 78;
78 : 77;
79 : 76;
80 : 75;
81 : 73;
82 : 72;
83 : 71;
84 : 6F;
85 : 6E;
86 : 6C;
87 : 6A;
88 : 69;
89 : 67;
90 : 65;
91 : 63;
92 : 61;
93 : 5F;
94 : 5D;
95 : 5B;
96 : 59;
97 : 56;
98 : 54;
99 : 52;
100 : 4F;
101 : 4D;
102 : 4A;
103 : 48;
104 : 45;
105 : 43;
106 : 40;
107 : 3D;
108 : 3A;
109 : 38;
110 : 35;
111 : 32;
112 : 2F;
113 : 2C;
114 : 29;
115 : 26;
116 : 23;
117 : 20;
118 : 1D;
119 : 1A;
120 : 17;
121 : 14;
122 : 11;
123 : 0E;
124 : 0B;
125 : 08;
126 : 05;
127 : 02;
128 : FE;
129 : FB;
130 : F8;
131 : F5;
132 : F2;
133 : EF;
134 : EC;
135 : E9;
136 : E6;
137 : E3;
138 : E0;
139 : DD;
140 : DA;
141 : D7;
142 : D4;
143 : D1;
144 : CE;
145 : CB;
146 : C8;
147 : C6;
148 : C3;
149 : C0;
150 : BD;
151 : BB;
152 : B8;
153 : B6;
154 : B3;
155 : B1;
156 : AE;
157 : AC;
158 : AA;
159 : A7;
160 : A5;
161 : A3;
162 : A1;
163 : 9F;
164 : 9D;
165 : 9B;
166 : 99;
167 : 97;
168 : 96;
169 : 94;
170 : 92;
171 : 91;
172 : 8F;
173 : 8E;
174 : 8D;
175 : 8B;
176 : 8A;
177 : 89;
178 : 88;
179 : 87;
180 : 86;
181 : 85;
182 : 84;
183 : 84;
184 : 83;
185 : 83;
[186..197] : 82;
198 : 83;
199 : 83;
200 : 84;
201 : 84;
202 : 85;
203 : 86;
204 : 87;
205 : 88;
206 : 89;
207 : 8A;
208 : 8B;
209 : 8D;
210 : 8E;
211 : 8F;
212 : 91;
213 : 92;
214 : 94;
215 : 96;
216 : 97;
217 : 99;
218 : 9B;
219 : 9D;
220 : 9F;
221 : A1;
222 : A3;
223 : A5;
224 : A7;
225 : AA;
226 : AC;
227 : AE;
228 : B1;
229 : B3;
230 : B6;
231 : B8;
232 : BB;
233 : BD;
234 : C0;
235 : C3;
236 : C6;
237 : C8;
238 : CB;
239 : CE;
240 : D1;
241 : D4;
242 : D7;
243 : DA;
244 : DD;
245 : E0;
246 : E3;
247 : E6;
248 : E9;
249 : EC;
250 : EF;
251 : F2;
252 : F5;
253 : F8;
254 : FB;
255 : FE;
END;

5
HDL/IP/sinelut.qip Normal file
View File

@ -0,0 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "18.1"
set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "sinelut.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "sinelut_bb.v"]

159
HDL/IP/sinelut.v Normal file
View File

@ -0,0 +1,159 @@
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sinelut.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sinelut (
address,
clock,
q);
input [7:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "sine256.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "sine256.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "sine256.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

110
HDL/IP/sinelut_bb.v Normal file
View File

@ -0,0 +1,110 @@
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sinelut.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
module sinelut (
address,
clock,
q);
input [7:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "sine256.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "sine256.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sinelut_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

5
HDL/IP/sinelut_inst.v Normal file
View File

@ -0,0 +1,5 @@
sinelut sinelut_inst (
.address ( address_sig ),
.clock ( clock_sig ),
.q ( q_sig )
);

271
HDL/dec.sv
View File

@ -1,132 +1,155 @@
module dec
#(m = 8)
(
//clock and reset
input logic clk, clrn,
//control slave
input logic ctl_wr, ctl_rd,
input logic ctl_addr,
input logic [31:0] ctl_wrdata,
output logic [31:0] ctl_rddata,
//memory slave
input logic ram_wr,
input logic [1:0] ram_addr,
input logic [31:0] ram_wrdata,
//external ports
input logic train,
output logic red, yellow, green
);
logic run;
logic [1:0] divider;
logic [m-1:0] divisor;
logic [1:0] contr;
logic [2:0] colors;
logic [m-1:0] cntdiv;
logic enacnt;
#(m = 32)
(
//clock and reset
input logic clk, clrn,
//control slave
input logic ctl_wr, ctl_rd,
input logic ctl_addr,
input logic [31:0] ctl_wrdata,
output logic [31:0] ctl_rddata,
//memory slave
input logic ram_wr,
input logic [3:0] ram_addr,
input logic [31:0] ram_wrdata,
//external ports
input logic train,
output logic red, yellow, green
);
//control slave logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
run <= 0;
divider <= 0;
end
else
begin
if (ctl_wr)
begin
case (ctl_addr)
1'b0: run <= ctl_wrdata[0];
1'b1: divider <= ctl_wrdata[1:0];
endcase
end
end
end
always_comb
begin
case (ctl_addr)
1'b0: ctl_rddata = {31'b0,run};
1'b1: ctl_rddata = {30'b0,divider};
default: ctl_rddata = 'bx;
endcase
end
//semaphore logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn) cntdiv<=0;
else
begin
if (train | ~run) cntdiv<=0;
else
begin
if (enacnt) cntdiv<=0;
else cntdiv<=cntdiv+1;
end
end
end
always_comb
begin
enacnt=(cntdiv==divisor);
end
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
colors <= 3'b100;
end
else
begin
if (train | ~run)
begin
colors <= 3'b100;
end
else
begin
if (enacnt)
begin
case (colors)
3'b100: colors <= 3'b010;
3'b010: colors <= 3'b011;
3'b011: colors <= 3'b001;
3'b001: colors <= 3'b001;
default: colors <= 3'b100;
endcase
end
end
end
end
always_comb
begin
case (colors)
3'b100: contr = 2'b00;
3'b010: contr = 2'b01;
3'b011: contr = 2'b10;
3'b001: contr = 2'b11;
default : contr = 2'b00;
typedef enum logic [1:0] {RED, YELLOW, BLINK, GREEN} FSMStates;
logic run;
logic [1:0] divider;
logic [1:0] state;
logic [31:0] greenSaved;
logic [31:0] greenCount;
logic [m-1:0] divisor;
logic [1:0] contr;
logic [2:0] colors;
logic [m-1:0] cntdiv;
logic enacnt;
//control slave logic
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn) begin
run <= 0;
divider <= 0;
end else begin
if (ctl_wr) begin
case (ctl_addr)
1'b0: run <= ctl_wrdata[0];
1'b1: divider <= ctl_wrdata[1:0];
endcase
end
end
end
always_comb begin
case (ctl_addr)
1'b0: ctl_rddata = {31'b0,run};
1'b1: ctl_rddata = {30'b0,divider};
default: ctl_rddata = 'bx;
endcase
end
assign red = colors[2];
assign yellow = colors[1];
assign green = colors[0];
periodram b2v_inst3(
.clock(clk),
.data (ram_wrdata),
.wraddress (ram_addr),
.wren (ram_wr),
.rdaddress({divider,contr}),
.q(divisor)
);
//semaphore logic
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn)
cntdiv <= 0;
else begin
if (train | ~run)
cntdiv<=0;
else begin
if (enacnt) cntdiv<=0;
else cntdiv<=cntdiv+1;
end
end
end
// we don't enable counters, if color is green
always_comb begin
enacnt = ((cntdiv == divisor) && !(colors == 3'b001));
end
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn) begin
colors <= 3'b001;
state <= GREEN;
greenCount <= 32'd0;
end else begin
if (~run) begin
colors <= 3'b001;
state <= GREEN;
end
if (train) begin
colors <= 3'b100;
state <= RED;
greenSaved <= divisor;
greenCount <= divisor;
end else begin
case (state)
RED: begin
colors <= 3'b100;
if (enacnt) begin
state <= YELLOW;
greenSaved <= divisor;
end
end
YELLOW: begin
colors <= 3'b010;
if (enacnt) begin
state <= BLINK;
end
end
BLINK: begin
if (enacnt) begin
state <= GREEN;
end
if (greenSaved[0] == 0) begin
colors <= 3'b011;
end else begin
greenCount <= greenCount - 1'b1;
if (greenCount == 32'd0) begin
colors[1] <= ~colors[1];
greenCount <= greenSaved;
end
end
end
GREEN: begin
colors <= 3'b001;
end
default: colors <= 3'b100;
endcase
end
end
end
assign contr = state;
// always_comb begin
// case (state)
// 2'b00: contr = 2'b00;
// 2'b01: contr = 2'b01;
// 2'b10: contr = 2'b10;
// 2'b11: contr = 2'b11;
// default : contr = 2'b00;
// endcase
// end
assign red = colors[2];
assign yellow = colors[1];
assign green = colors[0];
periodram b2v_inst3
(
.clock(clk),
.data (ram_wrdata),
.wraddress (ram_addr),
.wren (ram_wr),
.rdaddress({divider,contr}),
.q(divisor)
);
endmodule

23
HDL/phacc.sv Normal file
View File

@ -0,0 +1,23 @@
module phacc
#(
parameter unsigned WIDTH = 14
) (
input logic [7:0] phinc,
input clk,
input reset,
output [7:0] phase
);
logic [WIDTH - 1 : 0] sum;
always_ff @(posedge clk, negedge reset) begin
if (~reset) begin
sum <= 0;
end else begin
sum <= sum + phinc;
end
end
assign phase = sum[WIDTH - 1 : WIDTH - 8];
endmodule

23
HDL/sdmod.sv Normal file
View File

@ -0,0 +1,23 @@
module sdmod (
input signed [7:0] val,
input clk,
input reset,
output daco
);
logic out;
logic signed [7:0] eps;
logic signed [8:0] un;
always_ff @(posedge clk, negedge reset) begin
if (~reset) begin
un <= 9'd0;
end else begin
un <= val - eps;
end
end
assign out = (un >= $signed(9'd0)) ? 1'd1 : 1'd0;
assign eps = (un >= $signed(9'd0)) ? $signed(9'd126) - un : $signed(-9'd126) - un;
assign daco = out;
endmodule

37
HDL/sigdel.sv Normal file
View File

@ -0,0 +1,37 @@
//top-level module
module sigdel
#(
PHACC_WIDTH = 27
) (
//clock and reset
input logic clk, clr_n,
//control slave
input logic [31:0] wr_data,
input logic wr_n,
output logic fout
);
logic [7:0] phinc_val, phase, sine;
//control slave logic
always_ff @ (posedge clk or negedge clr_n) begin
if (!clr_n) begin
phinc_val[7:0] <= 8'd0;
end else begin
if (!wr_n) begin
phinc_val[7:0] <= wr_data[31:0];
end
end
end
phacc phacc_inst (.phinc(1'b1), .clk(clk), .reset(clr_n), .phase(phase));
defparam phacc_inst.WIDTH = PHACC_WIDTH;
sinelut sinelut_inst (
.address (phase), .clock (clk), .q(sine)
);
sdmod sdmod_inst (
.val(sine), .clk(clk), .reset(clr_n), .daco(fout)
);
endmodule

38
Testbench/dec/.gitignore vendored
View File

@ -1,19 +1,19 @@
*.pdf
*.rpt
*.bak
.#*
/db
/incremental_db
/output_files
/simulation
/.qsys*
# /atom_netlists
/testbenches/*.bak
/common_uart/*.bak
/build/*
!/build/*.pdf
!/build/tikz*.sty
*.pdf
*.rpt
*.bak
.#*
/db
/incremental_db
/output_files
/simulation
/.qsys*
# /atom_netlists
/testbenches/*.bak
/common_uart/*.bak
/build/*
!/build/*.pdf
!/build/tikz*.sty

136
Testbench/dec/dec.qsf
View File

@ -1,67 +1,69 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:14:06 October 18, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# dec_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22A7
set_global_assignment -name TOP_LEVEL_ENTITY dec
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:14:06 OCTOBER 18, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name QIP_FILE ../../HDL/IP/periodram.qip
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/dec.sv
set_global_assignment -name SYSTEMVERILOG_FILE dec_tb.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dec_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:14:06 October 18, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# dec_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22A7
set_global_assignment -name TOP_LEVEL_ENTITY dec
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:14:06 OCTOBER 18, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 125
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name QIP_FILE ../../HDL/IP/periodram.qip
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/dec.sv
set_global_assignment -name SYSTEMVERILOG_FILE dec_tb.sv
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH dec_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME dec_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id dec_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME dec_tb -section_id dec_tb
set_global_assignment -name EDA_TEST_BENCH_FILE dec_tb.sv -section_id dec_tb
set_global_assignment -name HEX_FILE periodram.hex
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
Testbench/dec/dec.qws
View File

Binary file not shown.

256
Testbench/dec/dec_tb.sv
View File

@ -1,128 +1,128 @@
`timescale 1 ns/1 ns
module dec_tb();
// Wires and variables to connect to UUT (unit under test)
logic clk, clrn, train;
logic r, y, g;
logic [1:0] div;
logic ctl_wr, ctl_rd;
logic ctl_addr;
logic [31:0] ctl_wrdata;
logic [31:0] ctl_rddata;
logic ram_wr;
logic [1:0] ram_addr;
logic [31:0] ram_wrdata;
logic [31:0] divisor[3:0] = {
{8'd10, 8'd70, 8'd50, 8'd20},
{8'd10, 8'd30, 8'd40, 8'd30},
{8'd10, 8'd30, 8'd10, 8'd100},
{8'd10, 8'd60, 8'd80, 8'd50}
};
// Instantiate UUT
dec my_sem(
.clk(clk), .clrn(clrn),
.ctl_wr(ctl_wr), .ctl_rd(ctl_rd),
.ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
.ram_wr(ram_wr),
.ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
.train(train), .red(r), .yellow(y), .green(g)
);
// Clock definition
initial begin
clk = 0;
forever #10 clk = ~clk;
end
// Divisor and train definition
initial begin
//initial reset
clrn = 0;
div = 0;
train = 0;
//take reset off
@(negedge clk) clrn = 1;
//configure semaphore
for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM
write_reg_transaction(1,div); //write initial divisor
write_reg_transaction(0,1); //enable semaphore
//run trains
repeat (4)
begin
repeat (10) @(posedge clk);
train=1;
repeat (4) @(posedge clk);
train=0;
wait ({r,y,g}==3'b001);
repeat (10) @(posedge clk);
write_reg_transaction(1,div);
div=div+1;
end
//wait a little
repeat (10) @(posedge clk);
$stop;
end
//Single register write transaction task
task write_reg_transaction;
//input signals
input [1:0] offs;
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ctl_wr = 1;
ctl_addr = offs;
ctl_wrdata = val;
@(posedge clk);
//deassert signals
ctl_wr = 0;
ctl_addr = 'bx;
ctl_wrdata = 'bx;
end
endtask
//Single register read transaction task
task read_reg_transaction;
//input signals
input [1:0] offs;
output [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ctl_rd = 1;
ctl_addr = offs;
@(posedge clk);
val = ctl_rddata;
//deassert signals
ctl_rd = 0;
ctl_addr = 'bx;
end
endtask
//RAM write transaction task
task write_ram_transaction;
//input signals
input [1:0] offs;
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ram_wr = 1;
ram_addr = offs;
ram_wrdata = val;
@(posedge clk);
//deassert signals
ram_wr = 0;
ram_addr = 'bx;
ram_wrdata = 'bx;
end
endtask
endmodule
`timescale 1 ns/1 ns
module dec_tb();
// Wires and variables to connect to UUT (unit under test)
logic clk, clrn, train;
logic r, y, g;
logic [1:0] div;
logic ctl_wr, ctl_rd;
logic ctl_addr;
logic [31:0] ctl_wrdata;
logic [31:0] ctl_rddata;
logic ram_wr;
logic [1:0] ram_addr;
logic [31:0] ram_wrdata;
logic [31:0] divisor[3:0] = {
{8'd11, 8'd71, 8'd51, 8'd21},
{8'd11, 8'd31, 8'd41, 8'd31},
{8'd11, 8'd31, 8'd11, 8'd101},
{8'd11, 8'd61, 8'd81, 8'd51}
};
// Instantiate UUT
dec my_sem(
.clk(clk), .clrn(clrn),
.ctl_wr(ctl_wr), .ctl_rd(ctl_rd),
.ctl_addr(ctl_addr), .ctl_wrdata(ctl_wrdata), .ctl_rddata(ctl_rddata),
.ram_wr(ram_wr),
.ram_addr(ram_addr), .ram_wrdata(ram_wrdata),
.train(train), .red(r), .yellow(y), .green(g)
);
// Clock definition
initial begin
clk = 0;
forever #10 clk = ~clk;
end
// Divisor and train definition
initial begin
//initial reset
clrn = 0;
div = 0;
train = 0;
//take reset off
@(negedge clk) clrn = 1;
//configure semaphore
for (int i=0; i<4; i++) write_ram_transaction(i,divisor[i]); //write divisor RAM
write_reg_transaction(1,div); //write initial divisor
write_reg_transaction(0,1); //enable semaphore
//run trains
repeat (4)
begin
repeat (10) @(posedge clk);
train=1;
repeat (4) @(posedge clk);
train=0;
wait ({r,y,g}==3'b001);
repeat (10) @(posedge clk);
write_reg_transaction(1,div);
div=div+1;
end
//wait a little
repeat (10) @(posedge clk);
$stop;
end
//Single register write transaction task
task write_reg_transaction;
//input signals
input [1:0] offs;
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ctl_wr = 1;
ctl_addr = offs;
ctl_wrdata = val;
@(posedge clk);
//deassert signals
ctl_wr = 0;
ctl_addr = 'bx;
ctl_wrdata = 'bx;
end
endtask
//Single register read transaction task
task read_reg_transaction;
//input signals
input [1:0] offs;
output [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ctl_rd = 1;
ctl_addr = offs;
@(posedge clk);
val = ctl_rddata;
//deassert signals
ctl_rd = 0;
ctl_addr = 'bx;
end
endtask
//RAM write transaction task
task write_ram_transaction;
//input signals
input [1:0] offs;
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
ram_wr = 1;
ram_addr = offs;
ram_wrdata = val;
@(posedge clk);
//deassert signals
ram_wr = 0;
ram_addr = 'bx;
ram_wrdata = 'bx;
end
endtask
endmodule

17
Testbench/dec/periodram.hex Normal file
View File

@ -0,0 +1,17 @@
:040000000000006498
:040001000000006497
:0400020000000032C8
:040003000000000AEF
:040004000000006494
:04000500000000C82F
:040006000000006492
:040007000000000AEB
:04000800000000965E
:04000900000000FAF9
:04000A00000000C82A
:04000B000000000AE7
:04000C00000000FAF6
:04000D00000000FAF5
:04000E00000000FAF4
:04000F000000000AE3
:00000001FF

60
Testbench/dec/semafor.qpf
View File

@ -1,30 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:14:06 October 18, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "16:14:06 October 18, 2022"
# Revisions
PROJECT_REVISION = "dec"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:14:06 October 18, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "16:14:06 October 18, 2022"
# Revisions
PROJECT_REVISION = "dec"

70
Testbench/dec/wave.do
View File

@ -1,35 +1,35 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /dec_tb/clk
add wave -noupdate /dec_tb/clrn
add wave -noupdate /dec_tb/train
add wave -noupdate /dec_tb/r
add wave -noupdate /dec_tb/y
add wave -noupdate /dec_tb/g
add wave -noupdate /dec_tb/div
add wave -noupdate /dec_tb/ctl_wr
add wave -noupdate /dec_tb/ctl_rd
add wave -noupdate /dec_tb/ctl_addr
add wave -noupdate /dec_tb/ctl_wrdata
add wave -noupdate /dec_tb/ctl_rddata
add wave -noupdate /dec_tb/ram_wr
add wave -noupdate /dec_tb/ram_addr
add wave -noupdate /dec_tb/ram_wrdata
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {3346003 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {15928500 ps}
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /dec_tb/clk
add wave -noupdate /dec_tb/clrn
add wave -noupdate /dec_tb/train
add wave -noupdate /dec_tb/r
add wave -noupdate /dec_tb/y
add wave -noupdate /dec_tb/g
add wave -noupdate /dec_tb/div
add wave -noupdate /dec_tb/ctl_wr
add wave -noupdate /dec_tb/ctl_rd
add wave -noupdate /dec_tb/ctl_addr
add wave -noupdate /dec_tb/ctl_wrdata
add wave -noupdate /dec_tb/ctl_rddata
add wave -noupdate /dec_tb/ram_wr
add wave -noupdate /dec_tb/ram_addr
add wave -noupdate /dec_tb/ram_wrdata
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {3346003 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {15928500 ps}

47
Testbench/sigdel/inc_lut_tb.sv Normal file
View File

@ -0,0 +1,47 @@
`timescale 1 ns/1 ns
module inc_lut_tb();
// Parameters
localparam CLK_PRD = 20;
localparam PHACC_WIDTH = 14;
logic clk, clr_n, wr_n;
logic [7:0] phinc_val, phase, sine;
// Instantiate UUT and connect used ports
phacc phacc(.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
defparam phacc.WIDTH = PHACC_WIDTH;
sinelut sinelut_inst (
.address (phase), .clock (clk), .q(sine)
);
// Clock definition
initial begin
clk = 0;
forever #(CLK_PRD/2) clk = ~clk;
end
// Reset and initial values definition
initial begin
clr_n = 0;
#(CLK_PRD*5) clr_n = 1;
end
// Bus write transaction simulation
initial begin
// Wait until system is out of reset
@(posedge clr_n);
phinc_val=(2**(PHACC_WIDTH - 8));
if ((phinc_val <= 255) && (phinc_val != 0)) begin
#(CLK_PRD * 256 * 5) $stop;
end else begin
$display("Error: value of phase increment is out of range! Stopped simulation.");
#1 $stop;
end
end
endmodule

55
Testbench/sigdel/lut_mod_tb.sv Normal file
View File

@ -0,0 +1,55 @@
`timescale 1 ns/1 ns
module lut_mod_tb();
// Parameters
localparam CLK_PRD = 20;
localparam PHACC_WIDTH = 14;
logic clk, clr_n, wr_n, daco;
logic [7:0] phinc_val, phase, sine;
// Instantiate UUT and connect used ports
phacc phacc (
.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase)
);
defparam phacc.WIDTH = PHACC_WIDTH;
sinelut sinelut_inst (
.address(phase), .clock(clk), .q(sine)
);
sdmod sdmod_inst (
.val(sine), .clk(clk), .reset(clr_n), .daco(daco)
// .val(8'd0), .clk(clk), .reset(clr_n), .daco(daco)
// .val(8'd255), .clk(clk), .reset(clr_n), .daco(daco)
);
// Clock definition
initial begin
clk = 0;
forever #(CLK_PRD/2) clk = ~clk;
end
// Reset and initial values definition
initial begin
clr_n = 0;
#(CLK_PRD*5) clr_n = 1;
end
// Bus write transaction simulation
initial begin
// Wait until system is out of reset
@(posedge clr_n);
phinc_val=(2**(PHACC_WIDTH - 8));
if ((phinc_val <= 255) && (phinc_val != 0)) begin
#(CLK_PRD * 256 * 10) $stop;
end else begin
$display("Error: value of phase increment is out of range! Stopped simulation.");
#1 $stop;
end
end
endmodule

30
Testbench/sigdel/sigdel.qpf Normal file
View File

@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 10:16:23 January 27, 2023
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "10:16:23 January 27, 2023"
# Revisions
PROJECT_REVISION = "sigdel"

79
Testbench/sigdel/sigdel.qsf Normal file
View File

@ -0,0 +1,79 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 10:16:23 January 27, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# sigdel_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE15F23C8
set_global_assignment -name TOP_LEVEL_ENTITY sigdel
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:16:23 JANUARY 27, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH sigdel_tb -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME inc_lut_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id inc_lut_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME inc_lut_tb -section_id inc_lut_tb
set_global_assignment -name EDA_TEST_BENCH_NAME lut_mod_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id lut_mod_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME lut_mod_tb -section_id lut_mod_tb
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/phacc.sv
set_global_assignment -name QIP_FILE ../../HDL/IP/sinelut.qip
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sigdel.sv
set_global_assignment -name SYSTEMVERILOG_FILE ../../HDL/sdmod.sv
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT simulation/modelsim/wave.do -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_FILE inc_lut_tb.sv -section_id inc_lut_tb
set_global_assignment -name EDA_TEST_BENCH_FILE lut_mod_tb.sv -section_id lut_mod_tb
set_global_assignment -name EDA_TEST_BENCH_NAME sigdel_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sigdel_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sigdel_tb -section_id sigdel_tb
set_global_assignment -name EDA_TEST_BENCH_FILE sigdel_tb.sv -section_id sigdel_tb
set_location_assignment PIN_T2 -to clk
set_location_assignment PIN_E4 -to clr_n
set_location_assignment PIN_E3 -to fout
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
Testbench/sigdel/sigdel.qws Normal file
View File

Binary file not shown.

37
Testbench/sigdel/sigdel.sv Normal file
View File

@ -0,0 +1,37 @@
//top-level module
module sigdel
#(
PHACC_WIDTH = 14
) (
//clock and reset
input logic clk, clr_n,
//control slave
input logic [31:0] wr_data,
input logic wr_n,
output logic fout
);
logic [7:0] phinc_val;
//control slave logic
always_ff @ (posedge clk or negedge clr_n) begin
if (!clr_n) begin
phinc_val[7:0] <= 8'd0;
end else begin
if (!wr_n) begin
phinc_val[7:0] <= wr_data[31:0];
end
end
end
phacc phacc_inst (.phinc(phinc_val), .clk(clk), .reset(clr_n), .phase(phase));
defparam phacc_inst.WIDTH = PHACC_WIDTH;
sinelut sinelut_inst (
.address (phase), .clock (clk), .q(sine)
);
sdmod sdmod_inst (
.val(sine), .clk(clk), .reset(clr_n), .daco(fout)
);
endmodule

81
Testbench/sigdel/sigdel_tb.sv Normal file
View File

@ -0,0 +1,81 @@
`timescale 1 ns/1 ns
module sigdel_tb();
// Parameters
localparam CLK_PRD = 20;
localparam SAMPLES_PRD = 256;
localparam OVERSAMPLING = 4;
localparam PHACC_WIDTH = 14;
// Wires and variables to connect to UUT (unit under test)
logic clk, clr_n, wr_n;
logic [31:0] wr_data;
logic [31:0] phinc_val;
logic fout;
// Instantiate UUT and connect used ports
sigdel dut(.clk(clk), .clr_n(clr_n), .wr_n(wr_n), .wr_data(wr_data), .fout(fout));
defparam dut.PHACC_WIDTH = PHACC_WIDTH;
// Clock definition
initial begin
clk = 0;
forever #(CLK_PRD/2) clk = ~clk;
end
// Reset and initial values definition
initial begin
clr_n = 0;
wr_n = 1;
wr_data = 'bx;
#(CLK_PRD*5) clr_n = 1;
end
// Bus write transaction simulation
initial begin
// Wait until system is out of reset
@(posedge clr_n);
// Check if phase increment for required accumulator width
// and oversamlpling ratio will fit in 8 bits
phinc_val=(2**(PHACC_WIDTH-8))/OVERSAMPLING;
if ((phinc_val <= 255) && (phinc_val != 0))
begin
// Write phase increment several clock cycles after reset
#(CLK_PRD*3) write_transaction(phinc_val);
// Wait for one sine period (for 14-bit phase accumulator case)
#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
#(CLK_PRD*3) write_transaction(phinc_val*5);
#(CLK_PRD*SAMPLES_PRD*OVERSAMPLING)
$stop;
end
else
begin
//Output simulation error
$display("Error: value of phase increment is out of range! Stopped simulation.");
//Stop simulation (small delay needed for $display to work)
#1 $stop;
end
end
//Single write transaction task
task write_transaction;
//input signals
input [31:0] val;
//transaction implementation
begin
@(posedge clk);
//assert signals for one clock cycle
wr_n = 0;
wr_data = val;
@(posedge clk);
//deassert signals
wr_n = 1;
wr_data = 'bx;
end
endtask
endmodule

242
Testbench/sigdel/sine256.mif Normal file
View File

@ -0,0 +1,242 @@
WIDTH = 8;
DEPTH = 256;
ADDRESS_RADIX = DEC;
DATA_RADIX = HEX;
CONTENT BEGIN
0 : 02;
1 : 05;
2 : 08;
3 : 0B;
4 : 0E;
5 : 11;
6 : 14;
7 : 17;
8 : 1A;
9 : 1D;
10 : 20;
11 : 23;
12 : 26;
13 : 29;
14 : 2C;
15 : 2F;
16 : 32;
17 : 35;
18 : 38;
19 : 3A;
20 : 3D;
21 : 40;
22 : 43;
23 : 45;
24 : 48;
25 : 4A;
26 : 4D;
27 : 4F;
28 : 52;
29 : 54;
30 : 56;
31 : 59;
32 : 5B;
33 : 5D;
34 : 5F;
35 : 61;
36 : 63;
37 : 65;
38 : 67;
39 : 69;
40 : 6A;
41 : 6C;
42 : 6E;
43 : 6F;
44 : 71;
45 : 72;
46 : 73;
47 : 75;
48 : 76;
49 : 77;
50 : 78;
51 : 79;
52 : 7A;
53 : 7B;
54 : 7C;
55 : 7C;
56 : 7D;
57 : 7D;
[58..69] : 7E;
70 : 7D;
71 : 7D;
72 : 7C;
73 : 7C;
74 : 7B;
75 : 7A;
76 : 79;
77 : 78;
78 : 77;
79 : 76;
80 : 75;
81 : 73;
82 : 72;
83 : 71;
84 : 6F;
85 : 6E;
86 : 6C;
87 : 6A;
88 : 69;
89 : 67;
90 : 65;
91 : 63;
92 : 61;
93 : 5F;
94 : 5D;
95 : 5B;
96 : 59;
97 : 56;
98 : 54;
99 : 52;
100 : 4F;
101 : 4D;
102 : 4A;
103 : 48;
104 : 45;
105 : 43;
106 : 40;
107 : 3D;
108 : 3A;
109 : 38;
110 : 35;
111 : 32;
112 : 2F;
113 : 2C;
114 : 29;
115 : 26;
116 : 23;
117 : 20;
118 : 1D;
119 : 1A;
120 : 17;
121 : 14;
122 : 11;
123 : 0E;
124 : 0B;
125 : 08;
126 : 05;
127 : 02;
128 : FE;
129 : FB;
130 : F8;
131 : F5;
132 : F2;
133 : EF;
134 : EC;
135 : E9;
136 : E6;
137 : E3;
138 : E0;
139 : DD;
140 : DA;
141 : D7;
142 : D4;
143 : D1;
144 : CE;
145 : CB;
146 : C8;
147 : C6;
148 : C3;
149 : C0;
150 : BD;
151 : BB;
152 : B8;
153 : B6;
154 : B3;
155 : B1;
156 : AE;
157 : AC;
158 : AA;
159 : A7;
160 : A5;
161 : A3;
162 : A1;
163 : 9F;
164 : 9D;
165 : 9B;
166 : 99;
167 : 97;
168 : 96;
169 : 94;
170 : 92;
171 : 91;
172 : 8F;
173 : 8E;
174 : 8D;
175 : 8B;
176 : 8A;
177 : 89;
178 : 88;
179 : 87;
180 : 86;
181 : 85;
182 : 84;
183 : 84;
184 : 83;
185 : 83;
[186..197] : 82;
198 : 83;
199 : 83;
200 : 84;
201 : 84;
202 : 85;
203 : 86;
204 : 87;
205 : 88;
206 : 89;
207 : 8A;
208 : 8B;
209 : 8D;
210 : 8E;
211 : 8F;
212 : 91;
213 : 92;
214 : 94;
215 : 96;
216 : 97;
217 : 99;
218 : 9B;
219 : 9D;
220 : 9F;
221 : A1;
222 : A3;
223 : A5;
224 : A7;
225 : AA;
226 : AC;
227 : AE;
228 : B1;
229 : B3;
230 : B6;
231 : B8;
232 : BB;
233 : BD;
234 : C0;
235 : C3;
236 : C6;
237 : C8;
238 : CB;
239 : CE;
240 : D1;
241 : D4;
242 : D7;
243 : DA;
244 : DD;
245 : E0;
246 : E3;
247 : E6;
248 : E9;
249 : EC;
250 : EF;
251 : F2;
252 : F5;
253 : F8;
254 : FB;
255 : FE;
END;

53
Top/.gitignore vendored
View File

@ -1,19 +1,34 @@
*.pdf
*.rpt
*.bak
.#*
/db
/incremental_db
/output_files
/simulation
/.qsys*
# /atom_netlists
/testbenches/*.bak
/common_uart/*.bak
/build/*
!/build/*.pdf
!/build/tikz*.sty
*.pdf
*.rpt
*.bak
.#*
/db
/incremental_db
/output_files
/simulation
/.qsys*
# /atom_netlists
/greybox_tmp/
/.qsys_edit/
/synthesis/
/*output_files/
/simulation/
/obj/
/drivers/
/HAL/
/Part_test/
/.metadata/
/RemoteSystemsTempFiles/
/aldec/
/cadence/
/synopsys/
/testbenches/*.bak
/common_uart/*.bak
/build/*
!/build/*.pdf
!/build/tikz*.sty

27
Top/Semafor_hw.tcl
View File

@ -1,11 +1,11 @@
# TCL File Generated by Component Editor 18.1
# Wed Oct 19 14:12:17 MSK 2022
# Sat Dec 24 02:15:19 MSK 2022
# DO NOT MODIFY
#
# Semafor "Semafor" v1.0
# 2022.10.19.14:12:17
# sem "Semafor" v1.1
# 2022.12.24.02:15:19
#
#
@ -16,11 +16,11 @@ package require -exact qsys 16.1
#
# module Semafor
# module sem
#
set_module_property DESCRIPTION ""
set_module_property NAME Semafor
set_module_property VERSION 1.0
set_module_property NAME sem
set_module_property VERSION 1.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "User Logic"
@ -43,15 +43,24 @@ set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL dec
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
#
# parameters
#
add_parameter m INTEGER 8
set_parameter_property m DEFAULT_VALUE 8
add_parameter m INTEGER 32 ""
set_parameter_property m DEFAULT_VALUE 32
set_parameter_property m DISPLAY_NAME m
set_parameter_property m TYPE INTEGER
set_parameter_property m UNITS None
set_parameter_property m ALLOWED_RANGES -2147483648:2147483647
set_parameter_property m DESCRIPTION ""
set_parameter_property m HDL_PARAMETER true
@ -154,7 +163,7 @@ set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
set_interface_property ram_slave SVD_ADDRESS_GROUP ""
add_interface_port ram_slave ram_wr write Input 1
add_interface_port ram_slave ram_addr address Input 2
add_interface_port ram_slave ram_addr address Input 4
add_interface_port ram_slave ram_wrdata writedata Input 32
set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0

190
Top/Semafor_hw.tcl~ Normal file
View File

@ -0,0 +1,190 @@
# TCL File Generated by Component Editor 18.1
# Sat Dec 24 01:52:10 MSK 2022
# DO NOT MODIFY
#
# sem "Semafor" v1.1
# 2022.12.24.01:52:10
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module sem
#
set_module_property DESCRIPTION ""
set_module_property NAME sem
set_module_property VERSION 1.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "User Logic"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME Semafor
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL dec
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv TOP_LEVEL_FILE
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL dec
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file dec.sv SYSTEM_VERILOG PATH ../HDL/dec.sv
add_fileset_file periodram.v VERILOG PATH ../HDL/IP/periodram.v
#
# parameters
#
add_parameter m INTEGER 32 ""
set_parameter_property m DEFAULT_VALUE 32
set_parameter_property m DISPLAY_NAME m
set_parameter_property m TYPE INTEGER
set_parameter_property m UNITS None
set_parameter_property m ALLOWED_RANGES -2147483648:2147483647
set_parameter_property m DESCRIPTION ""
set_parameter_property m HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point ctl_slave
#
add_interface ctl_slave avalon end
set_interface_property ctl_slave addressUnits WORDS
set_interface_property ctl_slave associatedClock clock
set_interface_property ctl_slave associatedReset reset_n
set_interface_property ctl_slave bitsPerSymbol 8
set_interface_property ctl_slave burstOnBurstBoundariesOnly false
set_interface_property ctl_slave burstcountUnits WORDS
set_interface_property ctl_slave explicitAddressSpan 0
set_interface_property ctl_slave holdTime 0
set_interface_property ctl_slave linewrapBursts false
set_interface_property ctl_slave maximumPendingReadTransactions 0
set_interface_property ctl_slave maximumPendingWriteTransactions 0
set_interface_property ctl_slave readLatency 0
set_interface_property ctl_slave readWaitStates 0
set_interface_property ctl_slave readWaitTime 0
set_interface_property ctl_slave setupTime 0
set_interface_property ctl_slave timingUnits Cycles
set_interface_property ctl_slave writeWaitTime 0
set_interface_property ctl_slave ENABLED true
set_interface_property ctl_slave EXPORT_OF ""
set_interface_property ctl_slave PORT_NAME_MAP ""
set_interface_property ctl_slave CMSIS_SVD_VARIABLES ""
set_interface_property ctl_slave SVD_ADDRESS_GROUP ""
add_interface_port ctl_slave ctl_wr write Input 1
add_interface_port ctl_slave ctl_rd read Input 1
add_interface_port ctl_slave ctl_addr address Input 1
add_interface_port ctl_slave ctl_wrdata writedata Input 32
add_interface_port ctl_slave ctl_rddata readdata Output 32
set_interface_assignment ctl_slave embeddedsw.configuration.isFlash 0
set_interface_assignment ctl_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment ctl_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment ctl_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point reset_n
#
add_interface reset_n reset end
set_interface_property reset_n associatedClock clock
set_interface_property reset_n synchronousEdges DEASSERT
set_interface_property reset_n ENABLED true
set_interface_property reset_n EXPORT_OF ""
set_interface_property reset_n PORT_NAME_MAP ""
set_interface_property reset_n CMSIS_SVD_VARIABLES ""
set_interface_property reset_n SVD_ADDRESS_GROUP ""
add_interface_port reset_n clrn reset_n Input 1
#
# connection point ram_slave
#
add_interface ram_slave avalon end
set_interface_property ram_slave addressUnits WORDS
set_interface_property ram_slave associatedClock clock
set_interface_property ram_slave associatedReset reset_n
set_interface_property ram_slave bitsPerSymbol 8
set_interface_property ram_slave burstOnBurstBoundariesOnly false
set_interface_property ram_slave burstcountUnits WORDS
set_interface_property ram_slave explicitAddressSpan 0
set_interface_property ram_slave holdTime 0
set_interface_property ram_slave linewrapBursts false
set_interface_property ram_slave maximumPendingReadTransactions 0
set_interface_property ram_slave maximumPendingWriteTransactions 0
set_interface_property ram_slave readLatency 0
set_interface_property ram_slave readWaitTime 1
set_interface_property ram_slave setupTime 0
set_interface_property ram_slave timingUnits Cycles
set_interface_property ram_slave writeWaitTime 0
set_interface_property ram_slave ENABLED true
set_interface_property ram_slave EXPORT_OF ""
set_interface_property ram_slave PORT_NAME_MAP ""
set_interface_property ram_slave CMSIS_SVD_VARIABLES ""
set_interface_property ram_slave SVD_ADDRESS_GROUP ""
add_interface_port ram_slave ram_wr write Input 1
add_interface_port ram_slave ram_addr address Input 4
add_interface_port ram_slave ram_wrdata writedata Input 32
set_interface_assignment ram_slave embeddedsw.configuration.isFlash 0
set_interface_assignment ram_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment ram_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment ram_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point sem
#
add_interface sem conduit end
set_interface_property sem associatedClock ""
set_interface_property sem associatedReset reset_n
set_interface_property sem ENABLED true
set_interface_property sem EXPORT_OF ""
set_interface_property sem PORT_NAME_MAP ""
set_interface_property sem CMSIS_SVD_VARIABLES ""
set_interface_property sem SVD_ADDRESS_GROUP ""
add_interface_port sem train train Input 1
add_interface_port sem red red Output 1
add_interface_port sem yellow yellow Output 1
add_interface_port sem green green Output 1

119
Top/niosII.qsys
View File

@ -29,7 +29,7 @@
{
datum baseAddress
{
value = "133120";
value = "34816";
type = "String";
}
}
@ -45,7 +45,7 @@
{
datum baseAddress
{
value = "135224";
value = "36896";
type = "String";
}
}
@ -73,7 +73,47 @@
type = "String";
}
}
element sem
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element niosII
{
datum _originalDeviceFamily
{
value = "Cyclone IV E";
type = "String";
}
}
element sigdel_0
{
datum _sortIndex
{
@ -81,19 +121,11 @@
type = "int";
}
}
element sem.ctl_slave
element sigdel_0.avalon_slave
{
datum baseAddress
{
value = "135216";
type = "String";
}
}
element sem.ram_slave
{
datum baseAddress
{
value = "135200";
value = "36904";
type = "String";
}
}
@ -109,16 +141,16 @@
{
datum baseAddress
{
value = "135168";
value = "36864";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE115F29C7" />
<parameter name="device" value="EP4CE15F23C8" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="deviceSpeedGrade" value="8" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@ -135,8 +167,12 @@
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk.clk_in" type="clock" dir="end" />
<interface
name="conduit_end"
internal="sigdel_0.conduit_end"
type="conduit"
dir="end" />
<interface name="reset" internal="clk.clk_in_reset" type="reset" dir="end" />
<interface name="sem_export" internal="sem.sem" type="conduit" dir="end" />
<module name="clk" kind="clock_source" version="18.1" enabled="1">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
@ -146,8 +182,8 @@
<module name="cpu" kind="altera_nios2_gen2" version="18.1" enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="AUTO_DEVICE" value="EP4CE15F23C8" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
<parameter name="bht_ramBlockType" value="Automatic" />
<parameter name="breakOffset" value="32" />
<parameter name="breakSlave" value="None" />
@ -160,10 +196,10 @@
<parameter name="customInstSlavesSystemInfo_nios_a" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_b" value="&lt;info/&gt;" />
<parameter name="customInstSlavesSystemInfo_nios_c" value="&lt;info/&gt;" />
<parameter name="dataAddrWidth" value="18" />
<parameter name="dataAddrWidth" value="16" />
<parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
<parameter name="dataMasterHighPerformanceMapParam" value="" />
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /><slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /><slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /><slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /></address-map>]]></parameter>
<parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /><slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /><slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /></address-map>]]></parameter>
<parameter name="data_master_high_performance_paddr_base" value="0" />
<parameter name="data_master_high_performance_paddr_size" value="0" />
<parameter name="data_master_paddr_base" value="0" />
@ -201,8 +237,8 @@
<parameter name="icache_size" value="4096" />
<parameter name="icache_tagramBlockType" value="Automatic" />
<parameter name="impl" value="Tiny" />
<parameter name="instAddrWidth" value="18" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
<parameter name="instAddrWidth" value="16" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /><slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /></address-map>]]></parameter>
<parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
<parameter name="instructionMasterHighPerformanceMapParam" value="" />
<parameter name="instruction_master_high_performance_paddr_base" value="0" />
@ -360,7 +396,7 @@
<parameter name="initMemContent" value="true" />
<parameter name="initializationFileName" value="onchip_mem.hex" />
<parameter name="instanceID" value="NONE" />
<parameter name="memorySize" value="131072" />
<parameter name="memorySize" value="32768" />
<parameter name="readDuringWriteMode" value="DONT_CARE" />
<parameter name="resetrequest_enabled" value="true" />
<parameter name="simAllowMRAMContentsFile" value="false" />
@ -372,8 +408,8 @@
<parameter name="useShallowMemBlocks" value="false" />
<parameter name="writable" value="true" />
</module>
<module name="sem" kind="Semafor" version="1.0" enabled="1">
<parameter name="m" value="8" />
<module name="sigdel_0" kind="sigdel" version="1.0" enabled="1">
<parameter name="PHACC_WIDTH" value="26" />
</module>
<module
name="sys_clk_timer"
@ -397,16 +433,16 @@
start="cpu.data_master"
end="jtag_uart.avalon_jtag_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021038" />
<parameter name="baseAddress" value="0x9020" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="18.1"
start="cpu.data_master"
end="sem.ctl_slave">
end="sigdel_0.avalon_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021030" />
<parameter name="baseAddress" value="0x9028" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -415,16 +451,7 @@
start="cpu.data_master"
end="cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00020800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="18.1"
start="cpu.data_master"
end="sem.ram_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021020" />
<parameter name="baseAddress" value="0x8800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -433,7 +460,7 @@
start="cpu.data_master"
end="sys_clk_timer.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00021000" />
<parameter name="baseAddress" value="0x9000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection kind="avalon" version="18.1" start="cpu.data_master" end="mem.s2">
@ -447,7 +474,7 @@
start="cpu.instruction_master"
end="cpu.debug_mem_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00020800" />
<parameter name="baseAddress" value="0x8800" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
@ -463,7 +490,7 @@
<connection kind="clock" version="18.1" start="clk.clk" end="jtag_uart.clk" />
<connection kind="clock" version="18.1" start="clk.clk" end="sys_clk_timer.clk" />
<connection kind="clock" version="18.1" start="clk.clk" end="mem.clk1" />
<connection kind="clock" version="18.1" start="clk.clk" end="sem.clock" />
<connection kind="clock" version="18.1" start="clk.clk" end="sigdel_0.clock" />
<connection
kind="interrupt"
version="18.1"
@ -486,7 +513,11 @@
start="clk.clk_reset"
end="sys_clk_timer.reset" />
<connection kind="reset" version="18.1" start="clk.clk_reset" end="mem.reset1" />
<connection kind="reset" version="18.1" start="clk.clk_reset" end="sem.reset_n" />
<connection
kind="reset"
version="18.1"
start="clk.clk_reset"
end="sigdel_0.reset_sink" />
<connection
kind="reset"
version="18.1"
@ -511,7 +542,7 @@
kind="reset"
version="18.1"
start="cpu.debug_reset_request"
end="sem.reset_n" />
end="sigdel_0.reset_sink" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />

686
Top/niosII.sopcinfo
View File

File diff suppressed because it is too large Load Diff

88
Top/niosII/niosII.bsf
View File

@ -20,75 +20,51 @@ refer to the applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 288 232)
(text "niosII" (rect 130 -1 150 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 216 20 228)(font "Arial" ))
(rect 0 0 496 184)
(text "niosII" (rect 234 -1 254 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 20 180)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8)))
(text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 112 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 112 112)(line_width 1))
(line (pt 0 72)(pt 192 72)(line_width 1))
)
(port
(pt 0 152)
(input)
(text "sem_export_train" (rect 0 0 70 12)(font "Arial" (font_size 8)))
(text "sem_export_train" (rect 4 141 100 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 112 152)(line_width 1))
(text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8)))
(text "reset_reset_n" (rect 4 141 82 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 192 152)(line_width 1))
)
(port
(pt 0 168)
(pt 0 112)
(output)
(text "sem_export_red" (rect 0 0 67 12)(font "Arial" (font_size 8)))
(text "sem_export_red" (rect 4 157 88 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 112 168)(line_width 1))
)
(port
(pt 0 184)
(output)
(text "sem_export_yellow" (rect 0 0 77 12)(font "Arial" (font_size 8)))
(text "sem_export_yellow" (rect 4 173 106 184)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 112 184)(line_width 1))
)
(port
(pt 0 200)
(output)
(text "sem_export_green" (rect 0 0 76 12)(font "Arial" (font_size 8)))
(text "sem_export_green" (rect 4 189 100 200)(font "Arial" (font_size 8)))
(line (pt 0 200)(pt 112 200)(line_width 1))
(text "conduit_end_writeresponsevalid_n" (rect 0 0 135 12)(font "Arial" (font_size 8)))
(text "conduit_end_writeresponsevalid_n" (rect 4 101 196 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 192 112)(line_width 1))
)
(drawing
(text "clk" (rect 97 43 212 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 117 67 252 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 83 83 196 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 117 107 276 224)(font "Arial" (color 0 0 0)))
(text "sem_export" (rect 44 123 148 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "train" (rect 117 147 264 304)(font "Arial" (color 0 0 0)))
(text "red" (rect 117 163 252 336)(font "Arial" (color 0 0 0)))
(text "yellow" (rect 117 179 270 368)(font "Arial" (color 0 0 0)))
(text "green" (rect 117 195 264 400)(font "Arial" (color 0 0 0)))
(text " niosII " (rect 262 216 572 442)(font "Arial" ))
(line (pt 112 32)(pt 176 32)(line_width 1))
(line (pt 176 32)(pt 176 216)(line_width 1))
(line (pt 112 216)(pt 176 216)(line_width 1))
(line (pt 112 32)(pt 112 216)(line_width 1))
(line (pt 113 52)(pt 113 76)(line_width 1))
(line (pt 114 52)(pt 114 76)(line_width 1))
(line (pt 113 92)(pt 113 116)(line_width 1))
(line (pt 114 92)(pt 114 116)(line_width 1))
(line (pt 113 132)(pt 113 204)(line_width 1))
(line (pt 114 132)(pt 114 204)(line_width 1))
(line (pt 0 0)(pt 288 0)(line_width 1))
(line (pt 288 0)(pt 288 232)(line_width 1))
(line (pt 0 232)(pt 288 232)(line_width 1))
(line (pt 0 0)(pt 0 232)(line_width 1))
(text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 197 67 412 144)(font "Arial" (color 0 0 0)))
(text "conduit_end" (rect 123 83 312 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "writeresponsevalid_n" (rect 197 107 514 224)(font "Arial" (color 0 0 0)))
(text "reset" (rect 163 123 356 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset_n" (rect 197 147 436 304)(font "Arial" (color 0 0 0)))
(text " niosII " (rect 470 168 988 346)(font "Arial" ))
(line (pt 192 32)(pt 304 32)(line_width 1))
(line (pt 304 32)(pt 304 168)(line_width 1))
(line (pt 192 168)(pt 304 168)(line_width 1))
(line (pt 192 32)(pt 192 168)(line_width 1))
(line (pt 193 52)(pt 193 76)(line_width 1))
(line (pt 194 52)(pt 194 76)(line_width 1))
(line (pt 193 92)(pt 193 116)(line_width 1))
(line (pt 194 92)(pt 194 116)(line_width 1))
(line (pt 193 132)(pt 193 156)(line_width 1))
(line (pt 194 132)(pt 194 156)(line_width 1))
(line (pt 0 0)(pt 496 0)(line_width 1))
(line (pt 496 0)(pt 496 184)(line_width 1))
(line (pt 0 184)(pt 496 184)(line_width 1))
(line (pt 0 0)(pt 0 184)(line_width 1))
)
)

9
Top/niosII/niosII.cmp
View File

@ -1,11 +1,8 @@
component niosII is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sem_export_train : in std_logic := 'X'; -- train
sem_export_red : out std_logic; -- red
sem_export_yellow : out std_logic; -- yellow
sem_export_green : out std_logic -- green
clk_clk : in std_logic := 'X'; -- clk
conduit_end_writeresponsevalid_n : out std_logic; -- writeresponsevalid_n
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosII;

101
Top/niosII/niosII.html
View File

@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2022.10.19.14:20:53</td>
<td class="l">2023.02.07.17:03:00</td>
<td class="r">Datasheet</td>
</tr>
</table>
@ -100,8 +100,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a href="#module_mem"><b>mem</b>
</a> altera_avalon_onchip_memory2 18.1
<br/>&#160;&#160;
<a href="#module_sem"><b>sem</b>
</a> Semafor 1.0
<a href="#module_sigdel_0"><b>sigdel_0</b>
</a> sigdel 1.0
<br/>&#160;&#160;
<a href="#module_sys_clk_timer"><b>sys_clk_timer</b>
</a> altera_avalon_timer 18.1</span>
@ -131,8 +131,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="slaveb">debug_mem_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00020800</td>
<td class="addr"><span style="color:#989898">0x</span>00020800</td>
<td class="addr"><span style="color:#989898">0x</span>00008800</td>
<td class="addr"><span style="color:#989898">0x</span>00008800</td>
</tr>
<tr>
<td class="slavemodule">&#160;
@ -144,7 +144,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="slaveb">avalon_jtag_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021038</td>
<td class="addr"><span style="color:#989898">0x</span>00009020</td>
<td class="empty"></td>
</tr>
<tr>
@ -167,20 +167,15 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="slavemodule">&#160;
<a href="#module_sem"><b>sem</b>
<a href="#module_sigdel_0"><b>sigdel_0</b>
</a>
</td>
<td class="empty"></td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavem">ctl_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021030</td>
<td class="empty"></td>
</tr>
<tr>
<td class="slavem">ram_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021020</td>
<td class="slaveb">avalon_slave&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00009028</td>
<td class="empty"></td>
</tr>
<tr>
@ -193,7 +188,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="slaveb">s1&#160;</td>
<td class="addr"><span style="color:#989898">0x</span>00021000</td>
<td class="addr"><span style="color:#989898">0x</span>00009000</td>
<td class="empty"></td>
</tr>
</table>
@ -256,7 +251,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<a href="#module_clk">clk</a>
</td>
<td class="from">clk&#160;&#160;</td>
<td class="main" rowspan="31">cpu</td>
<td class="main" rowspan="29">cpu</td>
</tr>
<tr>
<td class="to">&#160;&#160;clk</td>
@ -307,24 +302,14 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
<td class="neighbor" rowspan="6">
<a href="#module_sem">sem</a>
<td class="neighbor" rowspan="4">
<a href="#module_sigdel_0">sigdel_0</a>
</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;ctl_slave</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="from">data_master&#160;&#160;</td>
</tr>
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;ram_slave</td>
<td class="to">&#160;&#160;avalon_slave</td>
</tr>
<tr>
<td></td>
@ -334,7 +319,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<tr>
<td></td>
<td></td>
<td class="to">&#160;&#160;reset_n</td>
<td class="to">&#160;&#160;reset_sink</td>
</tr>
<tr style="height:6px">
<td></td>
@ -991,7 +976,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">breakAbsoluteAddr</td>
<td class="parametervalue">133152</td>
<td class="parametervalue">34848</td>
</tr>
<tr>
<td class="parametername">mmu_TLBMissExcAbsAddr</td>
@ -1047,7 +1032,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">instAddrWidth</td>
<td class="parametervalue">18</td>
<td class="parametervalue">16</td>
</tr>
<tr>
<td class="parametername">faAddrWidth</td>
@ -1055,7 +1040,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">dataAddrWidth</td>
<td class="parametervalue">18</td>
<td class="parametervalue">16</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0AddrWidth</td>
@ -1099,7 +1084,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">instSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s1' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s1' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s1' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;/address-map&gt;</td>
</tr>
<tr>
<td class="parametername">faSlaveMapParam</td>
@ -1107,7 +1092,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">dataSlaveMapParam</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x20000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x20800' end='0x21000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x21000' end='0x21020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='sem.ram_slave' start='0x21020' end='0x21030' type='Semafor.ram_slave' /&gt;&lt;slave name='sem.ctl_slave' start='0x21030' end='0x21038' type='Semafor.ctl_slave' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x21038' end='0x21040' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;/address-map&gt;</td>
<td class="parametervalue">&lt;address-map&gt;&lt;slave name='mem.s2' start='0x0' end='0x8000' type='altera_avalon_onchip_memory2.s2' /&gt;&lt;slave name='cpu.debug_mem_slave' start='0x8800' end='0x9000' type='altera_nios2_gen2.debug_mem_slave' /&gt;&lt;slave name='sys_clk_timer.s1' start='0x9000' end='0x9020' type='altera_avalon_timer.s1' /&gt;&lt;slave name='jtag_uart.avalon_jtag_slave' start='0x9020' end='0x9028' type='altera_avalon_jtag_uart.avalon_jtag_slave' /&gt;&lt;slave name='sigdel_0.avalon_slave' start='0x9028' end='0x902C' type='sigdel.avalon_slave' /&gt;&lt;/address-map&gt;</td>
</tr>
<tr>
<td class="parametername">tightlyCoupledDataMaster0MapParam</td>
@ -1183,11 +1168,11 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">AUTO_DEVICE</td>
<td class="parametervalue">EP4CE115F29C7</td>
<td class="parametervalue">EP4CE15F23C8</td>
</tr>
<tr>
<td class="parametername">AUTO_DEVICE_SPEEDGRADE</td>
<td class="parametervalue">7</td>
<td class="parametervalue">8</td>
</tr>
<tr>
<td class="parametername">AUTO_CLK_CLOCK_DOMAIN</td>
@ -1220,7 +1205,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">BREAK_ADDR</td>
<td class="parametervalue">0x00020820</td>
<td class="parametervalue">0x00008820</td>
</tr>
<tr>
<td class="parametername">CPU_ARCH_NIOS2_R1</td>
@ -1244,7 +1229,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">DATA_ADDR_WIDTH</td>
<td class="parametervalue">18</td>
<td class="parametervalue">16</td>
</tr>
<tr>
<td class="parametername">DCACHE_LINE_SIZE</td>
@ -1316,7 +1301,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">INST_ADDR_WIDTH</td>
<td class="parametervalue">18</td>
<td class="parametervalue">16</td>
</tr>
<tr>
<td class="parametername">OCI_VERSION</td>
@ -1591,7 +1576,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">memorySize</td>
<td class="parametervalue">131072</td>
<td class="parametervalue">32768</td>
</tr>
<tr>
<td class="parametername">readDuringWriteMode</td>
@ -1659,11 +1644,11 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">derived_set_addr_width</td>
<td class="parametervalue">15</td>
<td class="parametervalue">13</td>
</tr>
<tr>
<td class="parametername">derived_set_addr_width2</td>
<td class="parametervalue">15</td>
<td class="parametervalue">13</td>
</tr>
<tr>
<td class="parametername">derived_set_data_width</td>
@ -1752,7 +1737,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">SIZE_VALUE</td>
<td class="parametervalue">131072</td>
<td class="parametervalue">32768</td>
</tr>
<tr>
<td class="parametername">WRITABLE</td>
@ -1763,34 +1748,28 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
</table>
</div>
<a name="module_sem"> </a>
<a name="module_sigdel_0"> </a>
<div>
<hr/>
<h2>sem</h2>Semafor v1.0
<h2>sigdel_0</h2>sigdel v1.0
<br/>
<div class="greydiv">
<table class="connectionboxes">
<tr>
<td class="neighbor" rowspan="6">
<td class="neighbor" rowspan="4">
<a href="#module_cpu">cpu</a>
</td>
<td class="from">data_master&#160;&#160;</td>
<td class="main" rowspan="11">sem</td>
<td class="main" rowspan="9">sigdel_0</td>
</tr>
<tr>
<td class="to">&#160;&#160;ctl_slave</td>
</tr>
<tr>
<td class="from">data_master&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;ram_slave</td>
<td class="to">&#160;&#160;avalon_slave</td>
</tr>
<tr>
<td class="from">debug_reset_request&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset_n</td>
<td class="to">&#160;&#160;reset_sink</td>
</tr>
<tr style="height:6px">
<td></td>
@ -1808,7 +1787,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<td class="from">clk_reset&#160;&#160;</td>
</tr>
<tr>
<td class="to">&#160;&#160;reset_n</td>
<td class="to">&#160;&#160;reset_sink</td>
</tr>
</table>
</div>
@ -1820,8 +1799,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
<h2>Parameters</h2>
<table>
<tr>
<td class="parametername">m</td>
<td class="parametervalue">8</td>
<td class="parametername">PHACC_WIDTH</td>
<td class="parametervalue">26</td>
</tr>
<tr>
<td class="parametername">deviceFamily</td>
@ -2038,8 +2017,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0,01 seconds</td>
<td class="r">rendering took 0,11 seconds</td>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.03 seconds</td>
</tr>
</table>
</body>

1508
Top/niosII/niosII.xml
View File

File diff suppressed because one or more lines are too long

12
Top/niosII/niosII_bb.v
View File

@ -1,16 +1,10 @@
module niosII (
clk_clk,
reset_reset_n,
sem_export_train,
sem_export_red,
sem_export_yellow,
sem_export_green);
conduit_end_writeresponsevalid_n,
reset_reset_n);
input clk_clk;
output conduit_end_writeresponsevalid_n;
input reset_reset_n;
input sem_export_train;
output sem_export_red;
output sem_export_yellow;
output sem_export_green;
endmodule

9
Top/niosII/niosII_inst.v
View File

@ -1,9 +1,6 @@
niosII u0 (
.clk_clk (<connected-to-clk_clk>), // clk.clk
.reset_reset_n (<connected-to-reset_reset_n>), // reset.reset_n
.sem_export_train (<connected-to-sem_export_train>), // sem_export.train
.sem_export_red (<connected-to-sem_export_red>), // .red
.sem_export_yellow (<connected-to-sem_export_yellow>), // .yellow
.sem_export_green (<connected-to-sem_export_green>) // .green
.clk_clk (<connected-to-clk_clk>), // clk.clk
.conduit_end_writeresponsevalid_n (<connected-to-conduit_end_writeresponsevalid_n>), // conduit_end.writeresponsevalid_n
.reset_reset_n (<connected-to-reset_reset_n>) // reset.reset_n
);

18
Top/niosII/niosII_inst.vhd
View File

@ -1,21 +1,15 @@
component niosII is
port (
clk_clk : in std_logic := 'X'; -- clk
reset_reset_n : in std_logic := 'X'; -- reset_n
sem_export_train : in std_logic := 'X'; -- train
sem_export_red : out std_logic; -- red
sem_export_yellow : out std_logic; -- yellow
sem_export_green : out std_logic -- green
clk_clk : in std_logic := 'X'; -- clk
conduit_end_writeresponsevalid_n : out std_logic; -- writeresponsevalid_n
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosII;
u0 : component niosII
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
sem_export_train => CONNECTED_TO_sem_export_train, -- sem_export.train
sem_export_red => CONNECTED_TO_sem_export_red, -- .red
sem_export_yellow => CONNECTED_TO_sem_export_yellow, -- .yellow
sem_export_green => CONNECTED_TO_sem_export_green -- .green
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
conduit_end_writeresponsevalid_n => CONNECTED_TO_conduit_end_writeresponsevalid_n, -- conduit_end.writeresponsevalid_n
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);

1038
Top/niosII/synthesis/niosII.debuginfo
View File

File diff suppressed because one or more lines are too long

445
Top/niosII/synthesis/niosII.qip
View File

File diff suppressed because one or more lines are too long

2
Top/niosII/synthesis/niosII.regmap
View File

@ -1,4 +1,4 @@
<?xml version="1.0"?>
<?xml version="1.0" encoding="UTF-8"?>
<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
<name>niosII</name>
<peripherals>

64
Top/niosII/synthesis/niosII.v
View File

@ -4,25 +4,22 @@
`timescale 1 ps / 1 ps
module niosII (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
input wire sem_export_train, // sem_export.train
output wire sem_export_red, // .red
output wire sem_export_yellow, // .yellow
output wire sem_export_green // .green
input wire clk_clk, // clk.clk
output wire conduit_end_writeresponsevalid_n, // conduit_end.writeresponsevalid_n
input wire reset_reset_n // reset.reset_n
);
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire cpu_data_master_debugaccess; // cpu:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [17:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire [15:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [17:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire [15:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
@ -31,11 +28,8 @@ module niosII (
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_0_sem_ctl_slave_readdata; // sem:ctl_rddata -> mm_interconnect_0:sem_ctl_slave_readdata
wire [0:0] mm_interconnect_0_sem_ctl_slave_address; // mm_interconnect_0:sem_ctl_slave_address -> sem:ctl_addr
wire mm_interconnect_0_sem_ctl_slave_read; // mm_interconnect_0:sem_ctl_slave_read -> sem:ctl_rd
wire mm_interconnect_0_sem_ctl_slave_write; // mm_interconnect_0:sem_ctl_slave_write -> sem:ctl_wr
wire [31:0] mm_interconnect_0_sem_ctl_slave_writedata; // mm_interconnect_0:sem_ctl_slave_writedata -> sem:ctl_wrdata
wire mm_interconnect_0_sigdel_0_avalon_slave_write; // mm_interconnect_0:sigdel_0_avalon_slave_write -> sigdel_0:wr_n
wire [31:0] mm_interconnect_0_sigdel_0_avalon_slave_writedata; // mm_interconnect_0:sigdel_0_avalon_slave_writedata -> sigdel_0:wr_data
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_readdata; // cpu:debug_mem_slave_readdata -> mm_interconnect_0:cpu_debug_mem_slave_readdata
wire mm_interconnect_0_cpu_debug_mem_slave_waitrequest; // cpu:debug_mem_slave_waitrequest -> mm_interconnect_0:cpu_debug_mem_slave_waitrequest
wire mm_interconnect_0_cpu_debug_mem_slave_debugaccess; // mm_interconnect_0:cpu_debug_mem_slave_debugaccess -> cpu:debug_mem_slave_debugaccess
@ -44,9 +38,6 @@ module niosII (
wire [3:0] mm_interconnect_0_cpu_debug_mem_slave_byteenable; // mm_interconnect_0:cpu_debug_mem_slave_byteenable -> cpu:debug_mem_slave_byteenable
wire mm_interconnect_0_cpu_debug_mem_slave_write; // mm_interconnect_0:cpu_debug_mem_slave_write -> cpu:debug_mem_slave_write
wire [31:0] mm_interconnect_0_cpu_debug_mem_slave_writedata; // mm_interconnect_0:cpu_debug_mem_slave_writedata -> cpu:debug_mem_slave_writedata
wire [1:0] mm_interconnect_0_sem_ram_slave_address; // mm_interconnect_0:sem_ram_slave_address -> sem:ram_addr
wire mm_interconnect_0_sem_ram_slave_write; // mm_interconnect_0:sem_ram_slave_write -> sem:ram_wr
wire [31:0] mm_interconnect_0_sem_ram_slave_writedata; // mm_interconnect_0:sem_ram_slave_writedata -> sem:ram_wrdata
wire mm_interconnect_0_sys_clk_timer_s1_chipselect; // mm_interconnect_0:sys_clk_timer_s1_chipselect -> sys_clk_timer:chipselect
wire [15:0] mm_interconnect_0_sys_clk_timer_s1_readdata; // sys_clk_timer:readdata -> mm_interconnect_0:sys_clk_timer_s1_readdata
wire [2:0] mm_interconnect_0_sys_clk_timer_s1_address; // mm_interconnect_0:sys_clk_timer_s1_address -> sys_clk_timer:address
@ -54,14 +45,14 @@ module niosII (
wire [15:0] mm_interconnect_0_sys_clk_timer_s1_writedata; // mm_interconnect_0:sys_clk_timer_s1_writedata -> sys_clk_timer:writedata
wire mm_interconnect_0_mem_s2_chipselect; // mm_interconnect_0:mem_s2_chipselect -> mem:chipselect2
wire [31:0] mm_interconnect_0_mem_s2_readdata; // mem:readdata2 -> mm_interconnect_0:mem_s2_readdata
wire [14:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2
wire [12:0] mm_interconnect_0_mem_s2_address; // mm_interconnect_0:mem_s2_address -> mem:address2
wire [3:0] mm_interconnect_0_mem_s2_byteenable; // mm_interconnect_0:mem_s2_byteenable -> mem:byteenable2
wire mm_interconnect_0_mem_s2_write; // mm_interconnect_0:mem_s2_write -> mem:write2
wire [31:0] mm_interconnect_0_mem_s2_writedata; // mm_interconnect_0:mem_s2_writedata -> mem:writedata2
wire mm_interconnect_0_mem_s2_clken; // mm_interconnect_0:mem_s2_clken -> mem:clken2
wire mm_interconnect_0_mem_s1_chipselect; // mm_interconnect_0:mem_s1_chipselect -> mem:chipselect
wire [31:0] mm_interconnect_0_mem_s1_readdata; // mem:readdata -> mm_interconnect_0:mem_s1_readdata
wire [14:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address
wire [12:0] mm_interconnect_0_mem_s1_address; // mm_interconnect_0:mem_s1_address -> mem:address
wire [3:0] mm_interconnect_0_mem_s1_byteenable; // mm_interconnect_0:mem_s1_byteenable -> mem:byteenable
wire mm_interconnect_0_mem_s1_write; // mm_interconnect_0:mem_s1_write -> mem:write
wire [31:0] mm_interconnect_0_mem_s1_writedata; // mm_interconnect_0:mem_s1_writedata -> mem:writedata
@ -69,7 +60,7 @@ module niosII (
wire irq_mapper_receiver0_irq; // sys_clk_timer:irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq
wire [31:0] cpu_irq_irq; // irq_mapper:sender_irq -> cpu:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sem:clrn, sys_clk_timer:reset_n]
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [cpu:reset_n, irq_mapper:reset, jtag_uart:rst_n, mem:reset, mm_interconnect_0:cpu_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sigdel_0:clr_n, sys_clk_timer:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [cpu:reset_req, mem:reset_req, rst_translator:reset_req_in]
wire cpu_debug_reset_request_reset; // cpu:debug_reset_request -> rst_controller:reset_in1
@ -136,23 +127,14 @@ module niosII (
.freeze (1'b0) // (terminated)
);
dec #(
.m (8)
) sem (
.clk (clk_clk), // clock.clk
.ctl_wr (mm_interconnect_0_sem_ctl_slave_write), // ctl_slave.write
.ctl_rd (mm_interconnect_0_sem_ctl_slave_read), // .read
.ctl_addr (mm_interconnect_0_sem_ctl_slave_address), // .address
.ctl_wrdata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
.ctl_rddata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
.clrn (~rst_controller_reset_out_reset), // reset_n.reset_n
.ram_wr (mm_interconnect_0_sem_ram_slave_write), // ram_slave.write
.ram_addr (mm_interconnect_0_sem_ram_slave_address), // .address
.ram_wrdata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
.train (sem_export_train), // sem.train
.red (sem_export_red), // .red
.yellow (sem_export_yellow), // .yellow
.green (sem_export_green) // .green
sigdel #(
.PHACC_WIDTH (26)
) sigdel_0 (
.clk (clk_clk), // clock.clk
.clr_n (~rst_controller_reset_out_reset), // reset_sink.reset_n
.fout (conduit_end_writeresponsevalid_n), // conduit_end.writeresponsevalid_n
.wr_n (~mm_interconnect_0_sigdel_0_avalon_slave_write), // avalon_slave.write_n
.wr_data (mm_interconnect_0_sigdel_0_avalon_slave_writedata) // .writedata
);
niosII_sys_clk_timer sys_clk_timer (
@ -210,14 +192,8 @@ module niosII (
.mem_s2_byteenable (mm_interconnect_0_mem_s2_byteenable), // .byteenable
.mem_s2_chipselect (mm_interconnect_0_mem_s2_chipselect), // .chipselect
.mem_s2_clken (mm_interconnect_0_mem_s2_clken), // .clken
.sem_ctl_slave_address (mm_interconnect_0_sem_ctl_slave_address), // sem_ctl_slave.address
.sem_ctl_slave_write (mm_interconnect_0_sem_ctl_slave_write), // .write
.sem_ctl_slave_read (mm_interconnect_0_sem_ctl_slave_read), // .read
.sem_ctl_slave_readdata (mm_interconnect_0_sem_ctl_slave_readdata), // .readdata
.sem_ctl_slave_writedata (mm_interconnect_0_sem_ctl_slave_writedata), // .writedata
.sem_ram_slave_address (mm_interconnect_0_sem_ram_slave_address), // sem_ram_slave.address
.sem_ram_slave_write (mm_interconnect_0_sem_ram_slave_write), // .write
.sem_ram_slave_writedata (mm_interconnect_0_sem_ram_slave_writedata), // .writedata
.sigdel_0_avalon_slave_write (mm_interconnect_0_sigdel_0_avalon_slave_write), // sigdel_0_avalon_slave.write
.sigdel_0_avalon_slave_writedata (mm_interconnect_0_sigdel_0_avalon_slave_writedata), // .writedata
.sys_clk_timer_s1_address (mm_interconnect_0_sys_clk_timer_s1_address), // sys_clk_timer_s1.address
.sys_clk_timer_s1_write (mm_interconnect_0_sys_clk_timer_s1_write), // .write
.sys_clk_timer_s1_readdata (mm_interconnect_0_sys_clk_timer_s1_readdata), // .readdata

271
Top/niosII/synthesis/submodules/dec.sv
View File

@ -1,132 +1,155 @@
module dec
#(m = 8)
(
//clock and reset
input logic clk, clrn,
//control slave
input logic ctl_wr, ctl_rd,
input logic ctl_addr,
input logic [31:0] ctl_wrdata,
output logic [31:0] ctl_rddata,
//memory slave
input logic ram_wr,
input logic [1:0] ram_addr,
input logic [31:0] ram_wrdata,
//external ports
input logic train,
output logic red, yellow, green
);
logic run;
logic [1:0] divider;
logic [m-1:0] divisor;
logic [1:0] contr;
logic [2:0] colors;
logic [m-1:0] cntdiv;
logic enacnt;
#(m = 32)
(
//clock and reset
input logic clk, clrn,
//control slave
input logic ctl_wr, ctl_rd,
input logic ctl_addr,
input logic [31:0] ctl_wrdata,
output logic [31:0] ctl_rddata,
//memory slave
input logic ram_wr,
input logic [3:0] ram_addr,
input logic [31:0] ram_wrdata,
//external ports
input logic train,
output logic red, yellow, green
);
//control slave logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
run <= 0;
divider <= 0;
end
else
begin
if (ctl_wr)
begin
case (ctl_addr)
1'b0: run <= ctl_wrdata[0];
1'b1: divider <= ctl_wrdata[1:0];
endcase
end
end
end
always_comb
begin
case (ctl_addr)
1'b0: ctl_rddata = {31'b0,run};
1'b1: ctl_rddata = {30'b0,divider};
default: ctl_rddata = 'bx;
endcase
end
//semaphore logic
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn) cntdiv<=0;
else
begin
if (train | ~run) cntdiv<=0;
else
begin
if (enacnt) cntdiv<=0;
else cntdiv<=cntdiv+1;
end
end
end
always_comb
begin
enacnt=(cntdiv==divisor);
end
always_ff @ (posedge clk or negedge clrn)
begin
if (!clrn)
begin
colors <= 3'b100;
end
else
begin
if (train | ~run)
begin
colors <= 3'b100;
end
else
begin
if (enacnt)
begin
case (colors)
3'b100: colors <= 3'b010;
3'b010: colors <= 3'b011;
3'b011: colors <= 3'b001;
3'b001: colors <= 3'b001;
default: colors <= 3'b100;
endcase
end
end
end
end
always_comb
begin
case (colors)
3'b100: contr = 2'b00;
3'b010: contr = 2'b01;
3'b011: contr = 2'b10;
3'b001: contr = 2'b11;
default : contr = 2'b00;
typedef enum logic [1:0] {RED, YELLOW, BLINK, GREEN} FSMStates;
logic run;
logic [1:0] divider;
logic [1:0] state;
logic [31:0] greenSaved;
logic [31:0] greenCount;
logic [m-1:0] divisor;
logic [1:0] contr;
logic [2:0] colors;
logic [m-1:0] cntdiv;
logic enacnt;
//control slave logic
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn) begin
run <= 0;
divider <= 0;
end else begin
if (ctl_wr) begin
case (ctl_addr)
1'b0: run <= ctl_wrdata[0];
1'b1: divider <= ctl_wrdata[1:0];
endcase
end
end
end
always_comb begin
case (ctl_addr)
1'b0: ctl_rddata = {31'b0,run};
1'b1: ctl_rddata = {30'b0,divider};
default: ctl_rddata = 'bx;
endcase
end
assign red = colors[2];
assign yellow = colors[1];
assign green = colors[0];
periodram b2v_inst3(
.clock(clk),
.data (ram_wrdata),
.wraddress (ram_addr),
.wren (ram_wr),
.rdaddress({divider,contr}),
.q(divisor)
);
//semaphore logic
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn)
cntdiv <= 0;
else begin
if (train | ~run)
cntdiv<=0;
else begin
if (enacnt) cntdiv<=0;
else cntdiv<=cntdiv+1;
end
end
end
// we don't enable counters, if color is green
always_comb begin
enacnt = ((cntdiv == divisor) && !(colors == 3'b001));
end
always_ff @ (posedge clk or negedge clrn) begin
if (!clrn) begin
colors <= 3'b001;
state <= GREEN;
greenCount <= 32'd0;
end else begin
if (~run) begin
colors <= 3'b001;
state <= GREEN;
end
if (train) begin
colors <= 3'b100;
state <= RED;
greenSaved <= divisor;
greenCount <= divisor;
end else begin
case (state)
RED: begin
colors <= 3'b100;
if (enacnt) begin
state <= YELLOW;
greenSaved <= divisor;
end
end
YELLOW: begin
colors <= 3'b010;
if (enacnt) begin
state <= BLINK;
end
end
BLINK: begin
if (enacnt) begin
state <= GREEN;
end
if (greenSaved[0] == 0) begin
colors <= 3'b011;
end else begin
greenCount <= greenCount - 1'b1;
if (greenCount == 32'd0) begin
colors[1] <= ~colors[1];
greenCount <= greenSaved;
end
end
end
GREEN: begin
colors <= 3'b001;
end
default: colors <= 3'b100;
endcase
end
end
end
assign contr = state;
// always_comb begin
// case (state)
// 2'b00: contr = 2'b00;
// 2'b01: contr = 2'b01;
// 2'b10: contr = 2'b10;
// 2'b11: contr = 2'b11;
// default : contr = 2'b00;
// endcase
// end
assign red = colors[2];
assign yellow = colors[1];
assign green = colors[0];
periodram b2v_inst3
(
.clock(clk),
.data (ram_wrdata),
.wraddress (ram_addr),
.wren (ram_wr),
.rdaddress({divider,contr}),
.q(divisor)
);
endmodule

4
Top/niosII/synthesis/submodules/niosII_cpu.v
View File

@ -10,7 +10,7 @@ module niosII_cpu (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [17:0] d_address, // data_master.address
output wire [15:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
@ -18,7 +18,7 @@ module niosII_cpu (
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [17:0] i_address, // instruction_master.address
output wire [15:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest

2
Top/niosII/synthesis/submodules/niosII_cpu_cpu.sdc
View File

@ -1,4 +1,4 @@
# Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
# Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
# use of Altera Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any
# output files any of the foregoing (including device programming or

58
Top/niosII/synthesis/submodules/niosII_cpu_cpu.v
View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
@ -617,7 +617,7 @@ module niosII_cpu_cpu_nios2_oci_xbrk (
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 15: 0] F_pc;
input [ 13: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
@ -635,7 +635,7 @@ reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 17: 0] cpu_i_address;
wire [ 15: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
@ -821,7 +821,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
)
;
output [ 17: 0] cpu_d_address;
output [ 15: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
@ -837,7 +837,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 17: 0] d_address;
input [ 15: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
@ -845,7 +845,7 @@ module niosII_cpu_cpu_nios2_oci_dbrk (
input reset_n;
wire [ 17: 0] cpu_d_address;
wire [ 15: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
@ -1201,7 +1201,7 @@ module niosII_cpu_cpu_nios2_oci_dtrace (
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 17: 0] cpu_d_address;
input [ 15: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
@ -2339,7 +2339,7 @@ defparam niosII_cpu_cpu_ociram_sp_ram.lpm_file = "niosII_cpu_cpu_ociram_default_
`endif
//synthesis translate_on
assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00000020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001212 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001010 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
@ -2403,12 +2403,12 @@ module niosII_cpu_cpu_nios2_oci (
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 15: 0] F_pc;
input [ 13: 0] F_pc;
input [ 8: 0] address_nxt;
input [ 31: 0] av_ld_data_aligned_filtered;
input [ 3: 0] byteenable_nxt;
input clk;
input [ 17: 0] d_address;
input [ 15: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
@ -2427,7 +2427,7 @@ reg [ 8: 0] address;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
reg [ 3: 0] byteenable;
wire [ 17: 0] cpu_d_address;
wire [ 15: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
@ -2864,7 +2864,7 @@ module niosII_cpu_cpu (
)
;
output [ 17: 0] d_address;
output [ 15: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
@ -2874,7 +2874,7 @@ module niosII_cpu_cpu (
output debug_mem_slave_waitrequest;
output debug_reset_request;
output dummy_ci_port;
output [ 17: 0] i_address;
output [ 15: 0] i_address;
output i_read;
input clk;
input [ 31: 0] d_readdata;
@ -2959,7 +2959,7 @@ wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 15: 0] D_jmp_direct_target_waddr;
wire [ 13: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
@ -3110,7 +3110,7 @@ wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 17: 0] E_mem_baddr;
wire [ 15: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
wire E_rf_ecc_recoverable_valid;
@ -3301,15 +3301,15 @@ wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 15: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
reg [ 13: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 15: 0] F_pc_no_crst_nxt;
wire [ 15: 0] F_pc_nxt;
wire [ 15: 0] F_pc_plus_one;
wire [ 13: 0] F_pc_no_crst_nxt;
wire [ 13: 0] F_pc_nxt;
wire [ 13: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 17: 0] F_pcb;
wire [ 17: 0] F_pcb_nxt;
wire [ 17: 0] F_pcb_plus_four;
wire [ 15: 0] F_pcb;
wire [ 15: 0] F_pcb_nxt;
wire [ 15: 0] F_pcb_plus_four;
wire F_valid;
wire [ 71: 0] F_vinst;
reg [ 1: 0] R_compare_op;
@ -3443,7 +3443,7 @@ reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 17: 0] W_mem_baddr;
wire [ 15: 0] W_mem_baddr;
reg W_rf_ecc_recoverable_valid;
reg W_rf_ecc_unrecoverable_valid;
wire W_rf_ecc_valid_any;
@ -3483,7 +3483,7 @@ wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 17: 0] d_address;
wire [ 15: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
@ -3501,7 +3501,7 @@ reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 17: 0] i_address;
wire [ 15: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
@ -3863,8 +3863,8 @@ reg wait_for_one_post_bret_inst;
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 8 :
(F_pc_sel_nxt == 2'b01)? 33288 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[17 : 2] :
(F_pc_sel_nxt == 2'b01)? 8712 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[15 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
@ -4166,7 +4166,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[17 : 0];
assign E_mem_baddr = E_arith_result[15 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
@ -4489,7 +4489,7 @@ defparam niosII_cpu_cpu_register_bank_b.lpm_file = "niosII_cpu_cpu_rf_ram_b.hex"
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result);
assign W_mem_baddr = W_alu_result[17 : 0];
assign W_mem_baddr = W_alu_result[15 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 5'd0);

2
Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_sysclk.v
View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or

2
Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_tck.v
View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or

2
Top/niosII/synthesis/submodules/niosII_cpu_cpu_debug_slave_wrapper.v
View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or

512
Top/niosII/synthesis/submodules/niosII_cpu_cpu_ociram_default_contents.mif
View File

@ -7,261 +7,261 @@ DATA_RADIX=HEX;
CONTENT BEGIN
00 : 88997af9;
01 : abaae595;
02 : 32fd14d1;
03 : b66193c4;
04 : c6a6aa09;
05 : 0b43de5b;
06 : d1d93028;
07 : bcd08e2a;
08 : 1c8bae85;
09 : b11dad63;
0a : 864ddf62;
0b : 68301486;
0c : 51a3d8d0;
0d : 7af7d39e;
0e : 4761b503;
0f : 2a976e14;
10 : 98141041;
11 : 4c1f6471;
12 : 41dc0a35;
13 : 7d484ae3;
14 : 2a1329f3;
15 : 44ecf499;
16 : dccdd125;
17 : 240142e9;
18 : 3b7e4b05;
19 : bb92e762;
1a : 4594a3c5;
1b : ea0d940f;
1c : 66525d7c;
1d : 0f552242;
1e : 452bd52d;
1f : d1f4ed11;
20 : 5d590422;
21 : c8016b5f;
22 : 9ab94f07;
23 : 16bac9b4;
24 : fe569ae3;
25 : c6e1e6e7;
26 : 2ff19932;
27 : feb058ad;
28 : 1dcce651;
29 : e18b9bfb;
2a : e2f4fc64;
2b : 05d34847;
2c : 077a8143;
2d : 2ce4207f;
2e : 3f3e5113;
2f : c24d2803;
30 : e289b503;
31 : d16bcd4e;
32 : 57a841cf;
33 : 1194f754;
34 : 5c925a31;
35 : 40fd6946;
36 : e397e5d7;
37 : eada7553;
38 : eba8ec01;
39 : f5b39d0b;
3a : 88af39a3;
3b : 5b7f243e;
3c : 4f2bb4ba;
3d : 9451a234;
3e : 10fd984d;
3f : ad4ef4f7;
40 : 7fe97f8b;
41 : 08ea614d;
42 : 9f2c5cf4;
43 : 3f90b7a2;
44 : 8c2bc774;
45 : 45dd63a5;
46 : 3204329c;
47 : 9909be0d;
48 : be65c97b;
49 : 78f3d4a4;
4a : 3ee8b71c;
4b : 9e9a0de4;
4c : 56db426b;
4d : e6869d81;
4e : 20ab0652;
4f : 05d247ed;
50 : 1edccf12;
51 : 1e483b5a;
52 : 8e48ef1e;
53 : f19aefbf;
54 : 98335d23;
55 : 954ac923;
56 : 4679ced6;
57 : ae18d9b8;
58 : be57db48;
59 : 2af933e3;
5a : 3f04e244;
5b : 5d11c958;
5c : 65bda8cb;
5d : c53fe664;
5e : 797ceac8;
5f : aaa406e5;
60 : f785e24e;
61 : 95510077;
62 : 5b6f55a3;
63 : 2a3c749a;
64 : a92e6ae6;
65 : b2117fb0;
66 : 262a254e;
67 : b8c4da74;
68 : f69070ee;
69 : 9e7f80b8;
6a : 834528b4;
6b : 4aaf6d98;
6c : 96023372;
6d : d11663ed;
6e : 33a3c007;
6f : 0e7f06ee;
70 : 34385787;
71 : 2edfd7b0;
72 : 00d60e4b;
73 : 49535c30;
74 : e83f5c14;
75 : 5e0c4c59;
76 : 1d7b944a;
77 : 6ae69731;
78 : bf8414e4;
79 : 7451c212;
7a : 74ede6d2;
7b : 080eafa5;
7c : f21052d8;
7d : cc0819fb;
7e : 8993e5b6;
7f : e20f2df6;
80 : 0f267a65;
81 : 7a8e8407;
82 : e7be656d;
83 : 01ba4ca3;
84 : 7f998e44;
85 : 29d83420;
86 : 149f9a73;
87 : 643ae51e;
88 : 125714d3;
89 : 6e49dc21;
8a : 0b227946;
8b : 360a837d;
8c : b2187074;
8d : 17b0bdbd;
8e : 938fc73d;
8f : e73f501e;
90 : 70b5b87e;
91 : 2a2aed8a;
92 : f96cc881;
93 : 021b49e1;
94 : 8691600d;
95 : b45e1d12;
96 : 64d9644e;
97 : 486cbaf9;
98 : 386acf20;
99 : 0d1384d4;
9a : 62455f77;
9b : 866fde20;
9c : 006fecec;
9d : 94e84514;
9e : 7babc333;
9f : afaa8445;
a0 : b1175e3a;
a1 : e08de629;
a2 : 7f12a52d;
a3 : 0e322909;
a4 : 18784dc6;
a5 : b23bcc20;
a6 : 266c9e34;
a7 : c857eaf3;
a8 : 2ae3b164;
a9 : 038acf2a;
aa : c1abc60d;
ab : 8af787bd;
ac : 043723a9;
ad : c37c952d;
ae : 693a361f;
af : da4b8e99;
b0 : fb8fdb10;
b1 : 4d6365f2;
b2 : 712358e9;
b3 : 85dae0fa;
b4 : 7e82a418;
b5 : d3493768;
b6 : 739c65ec;
b7 : 73b66b19;
b8 : 22142816;
b9 : ff498322;
ba : 3266495e;
bb : e26e8214;
bc : c8c47131;
bd : 660793d8;
be : 689f8d69;
bf : faae340b;
c0 : 37518ba7;
c1 : f2865fe5;
c2 : 1bb44f3d;
c3 : 3bce44c5;
c4 : aff2d188;
c5 : 985442da;
c6 : 85bb58bd;
c7 : 0c53135d;
c8 : 495f80bc;
c9 : 853c95dc;
ca : dde937f1;
cb : 418f9452;
cc : 7669641c;
cd : 0e752434;
ce : b0fe17a7;
cf : d1be9b88;
d0 : cfbfeb76;
d1 : 80b48a11;
d2 : 9327c69e;
d3 : beca5a88;
d4 : e71d428f;
d5 : b318d275;
d6 : 56fea35e;
d7 : 140cd6bd;
d8 : b8c937ce;
d9 : 540eea36;
da : ee58fc7f;
db : 5615c389;
dc : 46692ad0;
dd : 5c713e51;
de : 6ba95f60;
df : 0e166732;
e0 : ac0e49f5;
e1 : c9a5ea76;
e2 : 05b04d86;
e3 : b29ac712;
e4 : 4e344493;
e5 : d45ede48;
e6 : 3da7e426;
e7 : 4d6a8937;
e8 : 99b59bd4;
e9 : 1f8a5751;
ea : 8b07e64e;
eb : b4dcd496;
ec : 42f84fe6;
ed : f1d5952f;
ee : a2e5a42d;
ef : 15b1af16;
f0 : 168012bc;
f1 : 2e276612;
f2 : 89913eaa;
f3 : c607a1a2;
f4 : fd8b544d;
f5 : aec31a53;
f6 : 25f958ad;
f7 : 365903ec;
f8 : 14761865;
f9 : 568cc23b;
fa : b0386305;
fb : fb9ebd8a;
fc : a25911d4;
fd : 806e3fbb;
fe : 9df35264;
ff : d62b3814;
00 : 5870e850;
01 : c7a32b0d;
02 : 6f82d8fd;
03 : 40bb3819;
04 : 03c0b473;
05 : 8f16cf30;
06 : d708360b;
07 : 880f36dc;
08 : d1a275f0;
09 : 5944e053;
0a : c1313a53;
0b : 4cb0c559;
0c : 528cd209;
0d : 1ed6d1c2;
0e : 3fe378c9;
0f : aa1b9ac8;
10 : 31d374f0;
11 : be61ec44;
12 : 2c7a1043;
13 : 2641125e;
14 : 0c46e1e9;
15 : 9860f4c3;
16 : d9980c45;
17 : 85005ae5;
18 : b156d9cb;
19 : 8a5321c3;
1a : b603ed2b;
1b : 2a1eb3a0;
1c : f4b7b88b;
1d : a1ce694f;
1e : 469d3811;
1f : 2185240b;
20 : a745eb3e;
21 : 3d2ce9c9;
22 : e4f87c64;
23 : 4e473b66;
24 : f25af5e6;
25 : 5bf0ba5c;
26 : d9f793ee;
27 : a5410324;
28 : 298d0d25;
29 : e60402c3;
2a : 97132679;
2b : bcd9897b;
2c : 82a038f5;
2d : 201cbf45;
2e : fe6ce958;
2f : c368dfdf;
30 : 6a3f8ef7;
31 : 83368a01;
32 : 65976a6a;
33 : 821cfabf;
34 : 20bdc8df;
35 : 60d97952;
36 : 73819628;
37 : 674070d1;
38 : fc155d79;
39 : d3a408b1;
3a : bfdf2c88;
3b : 22a2fce0;
3c : 01e7c505;
3d : e3e78ba0;
3e : a049e343;
3f : c0f1b055;
40 : 877e1ef1;
41 : ca871fa5;
42 : 25ab3e85;
43 : f9f4b822;
44 : 90aad39a;
45 : 08f5e44c;
46 : 39d12cce;
47 : 80f2ed6f;
48 : 6a29b7d6;
49 : 8b913cf5;
4a : 63815e88;
4b : 3b598e73;
4c : 73bfa5d4;
4d : 77c09ce3;
4e : 839a407b;
4f : 6433730b;
50 : 44284f24;
51 : f5d5762e;
52 : b65d636d;
53 : d1c786b8;
54 : f3c8d2f5;
55 : 356dc558;
56 : 591772eb;
57 : 79e0fdb4;
58 : e8932f59;
59 : 259d108a;
5a : bb57a7f8;
5b : 4825e3bc;
5c : 52cf4522;
5d : 79e4316b;
5e : 8c0d6004;
5f : a754e118;
60 : 4e281ca2;
61 : fbbc819a;
62 : 4aee7640;
63 : 7d333e63;
64 : b15aaa9c;
65 : 4f43ec26;
66 : 1ec71c75;
67 : 8836d7ff;
68 : 03bf3159;
69 : 64fe92e3;
6a : 967a0361;
6b : 52d392c1;
6c : ed91cb89;
6d : 576cc97b;
6e : 6b3ffb6a;
6f : 35d248a1;
70 : f9045e40;
71 : 67ec2a14;
72 : c6a8d3b4;
73 : 215bfb86;
74 : c69c1f66;
75 : 4244d56d;
76 : 1b3928f3;
77 : 731a2236;
78 : 38d78b27;
79 : 059c9248;
7a : 5f87a44a;
7b : aba5ed2e;
7c : c0524059;
7d : 980abb72;
7e : 7437c9f5;
7f : 7eceac74;
80 : e459de2d;
81 : 70371382;
82 : 9e5c9169;
83 : e019ec71;
84 : 8a8a254a;
85 : 5d6b1e75;
86 : b69a1826;
87 : 1895f4fa;
88 : f357cacf;
89 : d52486ab;
8a : 1e598442;
8b : d8d4c72d;
8c : f8973f5f;
8d : 7df07844;
8e : 603c0386;
8f : 5fa48cd0;
90 : 7dad0b4e;
91 : d8063146;
92 : dd06b1d5;
93 : a42cea93;
94 : 937d88ca;
95 : 0c6e9a23;
96 : b81bdfa3;
97 : 28077cf0;
98 : 9aab97aa;
99 : b6597e34;
9a : 436fcd2b;
9b : be8fe3e1;
9c : dae80c2f;
9d : e95b81e6;
9e : 767f7b1b;
9f : 23d2190d;
a0 : dbd13b92;
a1 : ba04bced;
a2 : c59ab4a9;
a3 : d18cd97a;
a4 : fdc9eef9;
a5 : e5d3431b;
a6 : 36145dba;
a7 : 381901fd;
a8 : 2b84a31d;
a9 : 56d3b835;
aa : 82d83a4f;
ab : 521d2b9a;
ac : 0224591a;
ad : 80d7ea50;
ae : 49815eac;
af : 9c8177e2;
b0 : d83c171d;
b1 : 82d4e894;
b2 : 2da7a2cf;
b3 : ae082f05;
b4 : ea847ea7;
b5 : c53a36ee;
b6 : 9044fe8d;
b7 : dadb18f9;
b8 : 3631522b;
b9 : 2bae3746;
ba : 02d78d99;
bb : 8e0e2771;
bc : 2ed189db;
bd : 63aa82eb;
be : 754229af;
bf : a11062b5;
c0 : e28618e1;
c1 : fcaf3400;
c2 : c8a7faac;
c3 : be56d9b0;
c4 : 7c3f3063;
c5 : 4d331f3f;
c6 : 8cceb16d;
c7 : 2d352b5d;
c8 : 0db6cd22;
c9 : 745ff58e;
ca : e450c6d2;
cb : 5567ae51;
cc : ec2ac609;
cd : fcced128;
ce : 193f8e92;
cf : 5719a6cc;
d0 : 065cddb6;
d1 : 04f4e1f9;
d2 : a95d8a1e;
d3 : d516bf8e;
d4 : e30d671e;
d5 : ebeeb2fe;
d6 : b48fdd0f;
d7 : f4b75c46;
d8 : 4d9c9650;
d9 : f2df58d8;
da : 67ace373;
db : 7ccace3c;
dc : f4f3f5d5;
dd : 2be9f598;
de : f7889908;
df : f67c2f07;
e0 : 880a8491;
e1 : 9c3967d0;
e2 : d89b44d2;
e3 : 7c21987c;
e4 : 495e0377;
e5 : 1c88706d;
e6 : bf0b4325;
e7 : 79fcc944;
e8 : fd8c1d81;
e9 : f4f168ae;
ea : cf67e751;
eb : 75907b16;
ec : d859c7c1;
ed : 05ef2e02;
ee : 1f5802c9;
ef : 8cb4928b;
f0 : 19e65b5f;
f1 : 9c3b7bab;
f2 : 22bc8d7d;
f3 : 03aa0e5f;
f4 : 7d35f4ff;
f5 : e5208a6e;
f6 : 44fdd477;
f7 : 74a81f1c;
f8 : 6936d4f1;
f9 : 375fc2a2;
fa : 22a07f26;
fb : 701c1a4d;
fc : af4d2557;
fd : bac85a82;
fe : 29cff602;
ff : 3e17ccab;
END;

8
Top/niosII/synthesis/submodules/niosII_cpu_cpu_test_bench.v
View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
@ -59,7 +59,7 @@ module niosII_cpu_cpu_test_bench (
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 17: 0] F_pcb;
input [ 15: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
@ -70,11 +70,11 @@ module niosII_cpu_cpu_test_bench (
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 17: 0] d_address;
input [ 15: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 17: 0] i_address;
input [ 15: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;

2
Top/niosII/synthesis/submodules/niosII_jtag_uart.v
View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or

24576
Top/niosII/synthesis/submodules/niosII_mem.hex
View File

File diff suppressed because it is too large Load Diff

16
Top/niosII/synthesis/submodules/niosII_mem.v
View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
@ -48,8 +48,8 @@ module niosII_mem (
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 14: 0] address;
input [ 14: 0] address2;
input [ 12: 0] address;
input [ 12: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
@ -102,9 +102,9 @@ wire wren2;
the_altsyncram.indata_reg_b = "CLOCK0",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32768,
the_altsyncram.numwords_a = 32768,
the_altsyncram.numwords_b = 32768,
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.numwords_b = 8192,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
@ -114,8 +114,8 @@ wire wren2;
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 15,
the_altsyncram.widthad_b = 15,
the_altsyncram.widthad_a = 13,
the_altsyncram.widthad_b = 13,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK0";
//s1, which is an e_avalon_slave

1613
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0.v
View File

File diff suppressed because it is too large Load Diff

47
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux.sv
View File

@ -28,9 +28,9 @@
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_demux
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// NUM_OUTPUTS: 6
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// NUM_OUTPUTS: 5
// VALID_WIDTH: 1
// ------------------------------------------
@ -46,8 +46,8 @@ module niosII_mm_interconnect_0_cmd_demux
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [94-1 : 0] sink_data, // ST_DATA_W=94
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input [92-1 : 0] sink_data, // ST_DATA_W=92
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -56,47 +56,40 @@ module niosII_mm_interconnect_0_cmd_demux
// Sources
// -------------------
output reg src0_valid,
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg [92-1 : 0] src0_data, // ST_DATA_W=92
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
output reg [92-1 : 0] src1_data, // ST_DATA_W=92
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
output reg src2_valid,
output reg [94-1 : 0] src2_data, // ST_DATA_W=94
output reg [7-1 : 0] src2_channel, // ST_CHANNEL_W=7
output reg [92-1 : 0] src2_data, // ST_DATA_W=92
output reg [6-1 : 0] src2_channel, // ST_CHANNEL_W=6
output reg src2_startofpacket,
output reg src2_endofpacket,
input src2_ready,
output reg src3_valid,
output reg [94-1 : 0] src3_data, // ST_DATA_W=94
output reg [7-1 : 0] src3_channel, // ST_CHANNEL_W=7
output reg [92-1 : 0] src3_data, // ST_DATA_W=92
output reg [6-1 : 0] src3_channel, // ST_CHANNEL_W=6
output reg src3_startofpacket,
output reg src3_endofpacket,
input src3_ready,
output reg src4_valid,
output reg [94-1 : 0] src4_data, // ST_DATA_W=94
output reg [7-1 : 0] src4_channel, // ST_CHANNEL_W=7
output reg [92-1 : 0] src4_data, // ST_DATA_W=92
output reg [6-1 : 0] src4_channel, // ST_CHANNEL_W=6
output reg src4_startofpacket,
output reg src4_endofpacket,
input src4_ready,
output reg src5_valid,
output reg [94-1 : 0] src5_data, // ST_DATA_W=94
output reg [7-1 : 0] src5_channel, // ST_CHANNEL_W=7
output reg src5_startofpacket,
output reg src5_endofpacket,
input src5_ready,
// -------------------
// Clock & Reset
@ -108,7 +101,7 @@ module niosII_mm_interconnect_0_cmd_demux
);
localparam NUM_OUTPUTS = 6;
localparam NUM_OUTPUTS = 5;
wire [NUM_OUTPUTS - 1 : 0] ready_vector;
// -------------------
@ -150,13 +143,6 @@ module niosII_mm_interconnect_0_cmd_demux
src4_valid = sink_channel[4] && sink_valid;
src5_data = sink_data;
src5_startofpacket = sink_startofpacket;
src5_endofpacket = sink_endofpacket;
src5_channel = sink_channel >> NUM_OUTPUTS;
src5_valid = sink_channel[5] && sink_valid;
end
// -------------------
@ -167,7 +153,6 @@ module niosII_mm_interconnect_0_cmd_demux
assign ready_vector[2] = src2_ready;
assign ready_vector[3] = src3_ready;
assign ready_vector[4] = src4_ready;
assign ready_vector[5] = src5_ready;
assign sink_ready = |(sink_channel & {{1{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});

18
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv
View File

@ -28,8 +28,8 @@
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_cmd_demux_001
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// NUM_OUTPUTS: 2
// VALID_WIDTH: 1
// ------------------------------------------
@ -46,8 +46,8 @@ module niosII_mm_interconnect_0_cmd_demux_001
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [94-1 : 0] sink_data, // ST_DATA_W=94
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input [92-1 : 0] sink_data, // ST_DATA_W=92
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -56,15 +56,15 @@ module niosII_mm_interconnect_0_cmd_demux_001
// Sources
// -------------------
output reg src0_valid,
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg [92-1 : 0] src0_data, // ST_DATA_W=92
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
output reg src1_valid,
output reg [94-1 : 0] src1_data, // ST_DATA_W=94
output reg [7-1 : 0] src1_channel, // ST_CHANNEL_W=7
output reg [92-1 : 0] src1_data, // ST_DATA_W=92
output reg [6-1 : 0] src1_channel, // ST_CHANNEL_W=6
output reg src1_startofpacket,
output reg src1_endofpacket,
input src1_ready,
@ -109,7 +109,7 @@ module niosII_mm_interconnect_0_cmd_demux_001
assign ready_vector[0] = src0_ready;
assign ready_vector[1] = src1_ready;
assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
assign sink_ready = |(sink_channel & {{4{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule

22
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux.sv
View File

@ -43,9 +43,9 @@
// ARBITRATION_SHARES: 1
// ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// ------------------------------------------
module niosII_mm_interconnect_0_cmd_mux
@ -54,8 +54,8 @@ module niosII_mm_interconnect_0_cmd_mux
// Sinks
// ----------------------
input sink0_valid,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
@ -65,8 +65,8 @@ module niosII_mm_interconnect_0_cmd_mux
// Source
// ----------------------
output src_valid,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output [92-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
@ -77,13 +77,13 @@ module niosII_mm_interconnect_0_cmd_mux
input clk,
input reset
);
localparam PAYLOAD_W = 94 + 7 + 2;
localparam PAYLOAD_W = 92 + 6 + 2;
localparam NUM_INPUTS = 1;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 56;
assign src_valid = sink0_valid;
assign src_data = sink0_data;

30
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv
View File

@ -43,9 +43,9 @@
// ARBITRATION_SHARES: 1 1
// ARBITRATION_SCHEME "round-robin"
// PIPELINE_ARB: 1
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// ------------------------------------------
module niosII_mm_interconnect_0_cmd_mux_002
@ -54,15 +54,15 @@ module niosII_mm_interconnect_0_cmd_mux_002
// Sinks
// ----------------------
input sink0_valid,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [94-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input [92-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
@ -72,8 +72,8 @@ module niosII_mm_interconnect_0_cmd_mux_002
// Source
// ----------------------
output src_valid,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output [92-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
@ -84,13 +84,13 @@ module niosII_mm_interconnect_0_cmd_mux_002
input clk,
input reset
);
localparam PAYLOAD_W = 94 + 7 + 2;
localparam PAYLOAD_W = 92 + 6 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 1;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 56;
// ------------------------------------------
// Signals
@ -122,8 +122,8 @@ module niosII_mm_interconnect_0_cmd_mux_002
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[58];
lock[1] = sink1_data[58];
lock[0] = sink0_data[56];
lock[1] = sink1_data[56];
end
reg [NUM_INPUTS - 1 : 0] locked = '0;
always @(posedge clk or posedge reset) begin

97
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router.sv
View File

@ -44,26 +44,26 @@
module niosII_mm_interconnect_0_router_default_decode
#(
parameter DEFAULT_CHANNEL = 5,
parameter DEFAULT_CHANNEL = 4,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 3
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
(output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
DEFAULT_DESTID[78 - 76 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
endgenerate
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_default_decode
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input [92-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 55;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@ -134,18 +134,17 @@ module niosII_mm_interconnect_0_router
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
localparam PAD2 = log2ceil(64'h21020 - 64'h21000);
localparam PAD3 = log2ceil(64'h21030 - 64'h21020);
localparam PAD4 = log2ceil(64'h21038 - 64'h21030);
localparam PAD5 = log2ceil(64'h21040 - 64'h21038);
localparam PAD0 = log2ceil(64'h8000 - 64'h0);
localparam PAD1 = log2ceil(64'h9000 - 64'h8800);
localparam PAD2 = log2ceil(64'h9020 - 64'h9000);
localparam PAD3 = log2ceil(64'h9028 - 64'h9020);
localparam PAD4 = log2ceil(64'h902c - 64'h9028);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h21040;
localparam ADDR_RANGE = 64'h902c;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
@ -169,7 +168,7 @@ module niosII_mm_interconnect_0_router
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [7-1 : 0] default_src_channel;
wire [6-1 : 0] default_src_channel;
@ -198,40 +197,34 @@ module niosII_mm_interconnect_0_router
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x20000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
src_channel = 7'b100000;
// ( 0x0 .. 0x8000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 16'h0 ) begin
src_channel = 6'b10000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 3;
end
// ( 0x20800 .. 0x21000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
src_channel = 7'b000100;
// ( 0x8800 .. 0x9000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 16'h8800 ) begin
src_channel = 6'b00100;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end
// ( 0x21000 .. 0x21020 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 18'h21000 ) begin
src_channel = 7'b010000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 6;
end
// ( 0x21020 .. 0x21030 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 18'h21020 && write_transaction ) begin
src_channel = 7'b001000;
// ( 0x9000 .. 0x9020 )
if ( {address[RG:PAD2],{PAD2{1'b0}}} == 16'h9000 ) begin
src_channel = 6'b01000;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 5;
end
// ( 0x21030 .. 0x21038 )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 18'h21030 ) begin
src_channel = 7'b000010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
// ( 0x9020 .. 0x9028 )
if ( {address[RG:PAD3],{PAD3{1'b0}}} == 16'h9020 ) begin
src_channel = 6'b00001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
end
// ( 0x21038 .. 0x21040 )
if ( {address[RG:PAD5],{PAD5{1'b0}}} == 18'h21038 ) begin
src_channel = 7'b000001;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 1;
// ( 0x9028 .. 0x902c )
if ( {address[RG:PAD4],{PAD4{1'b0}}} == 16'h9028 && write_transaction ) begin
src_channel = 6'b00010;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 4;
end
end

60
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_001.sv
View File

@ -49,21 +49,21 @@ module niosII_mm_interconnect_0_router_001_default_decode
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 2
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
(output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
DEFAULT_DESTID[78 - 76 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
endgenerate
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_001_default_decode
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_001
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input [92-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router_001
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_001
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 0;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 55;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@ -134,14 +134,14 @@ module niosII_mm_interconnect_0_router_001
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h20000 - 64'h0);
localparam PAD1 = log2ceil(64'h21000 - 64'h20800);
localparam PAD0 = log2ceil(64'h8000 - 64'h0);
localparam PAD1 = log2ceil(64'h9000 - 64'h8800);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h21000;
localparam ADDR_RANGE = 64'h9000;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
@ -165,7 +165,7 @@ module niosII_mm_interconnect_0_router_001
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [PKT_DEST_ID_W-1:0] default_destid;
wire [7-1 : 0] default_src_channel;
wire [6-1 : 0] default_src_channel;
@ -189,15 +189,15 @@ module niosII_mm_interconnect_0_router_001
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x20000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 18'h0 ) begin
src_channel = 7'b10;
// ( 0x0 .. 0x8000 )
if ( {address[RG:PAD0],{PAD0{1'b0}}} == 16'h0 ) begin
src_channel = 6'b10;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 2;
end
// ( 0x20800 .. 0x21000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 18'h20800 ) begin
src_channel = 7'b01;
// ( 0x8800 .. 0x9000 )
if ( {address[RG:PAD1],{PAD1{1'b0}}} == 16'h8800 ) begin
src_channel = 6'b01;
src_data[PKT_DEST_ID_H:PKT_DEST_ID_L] = 0;
end

44
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_002.sv
View File

@ -49,21 +49,21 @@ module niosII_mm_interconnect_0_router_002_default_decode
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
(output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
DEFAULT_DESTID[78 - 76 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
endgenerate
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_002_default_decode
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_002
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input [92-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router_002
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_002
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 55;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@ -158,7 +158,7 @@ module niosII_mm_interconnect_0_router_002
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_src_channel;
wire [6-1 : 0] default_src_channel;
@ -185,7 +185,7 @@ module niosII_mm_interconnect_0_router_002
if (destid == 0 ) begin
src_channel = 7'b1;
src_channel = 6'b1;
end

46
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_004.sv
View File

@ -49,21 +49,21 @@ module niosII_mm_interconnect_0_router_004_default_decode
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 0
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
(output [78 - 76 : 0] default_destination_id,
output [6-1 : 0] default_wr_channel,
output [6-1 : 0] default_rd_channel,
output [6-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
DEFAULT_DESTID[78 - 76 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
assign default_src_channel = 6'b1 << DEFAULT_CHANNEL;
end
endgenerate
@ -73,8 +73,8 @@ module niosII_mm_interconnect_0_router_004_default_decode
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
assign default_wr_channel = 6'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 6'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
@ -93,7 +93,7 @@ module niosII_mm_interconnect_0_router_004
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input [92-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -102,8 +102,8 @@ module niosII_mm_interconnect_0_router_004
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output reg [92-1 : 0] src_data,
output reg [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
@ -112,18 +112,18 @@ module niosII_mm_interconnect_0_router_004
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_H = 51;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_DEST_ID_H = 78;
localparam PKT_DEST_ID_L = 76;
localparam PKT_PROTECTION_H = 82;
localparam PKT_PROTECTION_L = 80;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_TRANS_WRITE = 54;
localparam PKT_TRANS_READ = 55;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
@ -158,7 +158,7 @@ module niosII_mm_interconnect_0_router_004
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_src_channel;
wire [6-1 : 0] default_src_channel;
@ -190,11 +190,11 @@ module niosII_mm_interconnect_0_router_004
if (destid == 0 ) begin
src_channel = 7'b01;
src_channel = 6'b01;
end
if (destid == 1 && read_transaction) begin
src_channel = 7'b10;
src_channel = 6'b10;
end

440
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_router_008.sv
View File

@ -1,220 +1,220 @@
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// either (a) the address or (b) the dest id. The DECODER_TYPE
// parameter controls this behaviour. 0 means address decoder,
// 1 means dest id decoder.
//
// In the case of (a), it also sets the destination id.
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module niosII_mm_interconnect_0_router_008_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 1
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module niosII_mm_interconnect_0_router_008
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
niosII_mm_interconnect_0_router_008_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 1 && read_transaction) begin
src_channel = 7'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/18.1std/ip/merlin/altera_merlin_router/altera_merlin_router.sv.terp#1 $
// $Revision: #1 $
// $Date: 2018/07/18 $
// $Author: psgswbuild $
// -------------------------------------------------------
// Merlin Router
//
// Asserts the appropriate one-hot encoded channel based on
// either (a) the address or (b) the dest id. The DECODER_TYPE
// parameter controls this behaviour. 0 means address decoder,
// 1 means dest id decoder.
//
// In the case of (a), it also sets the destination id.
// -------------------------------------------------------
`timescale 1 ns / 1 ns
module niosII_mm_interconnect_0_router_008_default_decode
#(
parameter DEFAULT_CHANNEL = 0,
DEFAULT_WR_CHANNEL = -1,
DEFAULT_RD_CHANNEL = -1,
DEFAULT_DESTID = 1
)
(output [80 - 78 : 0] default_destination_id,
output [7-1 : 0] default_wr_channel,
output [7-1 : 0] default_rd_channel,
output [7-1 : 0] default_src_channel
);
assign default_destination_id =
DEFAULT_DESTID[80 - 78 : 0];
generate
if (DEFAULT_CHANNEL == -1) begin : no_default_channel_assignment
assign default_src_channel = '0;
end
else begin : default_channel_assignment
assign default_src_channel = 7'b1 << DEFAULT_CHANNEL;
end
endgenerate
generate
if (DEFAULT_RD_CHANNEL == -1) begin : no_default_rw_channel_assignment
assign default_wr_channel = '0;
assign default_rd_channel = '0;
end
else begin : default_rw_channel_assignment
assign default_wr_channel = 7'b1 << DEFAULT_WR_CHANNEL;
assign default_rd_channel = 7'b1 << DEFAULT_RD_CHANNEL;
end
endgenerate
endmodule
module niosII_mm_interconnect_0_router_008
(
// -------------------
// Clock & Reset
// -------------------
input clk,
input reset,
// -------------------
// Command Sink (Input)
// -------------------
input sink_valid,
input [94-1 : 0] sink_data,
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
// -------------------
// Command Source (Output)
// -------------------
output src_valid,
output reg [94-1 : 0] src_data,
output reg [7-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready
);
// -------------------------------------------------------
// Local parameters and variables
// -------------------------------------------------------
localparam PKT_ADDR_H = 53;
localparam PKT_ADDR_L = 36;
localparam PKT_DEST_ID_H = 80;
localparam PKT_DEST_ID_L = 78;
localparam PKT_PROTECTION_H = 84;
localparam PKT_PROTECTION_L = 82;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam DECODER_TYPE = 1;
localparam PKT_TRANS_WRITE = 56;
localparam PKT_TRANS_READ = 57;
localparam PKT_ADDR_W = PKT_ADDR_H-PKT_ADDR_L + 1;
localparam PKT_DEST_ID_W = PKT_DEST_ID_H-PKT_DEST_ID_L + 1;
// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h0;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg [PKT_DEST_ID_W-1 : 0] destid;
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire [7-1 : 0] default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data[PKT_TRANS_READ];
niosII_mm_interconnect_0_router_008_default_decode the_default_decode(
.default_destination_id (),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
// --------------------------------------------------
// DestinationID Decoder
// Sets the channel based on the destination ID.
// --------------------------------------------------
destid = sink_data[PKT_DEST_ID_H : PKT_DEST_ID_L];
if (destid == 1 && read_transaction) begin
src_channel = 7'b1;
end
end
// --------------------------------------------------
// Ceil(log2()) function
// --------------------------------------------------
function integer log2ceil;
input reg[65:0] val;
reg [65:0] i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule

14
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_demux.sv
View File

@ -28,8 +28,8 @@
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_rsp_demux
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// NUM_OUTPUTS: 1
// VALID_WIDTH: 1
// ------------------------------------------
@ -46,8 +46,8 @@ module niosII_mm_interconnect_0_rsp_demux
// Sink
// -------------------
input [1-1 : 0] sink_valid,
input [94-1 : 0] sink_data, // ST_DATA_W=94
input [7-1 : 0] sink_channel, // ST_CHANNEL_W=7
input [92-1 : 0] sink_data, // ST_DATA_W=92
input [6-1 : 0] sink_channel, // ST_CHANNEL_W=6
input sink_startofpacket,
input sink_endofpacket,
output sink_ready,
@ -56,8 +56,8 @@ module niosII_mm_interconnect_0_rsp_demux
// Sources
// -------------------
output reg src0_valid,
output reg [94-1 : 0] src0_data, // ST_DATA_W=94
output reg [7-1 : 0] src0_channel, // ST_CHANNEL_W=7
output reg [92-1 : 0] src0_data, // ST_DATA_W=92
output reg [6-1 : 0] src0_channel, // ST_CHANNEL_W=6
output reg src0_startofpacket,
output reg src0_endofpacket,
input src0_ready,
@ -94,7 +94,7 @@ module niosII_mm_interconnect_0_rsp_demux
// -------------------
assign ready_vector[0] = src0_ready;
assign sink_ready = |(sink_channel & {{6{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
assign sink_ready = |(sink_channel & {{5{1'b0}},{ready_vector[NUM_OUTPUTS - 1 : 0]}});
endmodule

78
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux.sv
View File

@ -39,13 +39,13 @@
// ------------------------------------------
// Generation parameters:
// output_name: niosII_mm_interconnect_0_rsp_mux
// NUM_INPUTS: 6
// ARBITRATION_SHARES: 1 1 1 1 1 1
// NUM_INPUTS: 5
// ARBITRATION_SHARES: 1 1 1 1 1
// ARBITRATION_SCHEME "no-arb"
// PIPELINE_ARB: 0
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// ------------------------------------------
module niosII_mm_interconnect_0_rsp_mux
@ -54,54 +54,47 @@ module niosII_mm_interconnect_0_rsp_mux
// Sinks
// ----------------------
input sink0_valid,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [94-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input [92-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
input sink2_valid,
input [94-1 : 0] sink2_data,
input [7-1: 0] sink2_channel,
input [92-1 : 0] sink2_data,
input [6-1: 0] sink2_channel,
input sink2_startofpacket,
input sink2_endofpacket,
output sink2_ready,
input sink3_valid,
input [94-1 : 0] sink3_data,
input [7-1: 0] sink3_channel,
input [92-1 : 0] sink3_data,
input [6-1: 0] sink3_channel,
input sink3_startofpacket,
input sink3_endofpacket,
output sink3_ready,
input sink4_valid,
input [94-1 : 0] sink4_data,
input [7-1: 0] sink4_channel,
input [92-1 : 0] sink4_data,
input [6-1: 0] sink4_channel,
input sink4_startofpacket,
input sink4_endofpacket,
output sink4_ready,
input sink5_valid,
input [94-1 : 0] sink5_data,
input [7-1: 0] sink5_channel,
input sink5_startofpacket,
input sink5_endofpacket,
output sink5_ready,
// ----------------------
// Source
// ----------------------
output src_valid,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output [92-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
@ -112,13 +105,13 @@ module niosII_mm_interconnect_0_rsp_mux
input clk,
input reset
);
localparam PAYLOAD_W = 94 + 7 + 2;
localparam NUM_INPUTS = 6;
localparam PAYLOAD_W = 92 + 6 + 2;
localparam NUM_INPUTS = 5;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 56;
// ------------------------------------------
// Signals
@ -138,14 +131,12 @@ module niosII_mm_interconnect_0_rsp_mux
wire [PAYLOAD_W - 1 : 0] sink2_payload;
wire [PAYLOAD_W - 1 : 0] sink3_payload;
wire [PAYLOAD_W - 1 : 0] sink4_payload;
wire [PAYLOAD_W - 1 : 0] sink5_payload;
assign valid[0] = sink0_valid;
assign valid[1] = sink1_valid;
assign valid[2] = sink2_valid;
assign valid[3] = sink3_valid;
assign valid[4] = sink4_valid;
assign valid[5] = sink5_valid;
// ------------------------------------------
@ -155,12 +146,11 @@ module niosII_mm_interconnect_0_rsp_mux
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[58];
lock[1] = sink1_data[58];
lock[2] = sink2_data[58];
lock[3] = sink3_data[58];
lock[4] = sink4_data[58];
lock[5] = sink5_data[58];
lock[0] = sink0_data[56];
lock[1] = sink1_data[56];
lock[2] = sink2_data[56];
lock[3] = sink3_data[56];
lock[4] = sink4_data[56];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));
@ -196,13 +186,11 @@ module niosII_mm_interconnect_0_rsp_mux
// 2 | 1 | 0
// 3 | 1 | 0
// 4 | 1 | 0
// 5 | 1 | 0
wire [SHARE_COUNTER_W - 1 : 0] share_0 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_1 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_2 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_3 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_4 = 1'd0;
wire [SHARE_COUNTER_W - 1 : 0] share_5 = 1'd0;
// ------------------------------------------
// Choose the share value corresponding to the grant.
@ -214,8 +202,7 @@ module niosII_mm_interconnect_0_rsp_mux
share_1 & { SHARE_COUNTER_W {next_grant[1]} } |
share_2 & { SHARE_COUNTER_W {next_grant[2]} } |
share_3 & { SHARE_COUNTER_W {next_grant[3]} } |
share_4 & { SHARE_COUNTER_W {next_grant[4]} } |
share_5 & { SHARE_COUNTER_W {next_grant[5]} };
share_4 & { SHARE_COUNTER_W {next_grant[4]} };
end
// ------------------------------------------
@ -287,14 +274,11 @@ module niosII_mm_interconnect_0_rsp_mux
wire final_packet_4 = 1'b1;
wire final_packet_5 = 1'b1;
// ------------------------------------------
// Concatenate all final_packet signals (wire or reg) into a handy vector.
// ------------------------------------------
wire [NUM_INPUTS - 1 : 0] final_packet = {
final_packet_5,
final_packet_4,
final_packet_3,
final_packet_2,
@ -388,7 +372,6 @@ module niosII_mm_interconnect_0_rsp_mux
assign sink2_ready = src_ready && grant[2];
assign sink3_ready = src_ready && grant[3];
assign sink4_ready = src_ready && grant[4];
assign sink5_ready = src_ready && grant[5];
assign src_valid = |(grant & valid);
@ -398,8 +381,7 @@ module niosII_mm_interconnect_0_rsp_mux
sink1_payload & {PAYLOAD_W {grant[1]} } |
sink2_payload & {PAYLOAD_W {grant[2]} } |
sink3_payload & {PAYLOAD_W {grant[3]} } |
sink4_payload & {PAYLOAD_W {grant[4]} } |
sink5_payload & {PAYLOAD_W {grant[5]} };
sink4_payload & {PAYLOAD_W {grant[4]} };
end
// ------------------------------------------
@ -416,8 +398,6 @@ module niosII_mm_interconnect_0_rsp_mux
sink3_startofpacket,sink3_endofpacket};
assign sink4_payload = {sink4_channel,sink4_data,
sink4_startofpacket,sink4_endofpacket};
assign sink5_payload = {sink5_channel,sink5_data,
sink5_startofpacket,sink5_endofpacket};
assign {src_channel,src_data,src_startofpacket,src_endofpacket} = src_payload;
endmodule

30
Top/niosII/synthesis/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv
View File

@ -43,9 +43,9 @@
// ARBITRATION_SHARES: 1 1
// ARBITRATION_SCHEME "no-arb"
// PIPELINE_ARB: 0
// PKT_TRANS_LOCK: 58 (arbitration locking enabled)
// ST_DATA_W: 94
// ST_CHANNEL_W: 7
// PKT_TRANS_LOCK: 56 (arbitration locking enabled)
// ST_DATA_W: 92
// ST_CHANNEL_W: 6
// ------------------------------------------
module niosII_mm_interconnect_0_rsp_mux_001
@ -54,15 +54,15 @@ module niosII_mm_interconnect_0_rsp_mux_001
// Sinks
// ----------------------
input sink0_valid,
input [94-1 : 0] sink0_data,
input [7-1: 0] sink0_channel,
input [92-1 : 0] sink0_data,
input [6-1: 0] sink0_channel,
input sink0_startofpacket,
input sink0_endofpacket,
output sink0_ready,
input sink1_valid,
input [94-1 : 0] sink1_data,
input [7-1: 0] sink1_channel,
input [92-1 : 0] sink1_data,
input [6-1: 0] sink1_channel,
input sink1_startofpacket,
input sink1_endofpacket,
output sink1_ready,
@ -72,8 +72,8 @@ module niosII_mm_interconnect_0_rsp_mux_001
// Source
// ----------------------
output src_valid,
output [94-1 : 0] src_data,
output [7-1 : 0] src_channel,
output [92-1 : 0] src_data,
output [6-1 : 0] src_channel,
output src_startofpacket,
output src_endofpacket,
input src_ready,
@ -84,13 +84,13 @@ module niosII_mm_interconnect_0_rsp_mux_001
input clk,
input reset
);
localparam PAYLOAD_W = 94 + 7 + 2;
localparam PAYLOAD_W = 92 + 6 + 2;
localparam NUM_INPUTS = 2;
localparam SHARE_COUNTER_W = 1;
localparam PIPELINE_ARB = 0;
localparam ST_DATA_W = 94;
localparam ST_CHANNEL_W = 7;
localparam PKT_TRANS_LOCK = 58;
localparam ST_DATA_W = 92;
localparam ST_CHANNEL_W = 6;
localparam PKT_TRANS_LOCK = 56;
// ------------------------------------------
// Signals
@ -119,8 +119,8 @@ module niosII_mm_interconnect_0_rsp_mux_001
// ------------------------------------------
reg [NUM_INPUTS - 1 : 0] lock;
always @* begin
lock[0] = sink0_data[58];
lock[1] = sink1_data[58];
lock[0] = sink0_data[56];
lock[1] = sink1_data[56];
end
assign last_cycle = src_valid & src_ready & src_endofpacket & ~(|(lock & grant));

2
Top/niosII/synthesis/submodules/niosII_sys_clk_timer.v
View File

@ -1,4 +1,4 @@
//Legal Notice: (C)2022 Altera Corporation. All rights reserved. Your
//Legal Notice: (C)2023 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or

436
Top/niosII/synthesis/submodules/periodram.v
View File

@ -1,214 +1,222 @@
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: periodram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.2 Build 209 09/17/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module periodram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [3:0] rdaddress;
input [1:0] wraddress;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 2,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "128"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "2"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
// Retrieval info: USED_PORT: wraddress 0 0 2 0 INPUT NODEFVAL "wraddress[1..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 2 0 wraddress 0 0 2 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: periodram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module periodram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "periodram.rif"
`else
altsyncram_component.init_file = "periodram.hex"
`endif
,
altsyncram_component.init_file_layout = "PORT_B",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "512"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "periodram.hex"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "periodram.hex"
// Retrieval info: CONSTANT: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL periodram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

376
Top/niosII/testbench/mentor/msim_setup.tcl Normal file
View File

@ -0,0 +1,376 @@
# (C) 2001-2023 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ----------------------------------------
# Auto-generated simulation script msim_setup.tcl
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# niosII_tb
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level script that compiles Altera simulation libraries and
# the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "mentor.do", and modify the text as directed.
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# set QSYS_SIMDIR <script generation output directory>
# #
# # Source the generated IP simulation script.
# source $QSYS_SIMDIR/mentor/msim_setup.tcl
# #
# # Set any compilation options you require (this is unusual).
# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
# #
# # Call command to compile the Quartus EDA simulation library.
# dev_com
# #
# # Call command to compile the Quartus-generated IP simulation files.
# com
# #
# # Add commands to compile all design files and testbench files, including
# # the top level. (These are all the files required for simulation other
# # than the files compiled by the Quartus-generated IP simulation script)
# #
# vlog <compilation options> <design and testbench files>
# #
# # Set the top-level simulation or testbench module/entity name, which is
# # used by the elab command to elaborate the top level.
# #
# set TOP_LEVEL_NAME <simulation top>
# #
# # Set any elaboration options you require.
# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
# #
# # Call command to elaborate your design and testbench.
# elab
# #
# # Run the simulation.
# run -a
# #
# # Report success to the shell.
# exit -code 0
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If niosII_tb is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 linux 2023.01.17.19:01:36
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "niosII_tb"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
}
if ![info exists USER_DEFINED_COMPILE_OPTIONS] {
set USER_DEFINED_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] {
set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] {
set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
}
if ![info exists USER_DEFINED_ELAB_OPTIONS] {
set USER_DEFINED_ELAB_OPTIONS ""
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
file copy -force $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries/
ensure_lib ./libraries/work/
vmap work ./libraries/work/
vmap work_lib ./libraries/work/
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
ensure_lib ./libraries/altera_ver/
vmap altera_ver ./libraries/altera_ver/
ensure_lib ./libraries/lpm_ver/
vmap lpm_ver ./libraries/lpm_ver/
ensure_lib ./libraries/sgate_ver/
vmap sgate_ver ./libraries/sgate_ver/
ensure_lib ./libraries/altera_mf_ver/
vmap altera_mf_ver ./libraries/altera_mf_ver/
ensure_lib ./libraries/altera_lnsim_ver/
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
ensure_lib ./libraries/cycloneive_ver/
vmap cycloneive_ver ./libraries/cycloneive_ver/
}
ensure_lib ./libraries/altera_common_sv_packages/
vmap altera_common_sv_packages ./libraries/altera_common_sv_packages/
ensure_lib ./libraries/error_adapter_0/
vmap error_adapter_0 ./libraries/error_adapter_0/
ensure_lib ./libraries/avalon_st_adapter/
vmap avalon_st_adapter ./libraries/avalon_st_adapter/
ensure_lib ./libraries/rsp_mux_001/
vmap rsp_mux_001 ./libraries/rsp_mux_001/
ensure_lib ./libraries/rsp_mux/
vmap rsp_mux ./libraries/rsp_mux/
ensure_lib ./libraries/rsp_demux/
vmap rsp_demux ./libraries/rsp_demux/
ensure_lib ./libraries/cmd_mux_002/
vmap cmd_mux_002 ./libraries/cmd_mux_002/
ensure_lib ./libraries/cmd_mux/
vmap cmd_mux ./libraries/cmd_mux/
ensure_lib ./libraries/cmd_demux_001/
vmap cmd_demux_001 ./libraries/cmd_demux_001/
ensure_lib ./libraries/cmd_demux/
vmap cmd_demux ./libraries/cmd_demux/
ensure_lib ./libraries/router_008/
vmap router_008 ./libraries/router_008/
ensure_lib ./libraries/router_004/
vmap router_004 ./libraries/router_004/
ensure_lib ./libraries/router_002/
vmap router_002 ./libraries/router_002/
ensure_lib ./libraries/router_001/
vmap router_001 ./libraries/router_001/
ensure_lib ./libraries/router/
vmap router ./libraries/router/
ensure_lib ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
vmap jtag_uart_avalon_jtag_slave_agent_rsp_fifo ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
ensure_lib ./libraries/jtag_uart_avalon_jtag_slave_agent/
vmap jtag_uart_avalon_jtag_slave_agent ./libraries/jtag_uart_avalon_jtag_slave_agent/
ensure_lib ./libraries/cpu_data_master_agent/
vmap cpu_data_master_agent ./libraries/cpu_data_master_agent/
ensure_lib ./libraries/jtag_uart_avalon_jtag_slave_translator/
vmap jtag_uart_avalon_jtag_slave_translator ./libraries/jtag_uart_avalon_jtag_slave_translator/
ensure_lib ./libraries/cpu_data_master_translator/
vmap cpu_data_master_translator ./libraries/cpu_data_master_translator/
ensure_lib ./libraries/cpu/
vmap cpu ./libraries/cpu/
ensure_lib ./libraries/rst_controller/
vmap rst_controller ./libraries/rst_controller/
ensure_lib ./libraries/irq_mapper/
vmap irq_mapper ./libraries/irq_mapper/
ensure_lib ./libraries/mm_interconnect_0/
vmap mm_interconnect_0 ./libraries/mm_interconnect_0/
ensure_lib ./libraries/sys_clk_timer/
vmap sys_clk_timer ./libraries/sys_clk_timer/
ensure_lib ./libraries/sem/
vmap sem ./libraries/sem/
ensure_lib ./libraries/mem/
vmap mem ./libraries/mem/
ensure_lib ./libraries/jtag_uart/
vmap jtag_uart ./libraries/jtag_uart/
ensure_lib ./libraries/niosII_inst_reset_bfm/
vmap niosII_inst_reset_bfm ./libraries/niosII_inst_reset_bfm/
ensure_lib ./libraries/niosII_inst_clk_bfm/
vmap niosII_inst_clk_bfm ./libraries/niosII_inst_clk_bfm/
ensure_lib ./libraries/niosII_inst/
vmap niosII_inst ./libraries/niosII_inst/
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
}
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/verbosity_pkg.sv" -work altera_common_sv_packages
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" -L altera_common_sv_packages -work error_adapter_0
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v" -work avalon_st_adapter
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv" -L altera_common_sv_packages -work rsp_mux_001
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work rsp_mux_001
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv" -L altera_common_sv_packages -work rsp_mux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work rsp_mux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv" -L altera_common_sv_packages -work rsp_demux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv" -L altera_common_sv_packages -work cmd_mux_002
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work cmd_mux_002
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv" -L altera_common_sv_packages -work cmd_mux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -L altera_common_sv_packages -work cmd_mux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv" -L altera_common_sv_packages -work cmd_demux_001
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv" -L altera_common_sv_packages -work cmd_demux
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv" -L altera_common_sv_packages -work router_008
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv" -L altera_common_sv_packages -work router_004
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv" -L altera_common_sv_packages -work router_002
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv" -L altera_common_sv_packages -work router_001
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv" -L altera_common_sv_packages -work router
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v" -work jtag_uart_avalon_jtag_slave_agent_rsp_fifo
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_agent
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_agent
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -L altera_common_sv_packages -work cpu_data_master_agent
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -L altera_common_sv_packages -work jtag_uart_avalon_jtag_slave_translator
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -L altera_common_sv_packages -work cpu_data_master_translator
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_synchronizer.v" -work rst_controller
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_irq_mapper.sv" -L altera_common_sv_packages -work irq_mapper
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v" -work mm_interconnect_0
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v" -work sys_clk_timer
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/dec.sv" -L altera_common_sv_packages -work sem
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/periodram.v" -work sem
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.v" -work mem
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_jtag_uart.v" -work jtag_uart
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu.v" -work cpu
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv" -L altera_common_sv_packages -work niosII_inst_reset_bfm
eval vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv" -L altera_common_sv_packages -work niosII_inst_clk_bfm
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII.v" -work niosII_inst
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/niosII_tb.v"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_common_sv_packages -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux -L cmd_mux_002 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L router_008 -L router_004 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L cpu_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L cpu_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L sys_clk_timer -L sem -L mem -L jtag_uart -L niosII_inst_reset_bfm -L niosII_inst_clk_bfm -L niosII_inst -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with novopt option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_common_sv_packages -L error_adapter_0 -L avalon_st_adapter -L rsp_mux_001 -L rsp_mux -L rsp_demux -L cmd_mux_002 -L cmd_mux -L cmd_demux_001 -L cmd_demux -L router_008 -L router_004 -L router_002 -L router_001 -L router -L jtag_uart_avalon_jtag_slave_agent_rsp_fifo -L jtag_uart_avalon_jtag_slave_agent -L cpu_data_master_agent -L jtag_uart_avalon_jtag_slave_translator -L cpu_data_master_translator -L cpu -L rst_controller -L irq_mapper -L mm_interconnect_0 -L sys_clk_timer -L sem -L mem -L jtag_uart -L niosII_inst_reset_bfm -L niosII_inst_clk_bfm -L niosII_inst -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -novopt
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with novopt option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo " For most designs, this should be overridden"
echo " to enable the elab/elab_debug aliases."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Platform Designer base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
echo
echo "USER_DEFINED_COMPILE_OPTIONS -- User-defined compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_ELAB_OPTIONS -- User-defined elaboration options, added to elab/elab_debug aliases."
echo
echo "USER_DEFINED_VHDL_COMPILE_OPTIONS -- User-defined vhdl compile options, added to com/dev_com aliases."
echo
echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS -- User-defined verilog compile options, added to com/dev_com aliases."
}
file_copy
h

2025
Top/niosII/testbench/niosII.html Normal file
View File

File diff suppressed because one or more lines are too long

12
Top/niosII/testbench/niosII.ipx Normal file
View File

@ -0,0 +1,12 @@
<library>
<!-- Include the system-under-test, and project-local components. -->
<path path="../../*" >
<tag2 key="COMPONENT_IN_PROJECT" value="true" />
</path>
<path path="../../ip/**/*" >
<tag2 key="COMPONENT_IN_PROJECT" value="true" />
</path>
<path path="../../*/*" >
<tag2 key="COMPONENT_IN_PROJECT" value="true" />
</path>
</library>

2346
Top/niosII/testbench/niosII_tb.html Normal file
View File

File diff suppressed because one or more lines are too long

102
Top/niosII/testbench/niosII_tb.qsys Normal file
View File

@ -0,0 +1,102 @@
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="" />
<parameter name="bonusData"><![CDATA[bonusData
{
element niosII_inst
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element niosII_inst_clk_bfm
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element niosII_inst_reset_bfm
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE115F29C7" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="hideFromIPCatalog" value="false" />
<parameter name="lockedInterfaceDefinition" value="" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="semafor.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="testBenchDutName" value="niosII" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="true" />
<instanceScript></instanceScript>
<module name="niosII_inst" kind="niosII" version="1.0" enabled="1">
<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
<parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
<parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
<parameter name="AUTO_DEVICE" value="EP4CE115F29C7" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="7" />
<parameter name="AUTO_GENERATION_ID" value="0" />
<parameter name="AUTO_UNIQUE_ID" value="niosII" />
</module>
<module
name="niosII_inst_clk_bfm"
kind="altera_avalon_clock_source"
version="18.1"
enabled="1">
<parameter name="CLOCK_RATE" value="50000000" />
<parameter name="CLOCK_UNIT" value="1" />
</module>
<module
name="niosII_inst_reset_bfm"
kind="altera_avalon_reset_source"
version="18.1"
enabled="1">
<parameter name="ASSERT_HIGH_RESET" value="0" />
<parameter name="INITIAL_RESET_CYCLES" value="50" />
</module>
<connection
kind="clock"
version="18.1"
start="niosII_inst_clk_bfm.clk"
end="niosII_inst.clk" />
<connection
kind="clock"
version="18.1"
start="niosII_inst_clk_bfm.clk"
end="niosII_inst_reset_bfm.clk" />
<connection
kind="reset"
version="18.1"
start="niosII_inst_reset_bfm.reset"
end="niosII_inst.reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>

33
Top/niosII/testbench/niosII_tb/simulation/niosII_tb.v Normal file
View File

@ -0,0 +1,33 @@
// niosII_tb.v
// Generated using ACDS version 18.1 625
`timescale 1 ps / 1 ps
module niosII_tb (
);
wire niosii_inst_clk_bfm_clk_clk; // niosII_inst_clk_bfm:clk -> [niosII_inst:clk_clk, niosII_inst_reset_bfm:clk]
wire niosii_inst_reset_bfm_reset_reset; // niosII_inst_reset_bfm:reset -> niosII_inst:reset_reset_n
niosII niosii_inst (
.clk_clk (niosii_inst_clk_bfm_clk_clk), // clk.clk
.conduit_end_writeresponsevalid_n (), // conduit_end.writeresponsevalid_n
.reset_reset_n (niosii_inst_reset_bfm_reset_reset) // reset.reset_n
);
altera_avalon_clock_source #(
.CLOCK_RATE (50000000),
.CLOCK_UNIT (1)
) niosii_inst_clk_bfm (
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
);
altera_avalon_reset_source #(
.ASSERT_HIGH_RESET (0),
.INITIAL_RESET_CYCLES (50)
) niosii_inst_reset_bfm (
.reset (niosii_inst_reset_bfm_reset_reset), // reset.reset_n
.clk (niosii_inst_clk_bfm_clk_clk) // clk.clk
);
endmodule

198
Top/niosII/testbench/synopsys/vcs/vcs_setup.sh Normal file
View File

@ -0,0 +1,198 @@
# (C) 2001-2023 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 linux 2023.01.17.19:01:36
# ----------------------------------------
# vcs - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# niosII_tb
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, follow the guidelines below.
#
# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
# below into a new file, e.g. named "vcs_sim.sh".
#
# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
# a separate file, e.g. named "filelist.f".
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
# # set the top-level simulation or testbench module/entity name.
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator.
# #
# # Source the Quartus-generated IP simulation script and do the following:
# # - Compile the Quartus EDA simulation library and IP simulation files.
# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
# # - Compile the design and top-level simulation module/entity using
# # information specified in "filelist.f".
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# # - Run the simulation.
# #
# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
# TOP_LEVEL_NAME=<simulation top> \
# QSYS_SIMDIR=<script generation output directory> \
# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# ----------------------------------------
# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the Quartus-generated IP simulation script)
# #
# +systemverilogext+.sv
# <design and testbench files, compile-time options, elaboration options>
# #
# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If niosII_tb is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 linux 2023.01.17.19:01:36
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
SKIP_FILE_COPY=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# copy RAM/ROM files to simulation directory
if [ $SKIP_FILE_COPY -eq 0 ]; then
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
fi
vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/verbosity_pkg.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_synchronizer.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_irq_mapper.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/dec.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/periodram.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_jtag_uart.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu.v \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv \
$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII.v \
$QSYS_SIMDIR/niosII_tb/simulation/niosII_tb.v \
-top $TOP_LEVEL_NAME
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi

41
Top/niosII/testbench/synopsys/vcsmx/synopsys_sim.setup Normal file
View File

@ -0,0 +1,41 @@
WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera_common_sv_packages: ./libraries/altera_common_sv_packages/
error_adapter_0: ./libraries/error_adapter_0/
avalon_st_adapter: ./libraries/avalon_st_adapter/
rsp_mux_001: ./libraries/rsp_mux_001/
rsp_mux: ./libraries/rsp_mux/
rsp_demux: ./libraries/rsp_demux/
cmd_mux_002: ./libraries/cmd_mux_002/
cmd_mux: ./libraries/cmd_mux/
cmd_demux_001: ./libraries/cmd_demux_001/
cmd_demux: ./libraries/cmd_demux/
router_008: ./libraries/router_008/
router_004: ./libraries/router_004/
router_002: ./libraries/router_002/
router_001: ./libraries/router_001/
router: ./libraries/router/
jtag_uart_avalon_jtag_slave_agent_rsp_fifo: ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
jtag_uart_avalon_jtag_slave_agent: ./libraries/jtag_uart_avalon_jtag_slave_agent/
cpu_data_master_agent: ./libraries/cpu_data_master_agent/
jtag_uart_avalon_jtag_slave_translator: ./libraries/jtag_uart_avalon_jtag_slave_translator/
cpu_data_master_translator: ./libraries/cpu_data_master_translator/
cpu: ./libraries/cpu/
rst_controller: ./libraries/rst_controller/
irq_mapper: ./libraries/irq_mapper/
mm_interconnect_0: ./libraries/mm_interconnect_0/
sys_clk_timer: ./libraries/sys_clk_timer/
sem: ./libraries/sem/
mem: ./libraries/mem/
jtag_uart: ./libraries/jtag_uart/
niosII_inst_reset_bfm: ./libraries/niosII_inst_reset_bfm/
niosII_inst_clk_bfm: ./libraries/niosII_inst_clk_bfm/
niosII_inst: ./libraries/niosII_inst/
altera_ver: ./libraries/altera_ver/
lpm_ver: ./libraries/lpm_ver/
sgate_ver: ./libraries/sgate_ver/
altera_mf_ver: ./libraries/altera_mf_ver/
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
cycloneive_ver: ./libraries/cycloneive_ver/

273
Top/niosII/testbench/synopsys/vcsmx/vcsmx_setup.sh Normal file
View File

@ -0,0 +1,273 @@
# (C) 2001-2023 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 18.1 625 linux 2023.01.17.19:01:36
# ----------------------------------------
# vcsmx - auto-generated simulation script
# ----------------------------------------
# This script provides commands to simulate the following IP detected in
# your Quartus project:
# niosII_tb
#
# Altera recommends that you source this Quartus-generated IP simulation
# script from your own customized top-level script, and avoid editing this
# generated script.
#
# To write a top-level shell script that compiles Altera simulation libraries
# and the Quartus-generated IP in your project, along with your design and
# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
#
# You can also modify the simulation flow to suit your needs. Set the
# following variables to 1 to disable their corresponding processes:
# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
# - SKIP_COM: skip compiling Quartus-generated IP simulation files
# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
#
# ----------------------------------------
# # TOP-LEVEL TEMPLATE - BEGIN
# #
# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
# # construct paths to the files required to simulate the IP in your Quartus
# # project. By default, the IP script assumes that you are launching the
# # simulator from the IP script location. If launching from another
# # location, set QSYS_SIMDIR to the output directory you specified when you
# # generated the IP script, relative to the directory from which you launch
# # the simulator. In this case, you must also copy the generated library
# # setup "synopsys_sim.setup" into the location from which you launch the
# # simulator, or incorporate into any existing library setup.
# #
# # Run Quartus-generated IP simulation script once to compile Quartus EDA
# # simulation libraries and Quartus-generated IP simulation files, and copy
# # any ROM/RAM initialization files to the simulation directory.
# #
# # - If necessary, specify any compilation options:
# # USER_DEFINED_COMPILE_OPTIONS
# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_ELAB=1 \
# SKIP_SIM=1 \
# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
# QSYS_SIMDIR=<script generation output directory>
# #
# # Compile all design files and testbench files, including the top level.
# # (These are all the files required for simulation other than the files
# # compiled by the IP script)
# #
# vlogan <compilation options> <design and testbench files>
# #
# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
# # testbench module/entity name.
# #
# # Run the IP script again to elaborate and simulate the top level:
# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
# # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
# #
# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
# SKIP_FILE_COPY=1 \
# SKIP_DEV_COM=1 \
# SKIP_COM=1 \
# TOP_LEVEL_NAME="'-top <simulation top>'" \
# QSYS_SIMDIR=<script generation output directory> \
# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
# #
# # TOP-LEVEL TEMPLATE - END
# ----------------------------------------
#
# IP SIMULATION SCRIPT
# ----------------------------------------
# If niosII_tb is one of several IP cores in your
# Quartus project, you can generate a simulation script
# suitable for inclusion in your top-level simulation
# script by running the following command line:
#
# ip-setup-simulation --quartus-project=<quartus project>
#
# ip-setup-simulation will discover the Altera IP
# within the Quartus project, and generate a unified
# script which supports all the Altera IP within the design.
# ----------------------------------------
# ACDS 18.1 625 linux 2023.01.17.19:01:36
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="niosII_tb"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="/home/ovchinnikov_ii@RISDE.ru/intelFPGA_lite/18.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera_common_sv_packages/
mkdir -p ./libraries/error_adapter_0/
mkdir -p ./libraries/avalon_st_adapter/
mkdir -p ./libraries/rsp_mux_001/
mkdir -p ./libraries/rsp_mux/
mkdir -p ./libraries/rsp_demux/
mkdir -p ./libraries/cmd_mux_002/
mkdir -p ./libraries/cmd_mux/
mkdir -p ./libraries/cmd_demux_001/
mkdir -p ./libraries/cmd_demux/
mkdir -p ./libraries/router_008/
mkdir -p ./libraries/router_004/
mkdir -p ./libraries/router_002/
mkdir -p ./libraries/router_001/
mkdir -p ./libraries/router/
mkdir -p ./libraries/jtag_uart_avalon_jtag_slave_agent_rsp_fifo/
mkdir -p ./libraries/jtag_uart_avalon_jtag_slave_agent/
mkdir -p ./libraries/cpu_data_master_agent/
mkdir -p ./libraries/jtag_uart_avalon_jtag_slave_translator/
mkdir -p ./libraries/cpu_data_master_translator/
mkdir -p ./libraries/cpu/
mkdir -p ./libraries/rst_controller/
mkdir -p ./libraries/irq_mapper/
mkdir -p ./libraries/mm_interconnect_0/
mkdir -p ./libraries/sys_clk_timer/
mkdir -p ./libraries/sem/
mkdir -p ./libraries/mem/
mkdir -p ./libraries/jtag_uart/
mkdir -p ./libraries/niosII_inst_reset_bfm/
mkdir -p ./libraries/niosII_inst_clk_bfm/
mkdir -p ./libraries/niosII_inst/
mkdir -p ./libraries/altera_ver/
mkdir -p ./libraries/lpm_ver/
mkdir -p ./libraries/sgate_ver/
mkdir -p ./libraries/altera_mf_ver/
mkdir -p ./libraries/altera_lnsim_ver/
mkdir -p ./libraries/cycloneive_ver/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
if [ $SKIP_FILE_COPY -eq 0 ]; then
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.dat ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_b.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_ociram_default_contents.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.mif ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_rf_ram_a.hex ./
cp -f $QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.hex ./
fi
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cycloneive_atoms.v" -work cycloneive_ver
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/verbosity_pkg.sv" -work altera_common_sv_packages
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" -work error_adapter_0
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_avalon_st_adapter.v" -work avalon_st_adapter
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux_001.sv" -work rsp_mux_001
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -work rsp_mux_001
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_mux.sv" -work rsp_mux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -work rsp_mux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_rsp_demux.sv" -work rsp_demux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux_002.sv" -work cmd_mux_002
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -work cmd_mux_002
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_mux.sv" -work cmd_mux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_arbitrator.sv" -work cmd_mux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux_001.sv" -work cmd_demux_001
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_cmd_demux.sv" -work cmd_demux
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_008.sv" -work router_008
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_004.sv" -work router_004
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_002.sv" -work router_002
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router_001.sv" -work router_001
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0_router.sv" -work router
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_sc_fifo.v" -work jtag_uart_avalon_jtag_slave_agent_rsp_fifo
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_agent.sv" -work jtag_uart_avalon_jtag_slave_agent
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv" -work jtag_uart_avalon_jtag_slave_agent
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_agent.sv" -work cpu_data_master_agent
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_slave_translator.sv" -work jtag_uart_avalon_jtag_slave_translator
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_merlin_master_translator.sv" -work cpu_data_master_translator
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_sysclk.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_tck.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_debug_slave_wrapper.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu_cpu_test_bench.v" -work cpu
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_controller.v" -work rst_controller
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_reset_synchronizer.v" -work rst_controller
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_irq_mapper.sv" -work irq_mapper
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mm_interconnect_0.v" -work mm_interconnect_0
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_sys_clk_timer.v" -work sys_clk_timer
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/dec.sv" -work sem
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/periodram.v" -work sem
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_mem.v" -work mem
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_jtag_uart.v" -work jtag_uart
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII_cpu.v" -work cpu
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv" -work niosII_inst_reset_bfm
vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv" -work niosII_inst_clk_bfm
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/submodules/niosII.v" -work niosII_inst
vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/niosII_tb/simulation/niosII_tb.v"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi

37
Top/niosII_tb.csv Normal file
View File

@ -0,0 +1,37 @@
# system info niosII_tb on 2023.01.27.19:00:20
system_info:
name,value
DEVICE,EP4CE115F29C7
DEVICE_FAMILY,Cyclone IV E
GENERATION_ID,1674831618
#
#
# Files generated for niosII_tb on 2023.01.27.19:00:20
files:
filepath,kind,attributes,module,is_top
niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
niosII_tb.niosII_inst,niosII
niosII_tb.niosII_inst.cpu,niosII_cpu
niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
niosII_tb.niosII_inst.mem,niosII_mem
niosII_tb.niosII_inst.sigdel_0,niosII_sigdel_0
niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
niosII_tb.niosII_inst.rst_controller,altera_reset_controller
niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source
1 # system info niosII_tb on 2023.01.27.19:00:20
2 system_info:
3 name,value
4 DEVICE,EP4CE115F29C7
5 DEVICE_FAMILY,Cyclone IV E
6 GENERATION_ID,1674831618
7 #
8 #
9 # Files generated for niosII_tb on 2023.01.27.19:00:20
10 files:
11 filepath,kind,attributes,module,is_top
12 niosII/testbench/niosII_tb/simulation/niosII_tb.v,VERILOG,,niosII_tb,true
13 niosII/testbench/niosII_tb/simulation/submodules/niosII.v,VERILOG,,niosII,false
14 niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
15 niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
16 niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
17 niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
18 niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v,VERILOG,,niosII_cpu,false
19 niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v,VERILOG,,niosII_jtag_uart,false
20 niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex,HEX,,niosII_mem,false
21 niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v,VERILOG,,niosII_mem,false
22 #
23 # Map from instance-path to kind of module
24 instances:
25 instancePath,module
26 niosII_tb.niosII_inst,niosII
27 niosII_tb.niosII_inst.cpu,niosII_cpu
28 niosII_tb.niosII_inst.cpu.cpu,niosII_cpu_cpu
29 niosII_tb.niosII_inst.jtag_uart,niosII_jtag_uart
30 niosII_tb.niosII_inst.mem,niosII_mem
31 niosII_tb.niosII_inst.sigdel_0,niosII_sigdel_0
32 niosII_tb.niosII_inst.sys_clk_timer,niosII_sys_clk_timer
33 niosII_tb.niosII_inst.mm_interconnect_0,niosII_mm_interconnect_0
34 niosII_tb.niosII_inst.irq_mapper,niosII_irq_mapper
35 niosII_tb.niosII_inst.rst_controller,altera_reset_controller
36 niosII_tb.niosII_inst_clk_bfm,altera_avalon_clock_source
37 niosII_tb.niosII_inst_reset_bfm,altera_avalon_reset_source

44
Top/niosII_tb.spd Normal file
View File

@ -0,0 +1,44 @@
<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="niosII/testbench/niosII_tb/simulation/submodules/verbosity_pkg.sv"
type="SYSTEM_VERILOG"
library="altera_common_sv_packages"
systemVerilogPackageName="avalon_vip_verbosity_pkg" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.hex"
type="HEX"
library="mem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_mem.v"
type="VERILOG"
library="mem" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_jtag_uart.v"
type="VERILOG"
library="jtag_uart" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII_cpu.v"
type="VERILOG"
library="cpu" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_reset_source.sv"
type="SYSTEM_VERILOG"
library="niosII_inst_reset_bfm" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/altera_avalon_clock_source.sv"
type="SYSTEM_VERILOG"
library="niosII_inst_clk_bfm" />
<file
path="niosII/testbench/niosII_tb/simulation/submodules/niosII.v"
type="VERILOG"
library="niosII_inst" />
<file
path="niosII/testbench/niosII_tb/simulation/niosII_tb.v"
type="VERILOG" />
<topLevel name="niosII_tb" />
<deviceFamily name="cycloneive" />
<modelMap
controllerPath="niosII_tb.niosII_inst.mem"
modelPath="niosII_tb.niosII_inst.mem" />
</simPackage>

60
Top/semafor.qpf
View File

@ -1,30 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:34:55 October 18, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "16:34:55 October 18, 2022"
# Revisions
PROJECT_REVISION = "semafor"
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:34:55 October 18, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.1"
DATE = "16:34:55 October 18, 2022"
# Revisions
PROJECT_REVISION = "semafor"

95
Top/semafor.qsf
View File

@ -1,44 +1,44 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:34:55 October 18, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# semafor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 16:34:55 October 18, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# semafor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY niosII
set_global_assignment -name DEVICE EP4CE15F23C8
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:34:55 OCTOBER 18, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
@ -46,14 +46,21 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name QSYS_FILE niosII.qsys
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE top.sv
set_global_assignment -name QIP_FILE niosII/synthesis/niosII.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to clk
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_location_assignment PIN_T2 -to CLOCK_50
set_location_assignment PIN_E3 -to LEDG[0]
set_location_assignment PIN_C21 -to FOUTA
set_location_assignment PIN_E4 -to nreset
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

808
Top/semafor_assignment_defaults.qdf Normal file
View File

@ -0,0 +1,808 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 11:08:42 January 24, 2023
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus Prime software and is used
# to preserve global assignments across Quartus Prime versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
set_global_assignment -name IP_COMPONENT_INTERNAL Off
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base -family "Arria V"
set_global_assignment -name REVISION_TYPE Base -family "Stratix V"
set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ"
set_global_assignment -name REVISION_TYPE Base -family "Cyclone V"
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name OPTIMIZATION_MODE Balanced
set_global_assignment -name ALLOW_REGISTER_MERGING On
set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX"
set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V"
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name OCP_HW_EVAL Enable
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
set_global_assignment -name PRPOF_ID Off
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name PHYSICAL_SYNTHESIS Off
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V"
set_global_assignment -name VID_OPERATION_MODE "PMBus Slave"
set_global_assignment -name USE_CONF_DONE AUTO
set_global_assignment -name USE_PWRMGT_SCL AUTO
set_global_assignment -name USE_PWRMGT_SDA AUTO
set_global_assignment -name USE_PWRMGT_ALERT AUTO
set_global_assignment -name USE_INIT_DONE AUTO
set_global_assignment -name USE_CVP_CONFDONE AUTO
set_global_assignment -name USE_SEU_ERROR AUTO
set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name ENABLE_CONFIGURATION_PINS On
set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
set_global_assignment -name ENABLE_NCE_PIN Off
set_global_assignment -name ENABLE_BOOT_SEL_PIN On
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF
set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name RESERVE_PR_PINS Off
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0
set_global_assignment -name SEU_FIT_REPORT Off
set_global_assignment -name HYPER_RETIMER Off -family "Arria 10"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery"
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP"
set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
set_global_assignment -name POR_SCHEME "Instant ON"
set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
set_global_assignment -name POF_VERIFY_PROTECT Off
set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
set_global_assignment -name GENERATE_PMSF_FILES On
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name HPS_EARLY_IO_RELEASE Off
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

143
Top/sigdel_hw.tcl Normal file
View File

@ -0,0 +1,143 @@
# TCL File Generated by Component Editor 18.1
# Tue Feb 07 16:48:35 MSK 2023
# DO NOT MODIFY
#
# sigdel "Sigma-Delta Modulator" v1.0
# 2023.02.07.16:48:35
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module sigdel
#
set_module_property DESCRIPTION ""
set_module_property NAME sigdel
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "User Logic"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "Sigma-Delta Modulator"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL sigdel
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file phacc.sv SYSTEM_VERILOG PATH ../HDL/phacc.sv
add_fileset_file sdmod.sv SYSTEM_VERILOG PATH ../HDL/sdmod.sv
add_fileset_file sigdel.sv SYSTEM_VERILOG PATH ../HDL/sigdel.sv TOP_LEVEL_FILE
add_fileset_file sinelut.v VERILOG PATH ../HDL/IP/sinelut.v
add_fileset_file sine256.mif MIF PATH ../HDL/IP/sine256.mif
#
# parameters
#
add_parameter PHACC_WIDTH INTEGER 14
set_parameter_property PHACC_WIDTH DEFAULT_VALUE 14
set_parameter_property PHACC_WIDTH DISPLAY_NAME PHACC_WIDTH
set_parameter_property PHACC_WIDTH TYPE INTEGER
set_parameter_property PHACC_WIDTH UNITS None
set_parameter_property PHACC_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property PHACC_WIDTH HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset_sink
#
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
add_interface_port reset_sink clr_n reset_n Input 1
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock ""
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end fout writeresponsevalid_n Output 1
#
# connection point avalon_slave
#
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock
set_interface_property avalon_slave associatedReset reset_sink
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits WORDS
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 0
set_interface_property avalon_slave readWaitTime 1
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
set_interface_property avalon_slave ENABLED true
set_interface_property avalon_slave EXPORT_OF ""
set_interface_property avalon_slave PORT_NAME_MAP ""
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave wr_n write_n Input 1
add_interface_port avalon_slave wr_data writedata Input 32
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0

143
Top/sigdel_hw.tcl~ Normal file
View File

@ -0,0 +1,143 @@
# TCL File Generated by Component Editor 18.1
# Fri Jan 27 18:48:38 MSK 2023
# DO NOT MODIFY
#
# sigdel "Sigma-Delta Modulator" v1.0
# 2023.01.27.18:48:38
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module sigdel
#
set_module_property DESCRIPTION ""
set_module_property NAME sigdel
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "User Logic"
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "Sigma-Delta Modulator"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL sigdel
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file phacc.sv SYSTEM_VERILOG PATH ../HDL/phacc.sv
add_fileset_file sdmod.sv SYSTEM_VERILOG PATH ../HDL/sdmod.sv
add_fileset_file sigdel.sv SYSTEM_VERILOG PATH ../HDL/sigdel.sv TOP_LEVEL_FILE
add_fileset_file sinelut.v VERILOG PATH ../HDL/IP/sinelut.v
add_fileset_file sine256.mif MIF PATH ../HDL/IP/sine256.mif
#
# parameters
#
add_parameter PHACC_WIDTH INTEGER 14
set_parameter_property PHACC_WIDTH DEFAULT_VALUE 14
set_parameter_property PHACC_WIDTH DISPLAY_NAME PHACC_WIDTH
set_parameter_property PHACC_WIDTH TYPE INTEGER
set_parameter_property PHACC_WIDTH UNITS None
set_parameter_property PHACC_WIDTH ALLOWED_RANGES -2147483648:2147483647
set_parameter_property PHACC_WIDTH HDL_PARAMETER true
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset_sink
#
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
add_interface_port reset_sink clr_n reset_n Input 1
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock ""
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end fout writeresponsevalid_n Output 1
#
# connection point avalon_slave
#
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock
set_interface_property avalon_slave associatedReset reset_sink
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits WORDS
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 0
set_interface_property avalon_slave readWaitTime 1
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
set_interface_property avalon_slave ENABLED true
set_interface_property avalon_slave EXPORT_OF ""
set_interface_property avalon_slave PORT_NAME_MAP ""
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave wr_n write_n Input 1
add_interface_port avalon_slave wr_data writedata Input 32
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0

40
Top/software/ci_project/.project Normal file
View File

@ -0,0 +1,40 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>ci_project</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>com.altera.sbtgui.project.SBTGUINature</nature>
<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
</natures>
</projectDescription>

90
Top/software/deltasigma/.cproject Normal file
View File

@ -0,0 +1,90 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505">
<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505" moduleId="org.eclipse.cdt.core.settings"/>
</buildSystem>
<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505">
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505." name="/" resourcePath="">
<toolChain id="altera.nios2.linux.gcc4.369748947" name="Linux Nios II GCC4" superClass="altera.nios2.linux.gcc4">
<targetPlatform id="altera.nios2.linux.gcc4.1270664660" name="Nios II" osList="linux" superClass="altera.nios2.linux.gcc4"/>
<builder buildPath="${workspace_loc://deltasigma}" id="altera.tool.gnu.builder.1746673051" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder"/>
<tool id="altera.tool.gnu.c.compiler.754191929" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler">
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.872290592" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.cpp.compiler.1100567708" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler">
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1394337200" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.archiver.1341986491" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver"/>
<tool id="altera.tool.gnu.c.linker.1132604299" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker"/>
<tool id="altera.tool.gnu.cpp.linker.395670393" name="Nios II GCC C++ Linker" superClass="altera.tool.gnu.cpp.linker">
<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.179960318" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
</inputType>
</tool>
<tool id="altera.tool.gnu.assembler.453471012" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler">
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.616300943" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
</tool>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="deltasigma.null.2123671809" name="deltasigma"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505.;altera.tool.gnu.cpp.compiler.1100567708;cdt.managedbuild.tool.gnu.cpp.compiler.input.1394337200">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1535533505.;altera.tool.gnu.c.compiler.754191929;cdt.managedbuild.tool.gnu.c.compiler.input.872290592">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
<buildTargets>
<target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>mem_init_install</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
<target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>mem_init_generate</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
<target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>help</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
</buildTargets>
</storageModule>
</cproject>

40
Top/software/deltasigma/.project Normal file
View File

@ -0,0 +1,40 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>deltasigma</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>com.altera.sbtgui.project.SBTGUINature</nature>
<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
</natures>
</projectDescription>

1081
Top/software/deltasigma/Makefile Normal file
View File

File diff suppressed because it is too large Load Diff

BIN
Top/software/deltasigma/deltasigma.elf Normal file
View File

Binary file not shown.

1631
Top/software/deltasigma/deltasigma.map Normal file
View File

File diff suppressed because it is too large Load Diff

6133
Top/software/deltasigma/deltasigma.objdump Normal file
View File

File diff suppressed because it is too large Load Diff

22
Top/software/deltasigma/main.c Normal file
View File

@ -0,0 +1,22 @@
/*
* main.c
*
*
* Created on: Feb 7, 2023
* Author: ovchinnikov_ii@RISDE.ru
*/
#include <stdio.h>
#include "alt_types.h"
#include "system.h"
#include "io.h"
#define IOWR_DELSIG_CTL(base, data) IOWR(base, 0, data)
int main() {
IOWR_DELSIG_CTL(SIGDEL_0_BASE, 0x2000);
printf("Ready\n");
while (1) {}
return 0;
}

83
Top/software/semafor/.cproject Normal file
View File

@ -0,0 +1,83 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672">
<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" moduleId="org.eclipse.cdt.core.settings"/>
</buildSystem>
<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672">
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672." name="/" resourcePath="">
<toolChain id="altera.nios2.mingw.gcc4.1451739338" name="MinGW Nios II GCC4" superClass="altera.nios2.mingw.gcc4">
<targetPlatform id="altera.nios2.mingw.gcc4.1894897402" name="Nios II" superClass="altera.nios2.mingw.gcc4"/>
<builder buildPath="${workspace_loc://semafor}" id="altera.tool.gnu.builder.mingw.1910544022" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder.mingw"/>
<tool id="altera.tool.gnu.c.compiler.mingw.2112423510" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.181439709" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.cpp.compiler.mingw.1092618596" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.693221313" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool>
<tool id="altera.tool.gnu.archiver.mingw.1773720286" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver.mingw"/>
<tool id="altera.tool.gnu.c.linker.mingw.544112231" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker.mingw"/>
<tool id="altera.tool.gnu.assembler.mingw.273557530" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler.mingw">
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.327317275" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
</tool>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="semafor.null.1915366667" name="semafor"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672.;altera.tool.gnu.c.compiler.mingw.2112423510;cdt.managedbuild.tool.gnu.c.compiler.input.181439709">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1595682672.;altera.tool.gnu.cpp.compiler.mingw.1092618596;cdt.managedbuild.tool.gnu.cpp.compiler.input.693221313">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
<buildTargets>
<target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>mem_init_install</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
<target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>mem_init_generate</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
<target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
<buildTarget>help</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>false</useDefaultCommand>
<runAllBuilders>false</runAllBuilders>
</target>
</buildTargets>
</storageModule>
</cproject>

40
Top/software/semafor/.project Normal file
View File

@ -0,0 +1,40 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>semafor</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.altera.sbtgui.project.makefileBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>com.altera.sbtgui.project.SBTGUINature</nature>
<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
</natures>
</projectDescription>

1082
Top/software/semafor/Makefile Normal file
View File

File diff suppressed because it is too large Load Diff

BIN
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.elf Normal file
View File

Binary file not shown.

1646
Top/software/semafor/RUN_ON_HDL_SIMULATOR_ONLY_semafor.map Normal file
View File

File diff suppressed because it is too large Load Diff

Some files were not shown because too many files have changed in this diff Show More